TL/F/11616
74LVX573
Low
Voltage
Octal
Latch
with
TRI-STATE
Outputs
October 1995
74LVX573
Low Voltage Octal Latch with TRI-STATE
É
Outputs
General Description
The LVX573 is a high-speed octal latch with buffered com-
mon Latch Enable (LE) and buffered common Output En-
able (OE) inputs. The LVX573 is functionally identical to the
LVX373 but with inputs and outputs on opposite sides of the
package. The inputs tolerate up to 7V allowing interface of
5V systems to 3V systems.
Features
Y
Input voltage translation from 5V to 3V
Y
Ideal for low power/low noise 3.3V applications
Y
Available in SOIC JEDEC, SOIC EIAJ, TSSOP and
SSOP packages
Y
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Logic Symbols
Connection Diagram
TL/F/11616 – 1
IEEE/IEC
TL/F/11616 – 4
Pin Assignment for
SOIC, SSOP and TSSOP
TL/F/11616 – 2
Pin Names
Description
D
0
– D
7
Data Inputs
LE
Latch Enable Input
OE
TRI-STATE Output Enable Input
O
0
– O
7
TRI-STATE Latch Outputs
SOIC JEDEC
SOIC EIAJ
SSOP TYPE 1
TSSOP
Order Number
74LVX573M
74LVX573SJ
74LVX573MTC
74LVX573MX
74LVX573SJX
74LVX573MSCX
74LVX573MTCX
See NS Package Number
M20B
M20D
MSC20
MTC20
TRI-STATE
É
is a registered trademark of National Semiconductor Corporation.
C1995 National Semiconductor Corporation
RRD-B30M115/Printed in U. S. A.
Functional Description
The
LVX573
contains
eight
D-type
latches
with
TRI-STATE
É
output buffers. When the Latch Enable (LE)
input is HIGH, data on the D
n
inputs enters the latches. In
this condition the latches are transparent, i.e., a latch output
will change state each time its D input changes. When LE is
LOW the latches store the information that was present on
the D inputs a setup time preceding the HIGH-to-LOW tran-
sition of LE. The TRI-STATE
É
buffers are controlled by the
Output Enable (OE) input. When OE is LOW, the buffers are
enabled. When OE is HIGH the buffers are in the high im-
pedance mode but this does not interfere with entering new
data into the latches.
Truth Table
Inputs
Outputs
OE
LE
D
O
n
L
H
H
H
L
H
L
L
L
L
X
O
0
H
X
X
Z
H e HIGH Voltage
L e LOW Voltage
Z e High Impedance
X e Immaterial
O
0
e
Previous O
0
before HIGH-to-LOW transition of Latch Enable
Logic Diagram
TL/F/11616 – 3
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
2
Absolute Maximum Rating
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
CC
)
b
0.5V to
a
7.0V
DC Input Diode Current (I
IK
)
V
I
e b
0.5V
b
20 mA
DC Input Voltage (V
I
)
b
0.5V to 7V
DC Output Diode Current (I
OK
)
V
O
e b
0.5V
b
20 mA
V
O
e
V
CC
a
0.5V
a
20 mA
DC Output Voltage (V
O
)
b
0.5V to V
CC
a
0.5V
DC Output Source
or Sink Current (I
O
)
g
25 mA
DC V
CC
or Ground Current (I
CC
or I
GND
)
g
75 mA
Storage Temperature (T
STG
)
b
65
§
C to
a
150
§
C
Power Dissipation
180 mW
Note:
The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed. The device should not be operated at these limits. The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation.
Recommended Operating
Conditions
Supply Voltage (V
CC
)
2.0V to 3.6V
Input Voltage (V
I
)
0V to 5.5V
Output Voltage (V
O
)
0V to V
CC
Operating Temperature (T
A
)
b
40
§
C to
a
85
§
C
Input Rise and Fall Time (Dt/DV)
0 ns/V to 100 ns/V
DC Electrical Characteristics
Symbol
Parameter
V
CC
74LVX573
74LVX573
Units
Conditions
T
A
e a
25
§
C
T
A
e
b
40
§
C to
a
85
§
C
Min
Typ
Max
Min
Max
V
IH
High Level
2.0
1.5
1.5
Input
3.0
2.0
2.0
V
Voltage
3.6
2.4
2.4
V
IL
Low Level
2.0
0.5
0.5
Input
3.0
0.8
0.8
V
Voltage
3.6
0.8
0.8
V
OH
High Level
2.0
1.9
2.0
1.9
V
IN
e
V
IH
or V
IL
I
OH
e b
50 mA
Output
3.0
2.9
3.0
2.9
V
I
OH
e b
50 mA
Voltage
3.0
2.58
2.48
I
OH
e b
4 mA
V
OL
Low Level
2.0
0.0
0.1
0.1
V
IN
e
V
IH
or V
IL
I
OL
e
50 mA
Output
3.0
0.0
0.1
0.1
V
I
OL
e
50 mA
Voltage
3.0
0.36
0.44
I
OL
e
4 mA
I
OZ
TRI-STATE
3.6
g
0.25
g
2.5
m
A
V
IN
e
V
IH
or V
IL
Output
V
OUT
e
V
CC
or GND
Off-State
Current
I
IN
Input
3.6
g
0.1
g
1.0
m
A
V
IN
e
5.5V or GND
Leakage
Current
I
CC
Quiescent
3.6
4.0
40.0
m
A
V
IN
e
V
CC
or GND
Supply
Current
3
Noise Characteristics
Symbol
Parameter
V
CC
(V)
74LVX573
Units
C
L
(pF)
T
A
e
25
§
C
Typ
Limit
V
OLP
Quiet Output Maximum Dynamic V
OL
3.3
0.5
0.8
V
50
V
OLV
Quiet Output Minimum Dynamic V
OL
3.3
b
0.5
b
0.8
V
50
V
IHD
Minimum High Level Dynamic Input Voltage
3.3
2.0
V
50
V
ILD
Maximum Low Level Dynamic Input Voltage
3.3
0.8
V
50
Note:
(Input t
r
e
t
f
e
3 ns)
AC Electrical Characteristics
Symbol
Parameter
V
CC
(V)
74LVX573
74LVX573
Units
Conditions
T
A
e a
25
§
C
T
A
e
b
40
§
C to
a
85
§
C
Min
Typ
Max
Min
Max
t
PLH
Propagation
2.7
7.6
14.5
1.0
17.5
ns
C
L
e
15 pF
t
PHL
Delay Time
10.1
18.0
1.0
21.0
C
L
e
50 pF
D
n
to O
n
3.3
g
0.3
5.9
9.3
1.0
11.0
C
L
e
15 pF
8.4
12.8
1.0
14.5
C
L
e
50 pF
t
PLH
Propagation
2.7
8.2
15.6
1.0
18.5
ns
C
L
e
15 pF
t
PHL
Delay Time
10.7
19.1
1.0
22.0
C
L
e
50 pF
LE to O
n
3.3
g
0.3
6.4
10.1
1.0
12.0
C
L
e
15 pF
8.9
13.6
1.0
15.5
C
L
e
50 pF
t
PZL
TRI-STATE
É
Output
2.7
7.8
15.0
1.0
18.5
ns
C
L
e
15 pF, R
L
e
1 kX
t
PZH
Enable Time
10.3
18.5
1.0
22.0
C
L
e
50 pF, R
L
e
1 kX
3.3
g
0.3
6.1
9.7
1.0
12.0
C
L
e
15 pF, R
L
e
1 kX
8.6
13.2
1.0
15.5
C
L
e
50 pF, R
L
e
1 kX
t
PHZ
t
PLZ
Disable Time
TRI-STATE
É
Output
2.7
12.1
19.1
1.0
22.0
ns
C
L
e
50 pF, R
L
e
1 kX
3.3
g
0.3
10.1
13.6
1.0
15.5
C
L
e
50 pF, R
L
e
1 kX
t
W
Width
LE Pulse
2.7
6.5
7.5
ns
3.3
g
0.3
5.0
5.0
t
S
D
n
to LE
Setup Time
2.7
5.0
5.0
ns
3.3
g
0.3
3.5
3.5
t
H
D
n
to LE
Hold Time
2.7
1.5
1.5
ns
3.3
g
0.3
1.5
1.5
t
OSHL
Output to Output
2.7
1.5
1.5
ns
C
L
e
50 pF
t
OSLH
Skew (Note 1)
Note 1:
Parameter guaranteed by design. t
OSLH
e
l
t
PLHm
b
t
PLHn
l
, t
OSHL
e
l
t
PHLm
b
t
PHLn
l
.
4
Capacitance
Symbol
Parameter
74LVX573
74LVX573
Units
T
A
e a
25
§
C
T
A
e b
40
§
C to
a
85
§
C
Min
Typ
Max
Min
Max
C
IN
Input Capacitance
4
10
10
pF
C
OUT
Output Capacitance
6
pF
C
PD
Power Dissipation
27
pF
Capacitance (Note 1)
Note 1:
C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption
without load.
Average operating current can be obtained by the equation: I
CC(opr.)
e
C
PD
c
V
CC
c
f
IN
a
I
CC
8 (per latch)
5
74LVX573 Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
TL/F/11616 – 5
Physical Dimensions
inches (millimeters)
20-Lead Small Outline Integrated Circuit (M)
Order Number 74LVX573M or 74LVX573MX
NS Package Number M20B
6
Physical Dimensions
inches (millimeters) (Continued)
20-Lead Small Outline Package EIAJ SOIC (SJ)
Order Number 74LVX573SJ or 74LVX573SJX
NS Package Number M20D
All dimensions in millimeters
20-Lead Plastic EIAJ SSOP Type I (MSC)
Order Number 74LVX573MSCX
NS Package Number MSC20
7
74LVX573
Low
Voltage
Octal
Latch
with
TRI-STATE
Outputs
Physical Dimensions
inches (millimeters) (Continued)
20-Lead Thin Shrink Small Outline Package, JEDEC
Order Number 74LVX573MTC or 74LVX573MTCX
NS Package Number MTC20
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failure to perform, when properly used in accordance
support device or system, or to affect its safety or
with instructions for use provided in the labeling, can
effectiveness.
be reasonably expected to result in a significant injury
to the user.
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