2015 Microchip Technology Inc.
DS20005291A-page 1
1.0
PRODUCT DESCRIPTION
The 25 series Serial Flash family features a four-wire,
SPI-compatible interface that allows for a low pin-count
package which occupies less board space and ulti-
mately lowers total system costs. The SST25VF016B
devices are enhanced with improved operating fre-
quency and even lower power consumption than the
original SST25VFxxxA devices. SST25VF016B SPI
serial flash memories are manufactured with propri-
etary, high-performance CMOS SuperFlash technol-
ogy. The split-gate cell design and thick-oxide tunneling
injector attain better reliability and manufacturability
compared with alternate approaches.
This document provides supplemental information
about the 75/80 MHz parts which are End-of-Life
(EOL). Except for the information provided herein, the
EOL parts behave as described in the SST25VF016B
data sheet DS-20005044. See
page 6
for specific part
numbers.
2.0
DEVICE OPERATION
2.1
Instructions
Instructions are used to read, write (Erase and Pro-
gram), and configure the SST25VF016B. The instruc-
tion bus cycles are 8 bits each for commands (Op
Code), data, and addresses. Prior to executing any
Byte-Program, Auto Address Increment (AAI) program-
ming, Sector-Erase, Block-Erase, Write-Status-Regis-
ter, or Chip-Erase instructions, the Write-Enable
(WREN) instruction must be executed first. The com-
plete list of instructions is provided in
Table 2-1
. All
instructions are synchronized off a high to low transition
of CE#. Inputs will be accepted on the rising edge of
SCK starting with the most significant bit. CE# must be
driven low before an instruction is entered and must be
driven high after the last bit of the instruction has been
shifted in (except for Read, Read-ID, and Read-Status-
Register instructions). Any low to high transition on
CE#, before receiving the last bit of an instruction bus
cycle, will terminate the instruction in progress and
return the device to standby mode. Instruction com-
mands (Op Code), addresses, and data are all input
from the most significant bit (MSB) first.
TABLE 2-1:
DEVICE OPERATION INSTRUCTIONS
Instruction
Description
Op Code Cycle
1
Address
Cycle(s)
2
Dummy
Cycle(s)
Data
Cycle(s)
Maximum
Frequency
Read
Read Memory at 25 MHz
0000 0011b (03H)
3
0
1 to
25 MHz
High-Speed
Read
Read Memory at 80 MHz
0000 1011b (0BH)
3
1
1 to
80 MHz
4 KByte Sector-
Erase
3
Erase 4 KByte of
memory array
0010 0000b (20H)
3
0
0
80 MHz
32 KByte Block-
Erase
4
Erase 32 KByte block
of memory array
0101 0010b (52H)
3
0
0
80 MHz
64 KByte Block-
Erase
5
Erase 64 KByte block
of memory array
1101 1000b (D8H)
3
0
0
80 MHz
Chip-Erase
Erase Full Memory Array
0110 0000b (60H) or
1100 0111b (C7H)
0
0
0
80 MHz
Byte-Program
To Program One Data Byte
0000 0010b (02H)
3
0
1
80 MHz
AAI-Word-Pro-
gram
6
Auto Address Increment
Programming
1010 1101b (ADH)
3
0
2 to
80 MHz
RDSR
7
Read-Status-Register
0000 0101b (05H)
0
0
1 to
80 MHz
EWSR
Enable-Write-Status-Register
0101b 0000b (50H)
0
0
0
80 MHz
WRSR
Write-Status-Register
0000 0001b (01H)
0
0
1
80 MHz
SST25VF016B
16 Mbit SPI Serial Flash
EOL Supplemental Information
SST25VF016B
DS20005291A-page 2
2015 Microchip Technology Inc.
2.1.1
HIGH-SPEED-READ (80 MHZ)
The High-Speed-Read instruction supporting up to 80
MHz Read is initiated by executing an 8-bit command,
0BH, followed by address bits [A
23
-A
0
] and a dummy
byte. CE# must remain active low for the duration of the
High-Speed-Read cycle. See
Figure 2-1
for the High-
Speed-Read sequence.
Following a dummy cycle, the High-Speed-Read
instruction outputs the data starting from the specified
address location. The data output stream is continuous
through all addresses until terminated by a low to high
transition on CE#. The internal address pointer will
automatically increment until the highest memory
address is reached. Once the highest memory address
is reached, the address pointer will automatically incre-
ment to the beginning (wrap-around) of the address
space. Once the data from address location 1FFFFFH
has been read, the next output will be from address
location 000000H.
FIGURE 2-1:
HIGH-SPEED-READ SEQUENCE
WREN
Write-Enable
0000 0110b (06H)
0
0
0
80 MHz
WRDI
Write-Disable
0000 0100b (04H)
0
0
0
80 MHz
RDID
8
Read-ID
1001 0000b (90H) or
1010 1011b (ABH)
3
0
1 to
80 MHz
JEDEC-ID
JEDEC ID read
1001 1111b (9FH)
0
0
3 to
80 MHz
EBSY
Enable SO to output RY/BY#
status during AAI program-
ming
0111 0000b (70H)
0
0
0
80 MHz
DBSY
Disable SO as RY/BY#
status during AAI program-
ming
1000 0000b (80H)
0
0
0
80 MHz
0
25044
1. One bus cycle is eight clock periods.
2. Address bits above the most significant bit of each density can be V
IL
or V
IH
.
3. 4KByte Sector Erase addresses: use A
MS
-A
12,
remaining addresses are don’t care but must be set either at V
IL
or V
IH.
4. 32KByte Block Erase addresses: use A
MS
-A
15,
remaining addresses are don’t care but must be set either at V
IL
or V
IH.
5. 64KByte Block Erase addresses: use A
MS
-A
16,
remaining addresses are don’t care but must be set either at V
IL
or V
IH.
6. To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by 2 bytes of data
to be programmed. Data Byte 0 will be programmed into the initial address [A
23
-A
1
] with A
0
=0, Data Byte 1 will be pro-
grammed into the initial address [A
23
-A
1
] with A
0
=1.
7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
8. Manufacturer’s ID is read with A
0
=0, and Device ID is read with A
0
=1. All other address bits are 00H. The Manufacturer’s ID
and device ID output stream is continuous until terminated by a low-to-high transition on CE#.
TABLE 2-1:
DEVICE OPERATION INSTRUCTIONS
Instruction
Description
Op Code Cycle
1
Address
Cycle(s)
2
Dummy
Cycle(s)
Data
Cycle(s)
Maximum
Frequency
1271 HSRdSeq.0
CE#
SO
SI
SCK
ADD.
0 1 2 3 4 5
6 7 8
ADD.
ADD.
0B
HIGH IMPEDANCE
15 16
23 24
31 32
39 40
47 48
55 56
63 64
N+2
N+3
N+4
N
N+1
X
MSB
MSB
MSB
MODE 0
MODE 3
D
OUT
D
OUT
D
OUT
D
OUT
80
71 72
D
OUT
Note: X = Dummy Byte: 8 Clocks Input Dummy Cycle (V
IL
or V
IH
)
2015 Microchip Technology Inc.
DS20005291A-page 3
SST25VF016B
3.0
ELECTRICAL SPECIFICATIONS
TABLE 3-1:
DC OPERATING CHARACTERISTICS
Symbol
Parameter
Limits
Test Conditions
Min
Max
Units
I
DDR
Read Current
10
mA
CE#=0.1 V
DD
/0.9 V
DD
@25 MHz, SO=open
I
DDR2
Read Current
15
mA
CE#=0.1 V
DD
/0.9 V
DD
@50 MHz, SO=open
I
DDR3
Read Current
20
mA
CE#=0.1 V
DD
/0.9 V
DD
@80 MHz, SO=open
I
DDW
Program and Erase Current
30
mA
CE#=V
DD
I
SB
Standby Current
20
µA
CE#=V
DD
, V
IN
=V
DD
or V
SS
I
LI
Input Leakage Current
1
µA
V
IN
=GND to V
DD
, V
DD
=V
DD
Max
I
LO
Output Leakage Current
1
µA
V
OUT
=GND to V
DD
, V
DD
=V
DD
Max
V
IL
Input Low Voltage
0.8
V
V
DD
=V
DD
Min
V
IH
Input High Voltage
0.7 V
DD
V
V
DD
=V
DD
Max
V
OL
Output Low Voltage
0.2
V
I
OL
=100 µA, V
DD
=V
DD
Min
V
OL2
Output Low Voltage
0.4
V
I
OL
=1.6 mA, V
DD
=V
DD
Min
V
OH
Output High Voltage
V
DD
-0.2
V
I
OH
=-100 µA, V
DD
=V
DD
Min
TABLE 3-2:
AC OPERATING CHARACTERISTICS
Symbol
Parameter
80 MHz
Min
Max
Units
F
CLK
1
1. Maximum clock frequency for Read Instruction, 03H, is 25 MHz
Serial Clock Frequency
80
MHz
T
SCKH
Serial Clock High Time
6
ns
T
SCKL
Serial Clock Low Time
6
ns
T
SCKR
2
2. Maximum Rise and Fall time may be limited by T
SCKH
and T
SCKL
requirements
Serial Clock Rise Time (Slew Rate)
0.1
V/ns
T
SCKF
Serial Clock Fall Time (Slew Rate)
0.1
V/ns
T
CES
3
3. Relative to SCK.
CE# Active Setup Time
5
ns
T
CEH
3
CE# Active Hold Time
5
ns
T
CHS
3
CE# Not Active Setup Time
5
ns
T
CHH
3
CE# Not Active Hold Time
5
ns
T
CPH
CE# High Time
50
ns
T
CHZ
CE# High to High-Z Output
7
ns
T
CLZ
SCK Low to Low-Z Output
0
ns
T
DS
Data In Setup Time
2
ns
T
DH
Data In Hold Time
4
ns
T
HLS
HOLD# Low Setup Time
5
ns
T
HHS
HOLD# High Setup Time
5
ns
T
HLH
HOLD# Low Hold Time
5
ns
T
HHH
HOLD# High Hold Time
5
ns
T
HZ
HOLD# Low to High-Z Output
7
ns
T
LZ
HOLD# High to Low-Z Output
7
ns
T
OH
Output Hold from SCK Change
0
ns
T
V
Output Valid from SCK
6
ns
T
SE
Sector-Erase
25
ms
T
BE
Block-Erase
25
ms
T
SCE
Chip-Erase
50
ms
T
BP
Byte-Program
10
µs
SST25VF016B
DS20005291A-page 4
2015 Microchip Technology Inc.
TABLE 3-3:
REVISION HISTORY
Revision
Description
Date
A
•
Initial release of EOL data sheet
Apr 2015
2015 Microchip Technology Inc.
DS20005291A-page 5
SST25VF016B
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at
www.microchip.com
. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
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• General Technical Support – Frequently Asked
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Microchip’s customer notification service helps keep
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To register, access the Microchip web site at
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. Under “Support”, click on “Cus-
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CUSTOMER SUPPORT
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
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• Technical Support
Customers should contact their distributor, representa-
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Local sales offices are also available to help custom-
ers. A listing of sales offices and locations is included in
the back of this document.
Technical support is available through the web site
at:
http://microchip.com/support
SST25VF016B
DS20005291A-page 6
2015 Microchip Technology Inc.
4.0
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
XX
XX
Operating
Device
Device:
SST25VF016B
= 16 Mbit, 2.7-3.6V, SPI Flash Memory
Operating
Frequency:
75
= 75 MHz (80 MHz)
Minimum
Endurance
4
= 10,000 cycles
Temperature:
I
= -40°C to +85°C
C
= 0°C to +70°C
Package:
QAE
= WSON (6mm x 5mm Body), 8-lead
S2AE
= SOIC (200 mil Body), 8-lead
Tape and
Reel Flag:
T
= Tape and Reel
Valid Combinations:
SST25VF016B-75-4I-S2AE
SST25VF016B-75-4I-S2AE-T
SST25VF016B-75-4I-QAE
SST25VF016B-75-4I-QAE-T
X
Tape/Reel
Indicator
Frequency
XX
Package
Temp
–
–
–
Range
Minimum
Endurance
–
2015 Microchip Technology Inc.
DS20005291A-page 7
SST25VF016B
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, K
EE
L
OQ
, K
EE
L
OQ
logo, Kleer,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, PICSTART, PIC
32
logo, RightTouch, SpyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo,
MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2015, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
ISBN:978-1-63277-221-3
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
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OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
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QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
==
ISO/TS 16949
==
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
®
MCUs and dsPIC
®
DSCs, K
EE
L
OQ
®
code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
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2015 Microchip Technology Inc.
DS20005291A-page 8
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