2016 Microchip Technology Inc.
DS20005569A-page 1
VP2450
Features
• Free from Secondary Breakdown
• Low Power Drive Requirement
• Ease of Paralleling
• Low C
ISS
and Fast Switching Speeds
• High Input Impedance and High Gain
• Excellent Thermal Stability
• Integral Source-drain Diode
Applications
• Motor Controls
• Converters
• Amplifiers
• Switches
• Power Supply Circuits
• Drivers: Relays, Hammers, Solenoids, Lamps,
Memory, Displays, Bipolar Transistors, etc.
General Description
The VP2450 is a low-threshold, Enhancement-mode
(normally-off) transistor that utilizes a vertical
Double-diffused Metal-Oxide Semiconductor (DMOS)
structure and a well-proven silicon gate manufacturing
process. This combination produces a device with the
power handling capabilities of bipolar transistors and
the high input impedance and positive temperature
coefficient inherent in MOS devices. Characteristic of
all MOS structures, this device is free from thermal
runaway and thermally induced secondary breakdown.
This Vertical DMOS Field-Effect Transistor (FET) is
ideally suited to a wide range of switching and
amplifying applications where very low threshold
voltage, high breakdown voltage, high input
impedance, low input capacitance, and fast switching
speeds are desired.
Package Type
TO-92
GATE
SOURCE
DRAIN
GATE
SOURCE
DRAIN
DRAIN
SOT-89
See
Table 3-1
for pin information.
s
P-Channel Enhancement-Mode Vertical DMOS FET
VP2450
DS20005569A-page 2
2016 Microchip Technology Inc.
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Drain-to-source Voltage.........................................................................................................................................BV
DSS
Drain-to-gate Voltage ............................................................................................................................................BV
DGS
Gate-to-source Voltage ........................................................................................................................................... ±20V
Operating and Storage Temperatures .................................................................................................. –55°C to +150°C
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions above those
indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for
extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
Electrical Specifications: For all specifications, T
A
= T
J
= +25°C unless otherwise noted.
Parameter
Sym.
Min.
Typ.
Max.
Unit
Conditions
DC PARAMETER (
Note 1
unless otherwise stated)
Drain-to-source Breakdown Voltage
BV
DSS
–500
—
—
V
V
GS
= 0V, I
D
= –250 µA
Gate Threshold Voltage
V
GS(th)
–1.5
—
–3.5
V
V
GS
= V
DS
, I
D
= –1 mA
Change in V
GS(th)
with Temperature
∆V
GS(th)
—
—
–4.8
mV/°C V
GS
= V
DS
, I
D
= –1 mA (
Note 2
)
Gate Body Leakage Current
I
GSS
—
—
–100
nA
V
GS
= ±20V, V
DS
= 0V
Zero Gate Voltage Drain Current
I
DSS
—
—
–10
µA
V
GS
= 0V, V
DS
= Maximum Rating
—
—
–1
mA
V
DS
= 0.8 Maximum Rating,
V
GS
= 0V, T
A
= 125°C (
Note 2
)
On-state Drain Current
I
D(ON)
–75
—
—
mA
V
GS
= –4.5V, V
DS
= –15V
–200
—
—
V
GS
= –10V, V
DS
= –15V
Static Drain-to-source On-state
Resistance
R
DS(ON)
—
—
35
Ω
V
GS
= –4.5V, I
D
= –50 mA
—
—
30
V
GS
= –10V, I
D
= –100 mA
Change in R
DS(ON)
with Temperature
∆R
DS(ON)
—
—
0.75
%/°C
V
GS
= –10V, I
D
= –100 mA
(
Note 2
)
AC PARAMETER (
Note 2
)
Forward Transconductance
G
FS
150
320
—
mmho V
DS
= –15V, I
D
= –100 mA
Input Capacitance
C
ISS
—
—
190
pF
V
GS
= 0V, V
DS
= –25V, f = 1 MHz
Common Source Output Capacitance
C
OSS
—
—
75
Reverse Transfer Capacitance
C
RSS
—
—
20
Turn-on Delay Time
t
d(ON)
—
—
10
ns
V
DD
= –25V, I
D
= –200 mA,
R
GEN
= 25Ω
Rise Time
t
r
—
—
25
Turn-off Delay Time
t
d(OFF)
—
—
45
Fall Time
t
f
—
—
25
DIODE PARAMETER
Diode Forward Voltage Drop
V
SD
—
—
–1.8
V
V
GS
= 0V, I
SD
= –100 mA
(
Note 1
)
Reverse Recovery Time
t
rr
—
300
—
ns
V
GS
= 0V, I
SD
= –100 mA
(
Note 2
)
Note 1: All DC parameters are 100% tested at 25°C unless otherwise stated.
(Pulse test: 300 µs pulse, 2% duty cycle)
2: Specification is obtained by characterization and is not 100% tested.
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise noted, for all specifications T
A
=T
J
= +25°C.
Parameter
Sym.
Min.
Typ.
Max.
Unit
Conditions
TEMPERATURE RANGE
Operating Temperature
T
A
–55
—
+150
°C
Storage Temperature
T
S
–55
—
+150
°C
PACKAGE THERMAL RESISTANCE
TO-92
JA
—
132
—
°C/W
SOT-89
JA
—
133
—
°C/W
THERMAL CHARACTERISTICS
Package
I
D
(
Note 1
)
(Continuous)
(mA)
I
D
(Pulsed)
(mA)
Power Dissipation at
T
A
= 25°C
(W)
I
DR
(
Note 1
)
(mA)
I
DRM
(mA)
TO-92
–100
–300
0.74
–100
–300
SOT-89
–160
–800
1.6 (
Note 2
)
–160
–800
Note 1: I
D
(continuous) is limited by maximum T
J
.
2: Mounted on FR5 board, 25 mm x 25 mm X 1.57 mm
2016 Microchip Technology Inc.
DS20005569A-page 3
VP2450
VP2450
DS20005569A-page 4
2016 Microchip Technology Inc.
2.0
TYPICAL PERFORMANCE CURVES
BV
DSS
(normalized)
T
j
(
O
C)
1.2
1.1
1.0
0.9
0.8
-50 0 50 100 150
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g. outside specified power supply range) and therefore outside the warranted range.
FIGURE 2-1:
BV
DSS
Variation with
Temperature.
I
D
(amperes)
V
GS
(volts)
-1.2
-1.0
-0.8
-0.6
-0.4
-0.2
0
0 -1.0 -2.0 -3.0 -4.0
V
DS
= -20V
T
A
= -55
O
C
25
O
C
125
O
C
FIGURE 2-2:
Transfer Characteristics.
C
(picofarads)
V
DS
(volts)
0 -10 -20 -30 -40
400
300
200
100
0
C
OSS
C
ISS
C
RSS
f = 1.0 MHz
FIGURE 2-3:
Capacitance vs.
Drain-to-source Voltage.
FIGURE 2-4:
On-resistance vs. Drain
Current.
0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2
R
DS(ON)
(ohms)
I
D
(amperes)
80
60
40
20
0
V
GS
= -4.5V
V
GS
= -10V
V
GS(th)
(normalized)
T
j
(
O
C)
1.5
1.3
1.1
0.9
0.7
R
DS(ON)
(normalized)
2.2
1.8
1.4
1.0
0.6
V
TH
@ -1.0 mA
R
DS(ON)
@ -10V, -0.1A
-50 0 50 100 150
FIGURE 2-5:
V
GS(th)
and R
DS(ON)
Variation with Temperature.
V
GS
(volts)
Q
G
(nanocoulombs)
0 1.0 2.0 3.0
-10
-8.0
-6.0
-4.0
-2.0
0
I
D
= -100mA
V
DS
= -20V
V
DS
= -40V
FIGURE 2-6:
Gate Drive Dynamic
Characteristics.
2016 Microchip Technology Inc.
DS20005569A-page 5
VP2450
FIGURE 2-7:
I
D
(amperes)
V
DS
(volts)
-1.0
-0.8
-0.6
-0.4
-0.2
0
0 -10 -20 -30 -40 -50
V
GS
= -10V
V
GS
= -4.5V
V
GS
= -3.5V
V
GS
= -6.0V
Output Characteristics.
G
FS
(siemens)
I
D
(milliamperes)
1.0
0.8
0.6
0.4
0.2
0
0 -100 -200 -300 -400 -500
V
DS
= -20V
T
A
= -55
O
C
25
O
C
125
O
C
FIGURE 2-8:
Transconductance vs. Drain
Current.
I
D
(amperes)
V
DS
(volts)
-1.0 -10 -100 -1000
-1.0
-0.1
-0.01
-0.001
TO-243AA (DC)
TO-92 (DC)
TO-243AA (pulsed)
TO-92 (pulsed)
T
A
= 25
O
C
FIGURE 2-9:
Maximum Rated Safe
Operating Area.
FIGURE 2-10:
I
D
(amperes)
V
DS
(volts)
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0 -2.0 -4.0 -6.0 -8.0 -10
V
GS
= -10V
V
GS
= -4.5V
V
GS
= -3.5V
V
GS
= -6.0V
Saturation Characteristics.
P
D
(watts)
T
C
(
O
C)
2.0
1.5
1.0
0.5
0
0 25 50 75 100 125 150
TO-243AA
TO-92
FIGURE 2-11:
Power Dissipation vs. Case
Temperature.
Thermal Resistance
(normalized)
t
P
(seconds)
0.001 0.01 0.1 1.0 10
1.0
0.8
0.6
0.4
0.2
0
TO-243AA
T
A
= 25
O
C
P
D
= 1.6W
TO-92
T
C
= 25
O
C
P
D
= 1.0W
FIGURE 2-12:
Thermal Response
Characteristics.
VP2450
DS20005569A-page 6
2016 Microchip Technology Inc.
3.0
PIN DESCRIPTION
The details on the pins of VP2450 (TO-92 and SOT-89)
are listed on
Table 3-1
. Refer to
Package Types
for the
location of pins.
TABLE 3-1:
PIN FUNCTION TABLE
TO-92
Pin Number
SOT-89
Pin Number
Pin Name
Description
1
3
Source
Source
2
1
Gate
Gate
3
2,4
Drain
Drain
2016 Microchip Technology Inc.
DS20005569A-page 7
VP2450
4.0
FUNCTIONAL DESCRIPTION
Figure 4-1
illustrates the switching waveforms and test
circuit for VP2450.
90%
10%
90%
90%
10%
10%
Pulse
Generator
VDD
R
L
OUTPUT
D.U.T.
t
(ON)
t
d(ON)
t
(OFF)
t
d(OFF)
t
f
t
r
INPUT
R
GEN
INPUT
OUTPUT
0V
VDD
0V
-10V
FIGURE 4-1:
Switching Waveforms and Test Circuit.
PRODUCT SUMMARY
BV
DSS
/BV
DGS
(V)
R
DS(ON)
(Maximum)
(Ω)
I
D(ON)
(Minimum)
(mA)
V
GS(th)
(Maximum)
(V)
–500
30
–200
–0.4
VP2450
DS20005569A-page 8
2016 Microchip Technology Inc.
5.0
PACKAGING INFORMATION
5.1
Package Marking Information
Legend: XX...X
Product Code or Customer-specific information
Y
Year code (last digit of calendar year)
YY
Year code (last 2 digits of calendar year)
WW
Week code (week of January 1 is week ‘01’)
NNN
Alphanumeric traceability code
Pb-free JEDEC
®
designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note:
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for product code or customer-specific information. Package may or
not include the corporate logo.
3
e
3
e
3-lead TO-92
YWWNNN
XXXXXX
XXXX
e3
Example
616343
VP2450
N3
e3
3-lead SOT-89
Example
XXXXYWW
NNN
VP4E612
343
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
2016 Microchip Technology Inc.
DS20005569A-page 9
VP2450
3-Lead TO-243AA (SOT-89) Package Outline (N8)
Symbol
A
b
b1
C
D
D1
E
E1
e
e1
H
L
Dimensions
(mm)
MIN
1.40
0.44
0.36
0.35
4.40
1.62
2.29
2.00
†
1.50
BSC
3.00
BSC
3.94
0.73
†
NOM
-
-
-
-
-
-
-
-
-
-
MAX
1.60
0.56
0.48
0.44
4.60
1.83
2.60
2.29
4.25
1.20
JEDEC Registration TO-243, Variation AA, Issue C, July 1986.
† This dimension differs from the JEDEC drawing
Drawings not to scale.
b
b1
D
D1
E H
E1
C
A
1
2
3
e
e1
Top View
Side View
L
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
VP2450
DS20005569A-page 10
2016 Microchip Technology Inc.