2014-2016 Microchip Technology Inc.
DS00001792E-page 1
Features
• Integrated ESD protection circuits
- Up to ±15kV IEC Air Discharge without exter-
nal devices
• Over-Voltage Protection circuit (OVP) protects the
VBUS pin from continuous DC voltages up to 30V
• Integrated USB Switch
- No degradation of Hi-Speed electrical char-
acteristics
- Allows single USB port of connection by pro-
viding switching function for:
–Battery charging
–Stereo and mono/mic audio
–USB Full-Speed/Low-Speed data
• flexPWR
®
Technology
- Low current design ideal for battery powered
applications
- “Sleep” mode tri-states all ULPI pins and
places the part in a low current state
- 1.8V to 3.3V IO Voltage (±10%)
• Integrated battery to 3.3V regulator
- 2.2uF bypass capacitor
- 100mV dropout voltage
• “Wrapper-less” design for optimal timing perfor-
mance and design ease
- Low Latency Hi-Speed Receiver (43 Hi-
Speed clocks Max) allows use of legacy
UTMI Links with a ULPI bridge
• Selectable Reference Clock Frequency
- Frequencies: 12, 13, 19.2, 24, 26, 27, 38.4,
52 or 60MHz - pin selectable
• External Reference Clock operation available
- ULPI Input Clock Mode (60MHz sourced by
Link)
- 0 to 3.6V input drive tolerant
- Able to accept “noisy” clock sources as refer-
ence to internal, low-jitter PLL
• Internal Oscillator operation available
• This mode requires external Quartz Crystal or
Ceramic Resonator
• Smart detection circuits allow identification of
USB charger, headset, or data cable insertion
• Includes full support for the optional On-The-Go
(OTG) protocol detailed in the On-The-Go Sup-
plement Revision 2.0 specification
• Supports Headset Audio Mode
• Supports the OTG Host Negotiation Protocol
(HNP) and Session Request Protocol (SRP)
• UART mode for non-USB serial data transfers
• Internal 5V cable short-circuit protection of ID, DP
and DM lines to VBUS or ground
• Industrial Operating Temperature -40
C to +85C
• 32-pin, QFN RoHS Compliant Package
(5 x 5 x 0.90 mm height)
Applications
The USB3320 is targeted for any application where a
Hi-Speed USB connection is desired and when board
space, power, and interface pins must be minimized.
The USB3320 is well suited for:
• Networking
• Audio Video
• Medical
• Industrial Computers
• Printers
• Repeaters
• Communication
USB3320
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI
Transceiver
USB3320
DS00001792E-page 2
2014-2016 Microchip Technology Inc.
TO OUR VALUED CUSTOMERS
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products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
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The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for cur-
rent devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the
revision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are
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2014-2016 Microchip Technology Inc.
DS00001792E-page 3
USB3320
Table of Contents
1.0 Introduction ..................................................................................................................................................................................... 4
2.0 USB3320 Pin Locations and Definitions ......................................................................................................................................... 6
3.0 Limiting Values ................................................................................................................................................................................ 9
4.0 Electrical Characteristics ............................................................................................................................................................... 10
5.0 Architecture Overview ................................................................................................................................................................... 17
6.0 ULPI Operation ............................................................................................................................................................................. 33
7.0 ULPI Register Map ........................................................................................................................................................................ 49
8.0 Application Notes .......................................................................................................................................................................... 58
9.0 Package Information ..................................................................................................................................................................... 63
Appendix A: Data Sheet Revision History ........................................................................................................................................... 67
The Microchip Web Site ...................................................................................................................................................................... 68
Customer Change Notification Service ............................................................................................................................................... 68
Customer Support ............................................................................................................................................................................... 68
Product Identification System ............................................................................................................................................................. 69
USB3320
DS00001792E-page 4
2014-2016 Microchip Technology Inc.
1.0
INTRODUCTION
1.1
General Description
The Microchip USB3320 is a Hi-Speed USB 2.0 Transceiver that provides a configurable physical layer (PHY) solution
and is an excellent match for a wide variety of products.
The frequency of the reference clock is user selectable. The USB3320 includes an internal oscillator that may be used
with either a quartz crystal or a ceramic resonator. Alternatively, the crystal input can be driven by an external clock oscil-
lator. Another option is the use of a 60MHz external clock when using the ULPI Input Clock mode.
Several advanced features make the USB3320 the transceiver of choice by reducing both electrical bill of material
(eBOM) part count and printed circuit board (PCB) area. Outstanding ESD robustness eliminates the need for external
ESD protection devices in typical applications. The internal Over-Voltage Protection circuit (OVP) protects the USB3320
from voltages up to 30V. By using a reference clock from the Link, the USB3320 removes the cost of a dedicated crystal
reference from the design. And the integrated USB switch enables unique product features with a single USB port of
connection.
The USB3320 meets all of the electrical requirements to be used as a Hi-Speed USB Host, Device, or an On-the-Go
(OTG) transceiver. In addition to the supporting USB signaling, the USB3320 also provides USB UART mode and USB
Audio mode.
USB3320 uses the industry standard UTMI+ Low Pin Interface (ULPI) to connect the USB Transceiver to the Link. ULPI
uses a method of in-band signaling and status byte transfers between the Link and transceiver to facilitate a USB ses-
sion with only 12 pins.
The USB3320 uses Microchip’s “wrapper-less” technology to implement the ULPI interface. This “wrapper-less” tech-
nology allows the transceiver to achieve a low latency transmit and receive time. Microchip’s low latency transceiver
allows an existing UTMI Link to be reused by adding a UTMI to ULPI bridge. By adding a bridge to the ASIC the existing
and proven UTMI Link IP can be reused.
FIGURE 1-1:
USB3320 BLOCK DIAGRAM
OTG
Hi-Speed
USB
Transceiver
ULPI Interface
ULPI
Registers
and State
Machine
BIAS
Crystal
Oscillator and
Low Jitter
Integrated
PLL
Integrated
Power
Management
VBUS
ID
DP
DM
RBIAS
REFCLK
ESD
Pr
ot
ec
tio
n
DATA[7:0]
CPEN
XO
RESETB
VDD18
VDD33
VBAT
DIR
NXT
STP
CLKOUT
USB
DP/DM
Switch
SPK_
L
SPK_R
VDDIO
REFSEL[2:0]
2014-2016 Microchip Technology Inc.
DS00001792E-page 5
USB3320
The USB3320 includes an integrated 3.3V Low Drop Out (LDO) regulator that may optionally be used to generate 3.3V
from power applied at the VBAT pin. The voltage on the VBAT pin can range from 3.1 to 5.5V. The regulator dropout
voltage is less than 100mV which allows the transceiver to continue USB signaling when the voltage on VBAT drops to
3.1V. The USB transceiver will continue to operate at lower voltages, although some parameters may be outside the
limits of the USB specifications. If the user would like to provide a 3.3V supply to the USB3320, the VBAT and VDD33
pins should be connected together as described in
Section 5.5.1
.
The USB3320 also includes integrated pull-up resistors that can be used for detecting the attachment of a USB Charger.
By sensing the attachment to a USB Charger, a product using the USB3320 can charge its battery at more than the
500mA allowed when charging from a USB Host. Please see Microchip Application Note AN 19.7 - Battery Charging
Using Microchip USB Transceivers for more information on battery charging.
In USB UART mode, the USB3320 DP and DM pins are redefined to enable pass-through of asynchronous serial data.
The USB3320 can only enter UART mode when the user programs the part into this mode, as described in
Section 6.5.1
.
In USB audio mode, a switch connects the DP pin to the SPK_R pin, and another switch connects he DM pin to the
SPK_L
pin. These switches are shown in the lower left-hand corner of
Figure 5.1
. The USB3320 can be configured to
enter USB audio mode as described in
Section 6.5.2
. In addition, these switches are on when the RESETB pin of the
USB3320 is asserted. The USB audio mode enables audio signaling from a single USB port of connection, and the
switches may also be used to connect Full Speed USB from another transceiver onto the USB cable.
1.2
Reference Documents
• Universal Serial Bus Specification, Revision 2.0, April 27, 2000
• On-The-Go Supplement to the USB 2.0 Specification, Revision 2.0, May 8, 2009
• USB Specification Revision 2.0 "Pull-up/pull-down resistors" ECN (27% Resistor ECN)
• USB 2.0 Transceiver Macrocell Interface (UTMI) Specification, Version 1.02, May 27, 2000
• UTMI+ Specification, Revision 1.0, February 25, 2004
• UTMI+ Low Pin Interface (ULPI) Specification, Revision 1.1, October 20th, 2004
• Technical Requirements and Test Methods of Charger and Interface for Mobile Telecommunication Terminal
Equipment (Chinese Charger Specification Approval Draft 11/29/2006)
USB3320
DS00001792E-page 6
2014-2016 Microchip Technology Inc.
2.0
USB3320 PIN LOCATIONS AND DEFINITIONS
2.1
USB3320
Pin Locations and Descriptions
2.1.1
PACKAGE DIAGRAM WITH PIN LOCATIONS
The illustration below is viewed from the top of the package.
2.1.2
PIN DEFINITIONS
The following table details the pin definitions for the figure above.
FIGURE 2-1:
USB3320 PIN LOCATIONS - TOP VIEW
TABLE 2-1:
USB3320 PIN DESCRIPTION
Pin
Name
Direction/
Type
Active
Level
Description
1
CLKOUT
Output,
CMOS
N/A
ULPI Output Clock Mode:
60MHz ULPI clock output. All ULPI signals
are driven synchronous to the rising edge
of this clock.
ULPI Input Clock Mode:
This pin is connected to VDDIO to
configure 60MHz ULPI Input Clock mode
as described in
Section 5.4.1
.
Following POR or hardware reset, the
voltage at CLKOUT must not exceed
V
IH_ED
as provided in
Table 4-4
.
2
NXT
Output,
CMOS
High
The transceiver asserts NXT to throttle the
data. When the Link is sending data to the
transceiver, NXT indicates when the
current byte has been accepted by the
transceiver. The Link places the next byte
on the data bus in the following clock
cycle.
3
DATA[0]
I/O,
CMOS
N/A
ULPI bi-directional data bus.
CLKOUT
NXT
DATA0
DATA1
DATA2
DATA3
REFSEL0
DATA4
DAT
A
5
DAT
A
6
REFSE
L
1
N/C
DATA7
REFSE
L
2
SPK_R
SPK
_
L
RBIAS
CPEN
DM
DP
VBUS
VBAT
VDD33
ID
VDDI
O
XO
RES
E
T
B
REFCL
K
VDD1
8
ST
P
VDD1
8
DI
R
USB3300
Hi-Speed USB2
ULPI PHY
32 Pin QFN
1
2
3
4
5
6
7
8
Hi-Speed USB
ULPI PHY
32 Pin QFN
GND FLAG
9
10
11
12
13
14
15
16
24
23
22
21
20
19
18
17
32
31
30
29
28
27
26
25
2014-2016 Microchip Technology Inc.
DS00001792E-page 7
USB3320
4
DATA[1]
I/O,
CMOS
N/A
ULPI bi-directional data bus.
5
DATA[2]
I/O,
CMOS
N/A
ULPI bi-directional data bus.
6
DATA[3]
I/O,
CMOS
N/A
ULPI bi-directional data bus.
7
DATA[4]
I/O,
CMOS
N/A
ULPI bi-directional data bus.
8
REFSEL[0]
Input,
CMOS
N/A
This signal, along with REFSEL[1] and
REFSEL[2]
selects one of the available
reference frequencies as defined in
Table 5-10
.
Note: This signal must be tied to VDDIO
when in ULPI 60MHz REFCLK IN mode.
9
DATA[5]
I/O,
CMOS
N/A
ULPI bi-directional data bus.
10
DATA[6]
I/O,
CMOS
N/A
ULPI bi-directional data bus.
11
REFSEL[1]
Input,
CMOS
N/A
This signal, along with REFSEL[0] and
REFSEL[2]
selects one of the available
reference frequencies as defined in
Table 5-10
.
Note: This signal must be tied to VDDIO
when in ULPI 60MHz REFCLK IN mode.
12
N/C
N/A
This pin must not be connected.
13
DATA[7]
I/O,
CMOS
N/A
ULPI bi-directional data bus.
14
REFSEL[2]
Input,
CMOS
N/A
This signal, along with REFSEL[0] and
REFSEL[1]
selects one of the available
reference frequencies as defined in
Table 5-10
.
Note: This signal must be tied to VDDIO
when in ULPI 60MHz REFCLK IN mode.
15
SPK_L
I/O,
Analog
N/A
USB switch in/out for DM signals
16
SPK_R
I/O,
Analog
N/A
USB switch in/out for DP signals
17
CPEN
Output,
CMOS
N/A
External 5V supply enable. Controls the
external V
BUS
power switch. CPEN is low
on POR.
18
DP
I/O,
Analog
N/A
D+ pin of the USB cable.
19
DM
I/O,
Analog
N/A
D- pin of the USB cable.
20
VDD33
Power
N/A
3.3V Regulator Output. A 2.2uF (<1 ohm
ESR) bypass capacitor to ground is
required for regulator stability. The bypass
capacitor should be placed as close as
possible to the USB3320.
21
VBAT
Power
N/A
Regulator input.
TABLE 2-1:
USB3320 PIN DESCRIPTION (CONTINUED)
Pin
Name
Direction/
Type
Active
Level
Description
USB3320
DS00001792E-page 8
2014-2016 Microchip Technology Inc.
22
VBUS
I/O,
Analog
N/A
This pin connects to an external resistor
(R
VBUS
) connected to the VBUS pin of the
USB cable. This pin is used for the VBUS
comparator inputs and for VBUS pulsing
during session request protocol. See
Table 5-7, "Required RVBUS Resistor
Value"
.
23
ID
Input,
Analog
N/A
ID
pin of the USB cable. For applications
not using ID this pin can be connected to
VDD33
. For an A-Device ID is grounded.
For a B-Device ID is floated.
24
RBIAS
Analog,
CMOS
N/A
Bias Resistor pin. This pin requires an
8.06kΩ (±1%) resistor to ground, placed as
close as possible to the USB3320.
Nominal voltage during ULPI operation is
0.8V.
25
XO
Output,
CMOS
N/A
External resonator pin. When using an
external clock on REFCLK, this pin should
be floated.
26
REFCLK
Input,
CMOS
N/A
ULPI Output Clock Mode:
Reference frequency as defined in
Table 5-
10
.
ULPI Input Clock Mode:
60MHz ULPI clock input.
27
RESETB
Input,
CMOS,
Low
When low, the part is suspended with all
ULPI outputs tri-stated. When high, the
USB3320 will operate as a normal ULPI
device, as described in
Section 5.5.2
. The
state of this pin may be changed
asynchronously to the clock signals. When
asserted for a minimum of 1 microsecond
and then de-asserted, the ULPI registers
are reset to their default state and all
internal state machines are reset.
28
VDD18
Power
N/A
External 1.8V Supply input pin. This pad
needs to be bypassed with a 0.1uF
capacitor to ground, placed as close as
possible to the USB3320.
29
STP
Input,
CMOS
High
The Link asserts STP for one clock cycle
to stop the data stream currently on the
bus. If the Link is sending data to the
transceiver, STP indicates the last byte of
data was on the bus in the previous cycle.
30
VDD18
Power
N/A
External 1.8V Supply input pin. This pad
needs to be bypassed with a 0.1uF
capacitor to ground, placed as close as
possible to the USB3320.
31
DIR
Output,
CMOS
N/A
Controls the direction of the data bus.
When the transceiver has data to transfer
to the Link, it drives DIR high to take
ownership of the bus. When the
transceiver has no data to transfer it drives
DIR
low and monitors the bus for
commands from the Link.
32
VDDIO
Power
N/A
External 1.8V to 3.3V ULPI supply input
pin. This voltage sets the value of V
OH
for
the ULPI signals. This pad needs to be
bypassed with a 0.1uF capacitor to ground,
placed as close as possible to the
USB3320.
FLAG
GND
Ground
N/A
Ground.
TABLE 2-1:
USB3320 PIN DESCRIPTION (CONTINUED)
Pin
Name
Direction/
Type
Active
Level
Description
2014-2016 Microchip Technology Inc.
DS00001792E-page 9
USB3320
3.0
LIMITING VALUES
3.1
Absolute Maximum Ratings
3.2
Recommended Operating Conditions
TABLE 3-1:
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Condition
MIN
TYP MAX Units
VBUS
, VBAT, ID, CPEN,
DP
, DM, SPK_L, and
SPK_R
voltage to GND
V
MAX_5V
Voltage measured at pin.
VBUS
tolerant to 30V with
external R
VBUS
.
-0.5
+6.0
V
Maximum VDD18 voltage
to Ground
V
MAX_18V
-0.5
2.5
V
Maximum VDDIO voltage
to Ground
V
MAX_IOV
VDD18
= V
DD18
-0.5
4.0
V
Maximum VDDIO voltage
to Ground
V
MAX_IOV
VDD18
= 0V
-0.5
0.7
V
Maximum VDD33 voltage
to Ground
V
MAX_33V
-0.5
4.0
V
Maximum I/O voltage to
Ground
V
MAX_IN
-0.5
V
DDIO
+ 0.7
V
Operating Temperature
T
MAX_OP
-40
85
C
Storage Temperature
T
MAX_STG
-55
150
C
Note:
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
TABLE 3-2:
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Condition
MIN
TYP MAX
Units
VBAT
to GND
V
VBAT
3.1
5.5
V
VDD33
to GND
V
DD33
3.0
3.3
3.6
V
VDDIO
to GND
V
DDIO
1.6
1.8-3.3
3.6
V
VDD18
to GND
V
DD18
1.6
1.8
2.0
V
Input Voltage on Digital
Pins (RESETB, STP, DIR,
NXT
, DATA[7:0])
V
I
0.0
V
DDIO
V
Voltage on Analog I/O
Pins (DP, DM, ID, CPEN,
SPK_L
, SPK_R)
V
I(I/O)
0.0
V
DD33
V
VBUS
to GND
V
VMAX
0.0
5.5
V
Ambient Temperature
T
A
-40
85
C
VDDIO
VDD18 min
USB3320
DS00001792E-page 10
2014-2016 Microchip Technology Inc.
4.0
ELECTRICAL CHARACTERISTICS
The following conditions are assumed unless otherwise specified:
V
VBAT
= 3.1 to 5.5V; V
DD18
= 1.6 to 2.0V; V
DDIO
= 1.6 to 2.0V; V
SS
= 0V; T
A
= -40
C to +85C
The current for 3.3V circuits is sourced at the VBAT pin, except when using an external 3.3V supply as shown in
Figure 5-7
.
4.1
Operating Current
Note 4-1
ClockSuspendM
bit = 0.
Note 4-2
SessEnd, VbusVld, and IdFloat comparators disabled. STP Interface protection disabled.
TABLE 4-1:
ELECTRICAL CHARACTERISTICS: OPERATING CURRENT
Parameter
Symbol
Condition
MIN
TYP MAX Units
Synchronous Mode Current
(Default Configuration)
I
33AVG(SYNC)
Start-up sequence defined in
Section 5.5.4
has
completed.
7.5
mA
I
18AVG(SYNC)
28.0
mA
I
IOAVG(SYNC)
4.1
mA
Synchronous Mode Current
(HS USB operation)
I
33AVG(HS)
Active USB Transfer
11.1
mA
I
18AVG(HS)
29.4
mA
I
IOAVG(HS)
5.9
mA
Synchronous Mode Current
(FS/LS USB operation)
I
33AVG(FS)
Active USB Transfer
6.3
mA
I
18AVG(FS)
22.5
mA
I
IOAVG(FS)
5.0
mA
Serial Mode Current
(FS/LS USB)
Note 4-1
I
33AVG(FS_S)
5.6
mA
I
18AVG(FS_S)
2.4
mA
I
IOAVG(FS_S)
86
uA
USB UART Current
Note 4-1
I
33AVG(UART)
5.6
mA
I
18AVG(UART)
2.4
mA
I
IOAVG(UART)
58
uA
Low Power Mode
Note 4-2
I
DD33(LPM)
V
VBAT
= 4.2V
V
DD18
= 1.8V
V
DDIO
= 1.8V
18.8
uA
I
DD18(LPM)
0.7
uA
I
DDIO(LPM)
30
uA
Standby Mode
I
DD33(RSTB)
RESETB = 0
V
VBAT
= 4.2V
V
DD18
= 1.8V
V
DDIO
= 1.8V
18
uA
I
DD18(RSTB)
0.6
uA
I
DDIO(RSTB)
0.1
uA