2017 Microchip Technology Inc.
DS20005709A-page 1
TN5325
Features
• Low Threshold (2V Maximum)
• High Input Impedance and High Gain
• Free from Secondary Breakdown
• Low CISS and Fast Switching Speeds
Applications
• Logic-level Interfaces (Ideal for TTL and CMOS)
• Solid State Relays
• Battery-operated Systems
• Photo-voltaic Drives
• Analog Switches
• General Purpose Line Drivers
• Telecommunication Switches
General Description
The TN5325 is a low-threshold, Enhancement-mode
(normally-off) transistor that utilizes a vertical DMOS
structure and a well-proven silicon gate manufacturing
process. This combination produces a device with the
power handling capabilities of bipolar transistors and
the high input impedance and positive temperature
coefficient inherent in MOS devices. Characteristic of
all MOS structures, this device is free from thermal
runaway and thermally induced secondary breakdown.
Microchip’s vertical DMOS FETs are ideally suited to a
wide range of switching and amplifying applications
where very low threshold voltage, high breakdown
voltage, high input impedance, low input capacitance
and fast switching speeds are desired.
Package Types
3-lead SOT-23 (TO-236AB)
(Top view)
See
Table 2-1
,
Table 2-2
and
Table 2-3
for pin information.
DRAIN
SOURCE
GATE
3-lead TO-92
(Top view)
3-lead SOT-89 (243AA)
(Top view)
GATE
SOURCE
DRAIN
DRAIN
GATE
SOURCE
DRAIN
N-Channel Enhancement-Mode Vertical DMOS FET
TN5325
DS20005709A-page 2
2017 Microchip Technology Inc.
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
Drain-to-source Voltage ....................................................................................................................................... BV
DSX
Drain-to-gate Voltage .......................................................................................................................................... BV
DGX
Gate-to-source Voltage ......................................................................................................................................... ±20V
Operating Ambient Temperature, T
A
................................................................................................... –55°C to +150°C
Storage Temperature, T
S
..................................................................................................................... –55°C to +150°C
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions above those
indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for
extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
1
Electrical Specifications: Unless otherwise specified, for all specifications T
A
= T
J
= +25°C.
Parameter
Sym.
Min. Typ. Max.
Unit
Conditions
Drain-to-source Breakdown Voltage
BV
DSS
250
—
—
V
V
GS
= 0V, I
D
= 100 µA
Gate Threshold Voltage
V
GS(th)
0.6
—
2
V
V
GS
= V
DS
, I
D
= 1 mA
Change in V
GS(th)
with Temperature
∆V
GS(th)
—
—
–4.5 mV/°C V
GS
= V
DS
, I
D
= 1 mA (
Note 2
)
Gate Body Leakage
I
GSS
—
—
100
nA
V
GS
= ± 20V, V
DS
= 0V
Zero-gate Voltage Drain Current
I
DSS
—
—
1
µA
V
GS
= 0V, V
DS
= 100V
—
—
10
V
GS
= 0V, V
DS
= Maximum Rating
—
—
1
mA
V
DS
= 0.8 Maximum Rating,
V
GS
= 0V, T
A
= 125°C (
Note 2
)
On-state Drain Current
I
D(ON)
0.6
—
—
A
V
GS
= 4.5V, V
DS
= 25V
1.2
—
—
V
GS
= 10V, V
DS
= 25V
Static Drain-to-source On-state
Resistance
R
DS(ON)
—
—
8
Ω
V
GS
= 4.5V, I
D
= 150 mA
—
—
7
V
GS
= 10V, I
D
= 1A
Change in R
DS(ON)
with Temperature
∆
RDS(ON)
—
—
1
%/°C
V
GS
= 4.5V, I
D
= 150 mA (
Note 2
)
Note 1: All DC parameters are 100% tested at 25°C unless otherwise stated. Pulse test: 300 µs pulse, 2% duty
cycle.
2: Specification is obtained by characterization and is not 100% tested.
AC ELECTRICAL CHARACTERISTICS
2
Electrical Specifications: Unless otherwise specified, for all specifications T
A
= T
J
= +25°C.
Parameter
Sym.
Min. Typ. Max.
Unit
Conditions
Forward Transconductance
G
FS
150
—
—
mmho V
DS
= 25V, I
D
= 200 mA
Input Capacitance
C
ISS
—
—
110
pF
V
GS
= 0V,
V
DS
= 25V,
f = 1 MHz
Common Source Output Capacitance
C
OSS
—
—
60
Reverse Transfer Capacitance
C
RSS
—
—
23
Turn-on Delay Time
t
d(ON)
—
—
20
ns
V
DD
= 25V,
I
D
= 150 mA,
R
GEN
= 25Ω
Rise Time
t
r
—
—
15
Turn-off Delay Time
t
d(OFF)
—
—
25
Fall Time
t
f
—
—
25
DIODE PARAMETER
Diode Forward Voltage Drop
V
SD
—
—
1.8
V
V
GS
= 0V, I
SD
= 200 mA (
Note 1
)
Reverse Recovery Time
t
rr
—
300
—
ns
V
GS
= 0V, I
SD
= 200 mA (
Note 2
)
Note 1: All DC parameters are 100% tested at 25°C unless otherwise stated. Pulse test: 300 µs pulse, 2% duty
cycle.
2: Specification is obtained by characterization and is not 100% tested.
TEMPERATURE SPECIFICATIONS
Parameter
Sym.
Min. Typ. Max.
Unit
Conditions
TEMPERATURE RANGE
Operating Ambient Temperature
T
A
–55
—
+150
°C
Storage Temperature
T
S
–55
—
+150
°C
PACKAGE THERMAL RESISTANCE
3-lead SOT-23
JA
—
350
—
°C/W
JC
—
200
—
°C/W
3-lead TO-92
JA
—
170
—
°C/W
JC
—
125
—
°C/W
3-lead SOT-89
JA
—
78
—
°C/W
Note 1
JC
—
15
—
°C/W
Note 1: Mounted on FR5 25 mm x 25 mm x 1.57 mm
THERMAL CHARACTERISTICS
Package
I
D
(
1
)
(Continuous)
(mA)
I
D
(Pulsed)
(A)
Power Dissipation at
T
A
= 25°C
(W)
I
DR
(
1
)
(mA)
I
DRM
(A)
3-lead SOT-23
150
0.4
0.36
150
0.4
3-lead TO-92
215
0.8
0.74
215
0.8
3-lead SOT-89
316
1.5
1.6
(
2
)
316
1.5
Note 1: I
D
(continuous) is limited by maximum T
J
.
2: Mounted on FR5 board, 25 mm x 25 mm x 1.57 mm
2017 Microchip Technology Inc.
DS20005709A-page 3
TN5325
TN5325
DS20005709A-page 4
2017 Microchip Technology Inc.
2.0
PIN DESCRIPTION
Table 2-1
,
Table 2-2
and
Table 2-3
show the
description of pins in TN5325 3-lead SOT-23, 3-lead
TO-92 and 3-lead SOT-89, respectively. Refer to
Package Types
for the location of pins.
TABLE 2-1:
SOT-23 PIN FUNCTION TABLE
Pin Number
Pin Name
Description
1
Gate
Gate
2
Source
Source
3
Drain
Drain
TABLE 2-2:
TO-92 PIN FUNCTION TABLE
Pin Number
Pin Name
Description
1
Source
Source
2
Gate
Gate
3
Drain
Drain
TABLE 2-3:
SOT-89 PIN FUNCTION TABLE
Pin Number
Pin Name
Description
1
Gate
Gate
2
Drain
Drain
3
Source
Source
4
Drain
Drain
2017 Microchip Technology Inc.
DS20005709A-page 5
TN5325
3.0
FUNCTIONAL DESCRIPTION
Figure 3-1
illustrates the switching waveforms and test
circuit for TN5325.
90%
10%
90%
90%
10%
10%
Pulse
Generator
VDD
R
L
OUTPUT
D.U.T.
t
(ON)
t
d(ON)
t
(OFF)
t
d(OFF)
t
r
INPUT
INPUT
OUTPUT
10V
VDD
R
GEN
0V
0V
t
f
FIGURE 3-1:
Switching Waveforms and Test Circuit.
PRODUCT SUMMARY
BV
DSS
/BV
DGS
(V)
R
DS(ON)
(Maximum)
(Ω)
I
D(ON)
(Minimum)
(A)
V
GS(th)
(Maximum)
(V)
250V
7
1.2
2
TN5325
DS20005709A-page 6
2017 Microchip Technology Inc.
4.0
Legend: XX...X
Product Code or Customer-specific information
Y
Year code (last digit of calendar year)
YY
Year code (last 2 digits of calendar year)
WW
Week code (week of January 1 is week ‘01’)
NNN
Alphanumeric traceability code
Pb-free JEDEC
®
designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note:
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for product code or customer-specific information. Package may or
not include the corporate logo.
3
e
3
e
XXXNNN
N3C232
3-lead SOT-23
Example
3-lead TO-92
YWWNNN
XXXXXX
XXXX
e3
Example
725698
TN5325
N3
e3
3-lead SOT-89
Example
XXXXYWW
NNN
TN3C714
478
PACKAGING INFORMATION
4.1
Package Marking Information
3-Lead TO-236AB (SOT-23) Package Outline (K1/T)
2.90x1.30mm body, 1.12mm height (max), 1.90mm pitch
Symbol
A
A1
A2
b
D
E
E1
e
e1
L
L1
ș
Dimension
(mm)
MIN
0.89
0.01
0.88
0.30
2.80
2.10
1.20
0.95
BSC
1.90
BSC
0.20
†
0.54
REF
0
O
NOM
-
-
0.95
-
2.90
-
1.30
0.50
-
MAX
1.12
0.10
1.02
0.50
3.04
2.64
1.40
0.60
8
O
JEDEC Registration TO-236, Variation AB, Issue H, Jan. 1999.
† This dimension differs from the JEDEC drawing.
Drawings not to scale.
View B
View A - A
Side View
Top View
View B
Gauge
Plane
Seating
Plane
0.25
L1
L
E1 E
D
3
1
2
e
e1
b
A
A
Seating
Plane
A
A2
A1
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
2017 Microchip Technology Inc.
DS20005709A-page 7
TN5325
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
TN5325
DS20005709A-page 8
2017 Microchip Technology Inc.
3-Lead TO-243AA (SOT-89) Package Outline (N8)
Symbol
A
b
b1
C
D
D1
E
E1
e
e1
H
L
Dimensions
(mm)
MIN
1.40
0.44
0.36
0.35
4.40
1.62
2.29
2.00
†
1.50
BSC
3.00
BSC
3.94
0.73
†
NOM
-
-
-
-
-
-
-
-
-
-
MAX
1.60
0.56
0.48
0.44
4.60
1.83
2.60
2.29
4.25
1.20
JEDEC Registration TO-243, Variation AA, Issue C, July 1986.
† This dimension differs from the JEDEC drawing
Drawings not to scale.
b
b1
D
D1
E H
E1
C
A
1
2
3
e
e1
Top View
Side View
L
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
2017 Microchip Technology Inc.
DS20005709A-page 9
TN5325
TN5325
DS20005709A-page 10
2017 Microchip Technology Inc.
NOTES: