Six Channel Delta Sigma A/D Converter

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© 2011 Microchip Technology Inc.

DS25048B-page 1

MCP3903

Features

• Six Synchronous Sampling 16/24-bit Resolution 

Delta-Sigma A/D Converters with Proprietary 
Multi-Bit Architecture

• 91 dB SINAD, -100 dBc Total Harmonic Distortion 

(THD) (up to 35

th

 

harmonic), 102 dB Spurious-free 

Dynamic Range (SFDR) for Each Channel

• Programmable Data Rate up to 64 ksps
• Ultra Low-Power Shutdown Mode with <2 μA
• -115 dB Crosstalk Between any Two Channels
• Low Drift Internal Voltage Reference: 5 ppm/°C
• Differential Voltage Reference Input Pins
• High Gain PGA on Each Channel (up to 32 V/V)
• Phase Delay Compensation Between Each Pair 

of Channels with 1 μs Time Resolution

• High-Speed Addressable 10 MHz SPI Interface 

with Mode 0,0 and 1,1 Compatibility

• Independent Analog and Digital Power Supplies 

4.5V - 5.5V AV

DD

, 2.7V - 3.6V DV

DD

• Available in Small 28-lead SSOP Package
• Extended Temperature Range: -40°C to +125°C

Applications

• Energy Metering and Power Measurement
• Portable Instrumentation
• Medical and Power Monitoring

Description

The MCP3903 is a six-channel Analog Front End (AFE)
containing three pairs made out of two synchronous
sampling Delta-Sigma Analog-to-Digital Converters
(ADC) with PGA, a phase delay compensation block,
internal voltage reference, and high-speed 10 MHz SPI
compatible serial interface. The converters contain a
proprietary dithering algorithm for reduced idle tones
and improved THD.
The internal register map contains 24-bit wide ADC
data words, a modulator output register as well as six
24-bit writable control registers to program gain,
over-sampling ratio, phase, resolution, dithering,
shut-down, reset and several communication features.
The communication is largely simplified with various
Continuous Read modes that can be accessed by the
Direct Memory Access (DMA) of an MCU and with
separate Data Ready pins that can directly be
connected to the Interrupt Request (IRQ) input of an
MCU. The MCP3903 is capable of interfacing to a large
variety of voltage and current sensors including shunts,
current transformers, Rogowski coils, and Hall-effect
sensors.

Package Type

CS

1
2
3
4

28
27
26
25
24
23
22

21

5
6
7
8

SCK

DV

DD

AV

DD

CH0+
CH0-
CH1-
CH1+
CH2+

20

9

DRB

OSC1
DRC

OSC2

CH2-
CH3-

RESET

19

10

CH3+

CH4+

SDO

SDI

           28-Lead SSOP

18

17

11
12

16

13

REFIN-

DGND
AGND

DRA

CH4-
CH5-

15

14

CH5+

REFIN/OUT+

Six Channel Delta Sigma A/D Converter

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MCP3903

DS25048B-page 2

© 2011 Microchip Technology Inc.

Functional Block Diagram

CH0+

CH0-

CH1+

CH1-

SDO

SDI
SCK

DUAL DS  ADC

ANALOG DIGITAL

SINC

3

-

+

PGA

Xtal Oscillator

MCLK

OSC1

OSC2

DRA

RESET

Digital SPI 

Interface

Clock 

Generation

SINC

3

-

+

PGA

Modulator

AMCLK

DMCLK/DRCLK

DMCLK

Phase 

Shifter

PHASEA <7:0>

OSR<1:0>

PRE<1:0>

DATA_CH0<23:0>

DATA_CH1<23:0>

CS

REFIN/OUT+

REFIN -

AV

DD

AGND

DGND

DV

DD

POR
AV

DD

 

Monitoring

Modulator

V

REF

+

V

REF

-

VREFEXT

Voltage 

Reference

V

REF

+

-

Δ -Σ 

Δ -Σ 

Φ

CH2+

CH2-

CH3+

CH3-

DUAL DS  ADC

SINC

3

-

+

PGA

SINC

3

-

+

PGA

Modulator

Phase 

Shifter

PHASEB <7:0>

DATA_CH2<23:0>

DATA_CH3<23:0>

Modulator

Δ -Σ 

Δ -Σ 

Φ

CH4+

CH4-

CH5+

CH5-

DUAL DS  ADC

SINC

3

-

+

PGA

SINC

3

-

+

PGA

Modulator

Phase 

Shifter

PHASEC <7:0>

DATA_CH4<23:0>

DATA_CH5<23:0>

Modulator

Δ -Σ 

Δ -Σ 

Φ

DRB

DRC

POR

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© 2011 Microchip Technology Inc.

DS25048B-page 3

MCP3903

1.0

 ELECTRICAL 
CHARACTERISTICS

The Reliability Targets section includes the absolute
maximum ratings for the device, defining the values
that will cause no long term damage regardless of
duration.
These tables also represent the testing requirements
per the Max. and Min. columns.

1.1

RELIABILITY TARGETS

ABSOLUTE MAXIMUM RATINGS †

V

DD

................................................................................... 7.0V

Digital inputs and outputs w.r.t. A

GND

........-0.6V to V

DD

 +0.6V

Analog input w.r.t. A

GND

..................................... ....-6V to +6V

V

REF

 input w.r.t. A

GND

................................-0.6V to V

DD

 +0.6V

Storage temperature..................................... -65°C to +150°C
Ambient temp. with power applied................ -65°C to +125°C
Soldering temperature of leads (10 seconds)............. +300°C
ESD on the analog inputs (HBM,MM)................. 5.0 kV, 500V
ESD on all other pins (HBM,MM)........................ 5.0 kV, 500V

TABLE 1-1:

ANALOG SPECIFICATIONS TARGET TABLE

Electrical Specifications:

 Unless otherwise indicated, all parameters apply at AV

DD 

= 4.5 to 5.5V, DV

DD

 = 2.7 to 

3.6V, Internal V

REF

, MCLK = 4 MHz;PRESCALE = 1; OSR = 64; f

S

 = 1 MHz; f

D

 = 15.625 ksps; T

A

 = -40°C to +125°C, 

GAIN = 1, V

IN

 = 1V

PP

 = 353mV

RMS

 @ 50/60 Hz.

Param. 

Num.

Symbol

Characteristic

Min.

Typ.

Max.

Units

Test Conditions

Internal Voltage Reference

A001

V

REF

Voltage

-2%

2.35

+2%

V

VREFEXT = 0

A002

TC

REF

Tempco

5

ppm/°C VREFEXT = 0

A003

ZOUT

REF

Output Impedance

7

k

Ω

AV

DD

=5V, 

VREFEXT = 0

Voltage Reference Input
A004

Input Capacitance

10

pF

A005

V

REF

Differential Input Voltage 
Range (V

REF+

 - V

REF-

2.2

2.6

V

V

REF

 = (V

REF+

 - V

REF-

), 

VREFEXT = 1

A006

V

REF+

Absolute Voltage on REFIN+ 
pin

1.9

2.9

V

VREFEXT = 1 

A007

V

REF-

Absolute Voltage on REFIN- 
pin

-0.3

+0.3

V

V

REF- 

should be connected 

to AGND when VREFEXT=0

ADC Performance
A008

Resolution (No Missing 
Codes)

24

bits

OSR = 256 (see 

Table 5-2

)

A009

f

S

Sampling Frequency

See 

Table 4-2

kHz

f

S

 = DMCLK = MCLK / (4 x 

PRESCALE)

A010

f

D

Output Data Rate

See 

Table 4-2

ksps

f

D

 = DRCLK= DMCLK / OSR 

= MCLK / (4 x PRESCALE x 
OSR)

Note 1:

 This specification implies that the ADC output is valid over this entire differential range, i.e. there is no distortion or 
instability across this input range. Dynamic Performance is specified at -0.5 dB below the maximum signal range,
V

IN

 = -0.5 dBFS @ 50/60 Hz = 333 mV

RMS

, V

REF

 = 2.4V.

2:

See terminology section for definition.

3:

This parameter is established by characterization and not 100% tested.

4:

For these operating currents, the following configuration bit settings apply: Config Register Settings: 
SHUTDOWN<5:0> = 000000, RESET<5:0> = 000000; VREFEXT = 0, CLKEXT = 0.

5:

For these operating currents, the following configuration bit settings apply: Config Register Settings: 
SHUTDOWN<5:0> = 111111, VREFEXT = 1, CLKEXT = 1.

6:

Applies to all gains. Offset error is dependant on PGA gain setting.

7:

Outside of this range, ADC accuracy is not specified. An extended input range of +/- 6V can be applied continuously to 
the part with no risk for damage.

8:

For proper operation and to keep ADC accuracy, AMCLK should always be in the range of 1 to 5 MHz with BOOST bits 
off. With BOOST bits on, AMCLK should be in the range of 1 to 8.192 MHz. AMCLK = MCLK/PRESCALE. When using a 
crystal, CLKEXT bit should be equal to ‘0’.

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MCP3903

DS25048B-page 4

© 2011 Microchip Technology Inc.

A011

CHn+-

Analog Input Absolute 
Voltage

-1

+1

V

All analog input channels, 
measured to AGND 

(Note 7)

A012

A

IN

Analog Input Leakage 
Current

1

nA

(Note 4)

A013

(CH

n+

-

CH

n-

)

Differential Input Voltage 
Range

500 / 

GAIN

mV

P

(Note 1)

A014

V

OS

Offset Error

-3

3

mV

(Note 6)(Note 2)

A015

Offset Error Drift

1

μV/C

From -40°C to 125°C

A016

GE

Gain Error

-3

3

%

All Gains

A017

Gain Error Drift

2

ppm/°C From -40°C to 125°C

A018

INL

Integral Non-Linearity

15

ppm

GAIN = 1, DITHER = ON

A019

Z

IN

Input Impedance

350

k

Ω

Proportional to 1/AMCLK 

A020

SINAD

Signal-to-Noise and 
Distortion Ratio

89

91

dB

T = 25°C

80

81.5

dB

A021

THD

Total Harmonic Distortion

-100

-97

dB

OSR = 256, DITHER = ON; 

(Note 2)(Note 3)

-90

-87

dB

A022

SNR

Signal To Noise Ratio

90

91.5

dB

T = 25°C

80

81.5

dB

A023

SFDR

Spurious Free Dynamic 
Range

102

dB

OSR = 256, DITHER = ON; 

(Note 2) (Note 3)

91

dB

A024

CTALK

Crosstalk (50 / 60 Hz)

-115

dB

OSR = 256, DITHER = ON; 

(Note 2)(Note 3)

A025

AC PSRR AC Power Supply Rejection

-68

dB

AV

DD

 = 5V + 1Vpp @ 50 Hz

A026

DC PSRR DC Power Supply Rejection

-68

dB

AV

DD

 = 4.5 to 5.5V, DV

DD

 = 

3.3V

A027

CMRR

DC Common Mode Rejection 
Ratio

-75

dB

V

CM

 varies from -1V to +1V; 

(Note 2)

Oscillator Input

TABLE 1-1:

ANALOG SPECIFICATIONS TARGET TABLE

 (CONTINUED)

Electrical Specifications:

 Unless otherwise indicated, all parameters apply at AV

DD 

= 4.5 to 5.5V, DV

DD

 = 2.7 to 

3.6V, Internal V

REF

, MCLK = 4 MHz;PRESCALE = 1; OSR = 64; f

S

 = 1 MHz; f

D

 = 15.625 ksps; T

A

 = -40°C to +125°C, 

GAIN = 1, V

IN

 = 1V

PP

 = 353mV

RMS

 @ 50/60 Hz.

Param. 

Num.

Symbol

Characteristic

Min.

Typ.

Max.

Units

Test Conditions

Note 1:

 This specification implies that the ADC output is valid over this entire differential range, i.e. there is no distortion or 
instability across this input range. Dynamic Performance is specified at -0.5 dB below the maximum signal range,
V

IN

 = -0.5 dBFS @ 50/60 Hz = 333 mV

RMS

, V

REF

 = 2.4V.

2:

See terminology section for definition.

3:

This parameter is established by characterization and not 100% tested.

4:

For these operating currents, the following configuration bit settings apply: Config Register Settings: 
SHUTDOWN<5:0> = 000000, RESET<5:0> = 000000; VREFEXT = 0, CLKEXT = 0.

5:

For these operating currents, the following configuration bit settings apply: Config Register Settings: 
SHUTDOWN<5:0> = 111111, VREFEXT = 1, CLKEXT = 1.

6:

Applies to all gains. Offset error is dependant on PGA gain setting.

7:

Outside of this range, ADC accuracy is not specified. An extended input range of +/- 6V can be applied continuously to 
the part with no risk for damage.

8:

For proper operation and to keep ADC accuracy, AMCLK should always be in the range of 1 to 5 MHz with BOOST bits 
off. With BOOST bits on, AMCLK should be in the range of 1 to 8.192 MHz. AMCLK = MCLK/PRESCALE. When using a 
crystal, CLKEXT bit should be equal to ‘0’.

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DS25048B-page 5

MCP3903

A028

MCLK

Master Clock Frequency 
Range

1

16.384

MHz

(Note 8)

Power Specifications
P001

AV

DD

Operating Voltage, Analog

4.5

5.5

V

P002

DV

DD

Operating Voltage, Digital

2.7

3.6

V

 

P003

AI

DD

Operating Current, Analog

(Note 4)

7.1

9

mA

BOOST bits low on all chan-
nels

12.3

16.8

mA

BOOST bits high on all 
channels

P004

DI

DD

Operating Current, Digital

1.2

1.7

mA

DV

DD

 = 3.6V, MCLK = 

4 MHz

2.4

3.4

mA

DV

DD

 = 3.6V, MCLK = 

8.192 MHz

P005

I

DDS,A

Shutdown Current, Analog

1

μA

-40°C to 85°C, AV

DD 

pin 

only, 

(Note 5)

3

μA

-40°C to 125°C, AV

DD 

pin 

only, 

(Note 5)

P006

I

DDS,D

Shutdown Current, Digital

1

μA

-40°C to 85°C, DV

DD 

pin 

only, 

(Note 5)

5

μA

-40°C to 125°C, DV

DD 

pin 

only, 

(Note 5)

TABLE 1-1:

ANALOG SPECIFICATIONS TARGET TABLE

 (CONTINUED)

Electrical Specifications:

 Unless otherwise indicated, all parameters apply at AV

DD 

= 4.5 to 5.5V, DV

DD

 = 2.7 to 

3.6V, Internal V

REF

, MCLK = 4 MHz;PRESCALE = 1; OSR = 64; f

S

 = 1 MHz; f

D

 = 15.625 ksps; T

A

 = -40°C to +125°C, 

GAIN = 1, V

IN

 = 1V

PP

 = 353mV

RMS

 @ 50/60 Hz.

Param. 

Num.

Symbol

Characteristic

Min.

Typ.

Max.

Units

Test Conditions

Note 1:

 This specification implies that the ADC output is valid over this entire differential range, i.e. there is no distortion or 
instability across this input range. Dynamic Performance is specified at -0.5 dB below the maximum signal range,
V

IN

 = -0.5 dBFS @ 50/60 Hz = 333 mV

RMS

, V

REF

 = 2.4V.

2:

See terminology section for definition.

3:

This parameter is established by characterization and not 100% tested.

4:

For these operating currents, the following configuration bit settings apply: Config Register Settings: 
SHUTDOWN<5:0> = 000000, RESET<5:0> = 000000; VREFEXT = 0, CLKEXT = 0.

5:

For these operating currents, the following configuration bit settings apply: Config Register Settings: 
SHUTDOWN<5:0> = 111111, VREFEXT = 1, CLKEXT = 1.

6:

Applies to all gains. Offset error is dependant on PGA gain setting.

7:

Outside of this range, ADC accuracy is not specified. An extended input range of +/- 6V can be applied continuously to 
the part with no risk for damage.

8:

For proper operation and to keep ADC accuracy, AMCLK should always be in the range of 1 to 5 MHz with BOOST bits 
off. With BOOST bits on, AMCLK should be in the range of 1 to 8.192 MHz. AMCLK = MCLK/PRESCALE. When using a 
crystal, CLKEXT bit should be equal to ‘0’.

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MCP3903

DS25048B-page 6

© 2011 Microchip Technology Inc.

1.2

SERIAL INTERFACE CHARACTERISTICS

SERIAL INTERFACE SPECIFICATIONS

Electrical Specifications:

 Unless otherwise indicated, all parameters apply at AV

DD 

= 4.5 to 5.5V,

DV

DD

 = 2.7 to 3.6V, -40°C < T

A

 <+125°C, C

LOAD

 = 30 pF.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Serial Clock frequency

f

SCK

10

MHz 2.7 

≤ DV

DD

 

< 3.6

CS setup time

t

CSS

50

ns

2.7 

≤ DV

DD

 

< 3.6

CS hold time

t

CSH

100

ns

2.7 

≤ DV

DD

 

< 3.6

CS disable time

t

CSD

50

ns

Data setup time

t

SU

10

ns

2.7 

≤ DV

DD

 

< 3.6

Data hold time

t

HD

20

ns

2.7 

≤ DV

DD

 

< 3.6

Serial Clock high time

t

HI

40

ns

2.7 

≤ DV

DD

 

< 3.6

Serial Clock low time

t

LO

40

ns

2.7 

≤ DV

DD

 

< 3.6

Serial Clock delay time

t

CLD

50

ns

Serial Clock enable time

t

CLE

50

ns

Output valid from SCK low

t

DO

50

ns

2.7 

≤ DV

DD

 

< 3.6

Output hold time

t

HO

0

ns

Output disable time

t

DIS

50

ns

2.7 

≤ DV

DD

 

< 3.6

Reset Pulse Width (RESET)

t

MCLR

100

ns

2.7 

≤ DV

DD

 

< 3.6

Data Transfer Time to DR (Data Ready) t

DODR

50

ns

2.7 

≤ DV

DD

 

< 3.6

Data Ready Pulse Low Time

t

DRP

1/

DMCLK

 

µs

2.7 

≤ DV

DD

 

< 3.6

Schmitt Trigger High-level Input voltage 
(All digital inputs)

V

IH1

.7 DV

DD

DV

DD

 +1

V

Schmitt Trigger Low-level input voltage 
(All digital inputs)

V

IL1

-0.3

0.25 

DV

DD

V

Hysteresis of Schmitt Trigger Inputs
(All digital inputs)

V

HYS

50

mV

Low-level output voltage, SDO pin

V

OL

0.4

V

SDO pin only, I

OL

 = 2 mA, 

DV

DD

 = 3.3V

Low-level output voltage, DRn pins

V

OL

0.4

V

DRn pins only,
I

OL

 = +1.5 mA, DV

DD

 =3.3V 

High-level output voltage, SDO pin

V

OH

DV

DD

 -

0.5

V

SDO pin only, 
I

OH

 = -2 mA, DV

DD

 = 3.3V

High-level output voltage, DRn pins 
only

V

OH

DV

DD

 -

0.5

V

DRn pins only, 
I

OH

 = -1.5 mA, DV

DD

=3.3V

Input leakage current

I

LI

±1

µA

CS = DV

DD

, Inputs tied to 

DV

DD

 

OR

 DGND

Output leakage current

I

LO

±1

µA

CS = DV

DD

, Inputs tied to 

DV

DD

 

OR

 DGND

Internal capacitance (all inputs and 
outputs)

C

INT

7

pF

T

A

 = 25°C, SCK = 1.0 MHz 

DV

DD

 = 3.3V 

(Note 1)

Note 1:

This parameter is periodically sampled and not 100% tested.

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DS25048B-page 7

MCP3903

FIGURE 1-1:

Serial Output Timing Diagram.

 

FIGURE 1-2:

 Serial Input Timing Diagram.

TEMPERATURE CHARACTERISTICS

Electrical Specifications:

 Unless otherwise indicated, all parameters apply at AV

DD 

= 4.5 to 5.5V, DV

DD

 = 2.7 to 

3.3 V.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Temperature Ranges

Operating Temperature Range

T

A

-40

+125

°C

(Note 1)

Storage Temperature Range

T

A

-65

+150

°C

Thermal Package Resistances

Thermal Resistance, 28-lead 
SSOP

 θ

JA

71

°C/W

Note 1:

The internal junction temperature (T

J

) must not exceed the absolute maximum specification of +150°C.

t

CSH

t

DIS

t

HI

t

LO

f

SCK

CS

SCK

SDO

MSB out

LSB out

Don’t Care

SDI

Mode 1,1
Mode 0,0

t

HO

t

DO

CS

SCK

SDI

LSB in

MSB in

Mode 1,1
Mode 0,0

t

CSS

t

SU

t

HD

t

CSD

t

CSH

t

CLD

t

CLE

SDO

HI-Z

t

HI

t

LO

f

SCK

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background image

MCP3903

DS25048B-page 8

© 2011 Microchip Technology Inc.

H

FIGURE 1-3:

Data Ready Pulse Timing Diagram.

H

FIGURE 1-4:

Specific Timing Diagrams.

 

FIGURE 1-5:

MCP3903 Clock Detail.

DR

SCK

SDO

1 / DRCLK

t

DODR

t

DRP

CS

V

IH

Timing Waveform for t

DIS

HI-Z

90%

10%

t

DIS

SDO

SCK

SDO

t

DO

Timing Waveform for t

DO

MDAT0/1

OSC1/CLKI

Timing Waveform for MDAT0/1

Modulator Output 

t

DOMDAT

CLKEXT

1

0

PRESCALE<1:0>

1 / 

MCLK

AMCLK

1 / 4

DMCLK

1 / OSR

DRCLK

OSR<1:0>

Multiplexer

Clock Divider

Clock Divider

Clock Divider

Crystal
Oscillator

OSC1

OSC2

Prescale

f

S

 ADC

Sampling

Rate

f

D

 ADC

Output
Data Rate

Digital Buffer

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background image

© 2011 Microchip Technology Inc.

DS25048B-page 9

MCP3903

2.0

TYPICAL PERFORMANCE CURVES

Note:

 Unless otherwise indicated, AV

DD

 = 5.0V, DV

DD 

= 3.3 V; Internal V

REF

; T

A

 = +25°C, MCLK = 4 MHz; PRESCALE

= 1; OSR = 64; GAIN = 1; Dithering OFF; V

IN

 = -0.5 dBFS @ 60 Hz.

.

FIGURE 2-1:

Spectral Response.

FIGURE 2-2:

Spectral Response.

FIGURE 2-3:

Spectral Response.

FIGURE 2-4:

Spectral Response.

FIGURE 2-5:

Spectral Response.

FIGURE 2-6:

Spectral Response.

Note:

The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

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background image

MCP3903

DS25048B-page 10

© 2011 Microchip Technology Inc.

Note:

 Unless otherwise indicated, AV

DD

 = 5.0V, DV

DD 

= 3.3 V; T

A

 = +25°C, MCLK = 4 MHz; PRESCALE = 1; OSR =

64; GAIN = 1; Dithering OFF; V

IN

 = -0.5 dBFS @ 60 Hz.

.

FIGURE 2-7:

Spectral Response.

FIGURE 2-8:

Spurious Free Dynamic 

Range vs Oversampling Ratio.

FIGURE 2-9:

Signal-to-Noise and 

Distortion vs. Oversampling Ratio.

FIGURE 2-10:

Signal-to-Noise and 

Distortion vs. Gain (Dithering OFF).

FIGURE 2-11:

Signal-to-Noise and 

Distortion vs. Gain (Dithering ON).

FIGURE 2-12:

Total Harmonic Distortion 

vs. Oversampling Ratio.

120

ic

Dithering ON

80

100

120

D

ynamic

B

)

Dithering ON

Dithering OFF

60

80

100

120

Free Dynamic 

n

ge (dB)

Dithering ON

Dithering OFF

40

60

80

100

120

rious Free Dynamic 

Range (dB)

Dithering ON

Dithering OFF

0

20

40

60

80

100

120

Spurious Free Dynamic 

Range (dB)

Dithering ON

Dithering OFF

0

20

40

60

80

100

120

32

64

128

256

Spurious Free Dynamic 

Range (dB)

Oversampling Ratio (OSR)

Dithering ON

Dithering OFF

0

20

40

60

80

100

120

32

64

128

256

Spurious Free Dynamic 

Range (dB)

Oversampling Ratio (OSR)

Dithering ON

Dithering OFF

120

80

100

120

B

)

Dithering  OFF

Dithering  ON

60

80

100

120

N

AD (dB)

Dithering  OFF

Dithering  ON

40

60

80

100

120

SINAD (dB)

Dithering  OFF

Dithering  ON

0

20

40

60

80

100

120

SINAD (dB)

Dithering  OFF

Dithering  ON

0

20

40

60

80

100

120

32

64

128

256

SINAD (dB)

Oversampling Ratio (OSR)

Dithering  OFF

Dithering  ON

0

20

40

60

80

100

120

32

64

128

256

SINAD (dB)

Oversampling Ratio (OSR)

Dithering  OFF

Dithering  ON

95

100

85

90

95

100

B

)

OSR = 256

70

75

80

85

90

95

100

N

AD (dB)

OSR = 256

OSR = 128

OSR = 64

60

65

70

75

80

85

90

95

100

SINAD (dB)

OSR = 256

OSR = 128

OSR = 32

OSR = 64

50

55

60

65

70

75

80

85

90

95

100

SINAD (dB)

OSR = 256

OSR = 128

OSR = 32

OSR = 64

50

55

60

65

70

75

80

85

90

95

100

1

2

4

8

16

32

SINAD (dB)

GAIN (V/V)

OSR = 256

OSR = 128

OSR = 32

OSR = 64

50

55

60

65

70

75

80

85

90

95

100

1

2

4

8

16

32

SINAD (dB)

GAIN (V/V)

OSR = 256

OSR = 128

OSR = 32

OSR = 64

95

100

85

90

95

100

)

OSR = 256

75

80

85

90

95

100

A

D (dB)

OSR = 256

OSR = 128

65

70

75

80

85

90

95

100

SINAD (dB)

OSR = 256

OSR = 128

OSR = 64

55

60

65

70

75

80

85

90

95

100

SINAD (dB)

OSR = 256

OSR = 128

OSR = 64

OSR = 32

50

55

60

65

70

75

80

85

90

95

100

1

2

4

8

16

32

SINAD (dB)

OSR = 256

OSR = 128

OSR = 64

OSR = 32

50

55

60

65

70

75

80

85

90

95

100

1

2

4

8

16

32

SINAD (dB)

GAIN (V/V)

OSR = 256

OSR = 128

OSR = 64

OSR = 32

Maker
Microchip Technology Inc.
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