2014 Microchip Technology Inc.
DS00001872A-page 1
Product Features
• General Features
- 3.3 Volt Operation (SIO Block is 5 Volt Toler-
ant)
- Programmable Wake-up Event (PME) Inter-
face
- PC99, PC2001 Compliant
- ACPI 2.0 Compliant
- Serial IRQ Interface Compatible with Serial-
ized IRQ Support for PCI Systems
- ISA Plug-and-Play Compatible Register Set
- Four Address Options for Power On Configu-
ration Port
- System Management Interrupt (SMI)
- 40 General Purpose I/O pins
- 6 GPIO with VID compatible inputs
- Support for power button on PS/2 Keyboard
- Security Key Register (32 byte) for Device
Authentication
• Low Pin Count Bus (LPC) Interface
- Supports LPC Bus frequencies of 19MHz to
33MHz
• Watchdog Timer
• Resume and Main Power Good Generator
• Programmable Clock Output to 16 HZ.
• 2.88MB Super I/O Floppy Disk Controller
- Licensed CMOS 765B Floppy Disk Controller
- Supports Two Floppy Drives
- Configurable Open Drain/Push-Pull
- Supports Vertical Recording Format
- 16-Byte Data FIFO
- 100% IBM® Compatibility
- Detects All Overrun and Underrun Conditions
- Sophisticated Power Control Circuitry (PCC)
Including Multiple Powerdown Modes for
Reduced Power Consumption
- DMA Enable Logic
- Data Rate and Drive Control Registers
- 480 Address, Up to Eight IRQ and Four DMA
Options
- Support FDD Interface on Parallel Port Pins
• Enhanced Digital Data Separator
- 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250
Kbp Data Rates
- Programmable Precompensation Modes
• Keyboard Controller
- 8042 Software Compatible
- 8 Bit Microcomputer
- 2k Bytes of Program ROM
- 256 Bytes of Data RAM
- Four Open Drain Outputs Dedicated for Key-
board/Mouse Interface
- Asynchronous Access to Two Data Registers
and One Status Register
- Supports Interrupt and Polling Access
- 8 Bit Counter Timer
- Port 92 Support
- Fast Gate A20 and KRESET Outputs
- Phoenix Keyboard BIOS ROM
• Multiple Serial Ports
- SCH3112 - 2 Full Function Serial Ports
- SCH3114 - 4 Full Function Serial Ports
- SCH3116 - 4 Full Function and 2 Four-Pin
Serial Ports
- High Speed NS16C550A Compatible UARTs
with
- Send/Receive 16-Byte FIFOs
- Supports 230k, 460k, 921k and 1.5M Baud
- Programmable Baud Rate Generator
- Modem Control Circuitry
- 480 Address and 15 IRQ Options
- Support IRQ Sharing among serial ports
- RS485 Auto Direction Control Mode
• Infrared Port
- Multiprotocol Infrared Interface
- IrDA 1.0 Compliant
- SHARP ASK IR
- 480 Addresses, Up to 15 IRQ
• Multi-Mode™ Parallel Port with ChiProtect™
- Standard Mode IBM PC/XT
®,
PC/AT
®
, and
PS/2™ Compatible Bi-directional Parallel
Port
- Enhanced Parallel Port (EPP) Compatible -
EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant)
SCH3112/SCH3114/SCH3116
LPC IO with 8042 KBC, Reset Generation, HWM and
Multiple Serial Ports
SCH3112/SCH3114/SCH3116
DS00001872A-page 2
2014 Microchip Technology Inc.
- IEEE 1284 Compliant Enhanced Capabilities
Port (ECP)
- ChiProtect Circuitry for Protection
- 960 Address, Up to 15 IRQ and Four DMA
Options
• Hardware Monitor
- Monitor Power supplies (+2.5V, +5V, +12V,
Vccp (processor voltage), VCC, Vbat and Vtr.
- Remote Thermal Diode Sensing for Two
External Temperature Measurements accu-
rate to 1.5
o
C
- Internal Ambient Temperature Measurement
- Limit Comparison of all Monitored Values
- Programmable Automatic FAN control based
on temperature
- nHWM_INT Pin for out-of-limit Temperature
or Voltage Indication
- Thermtrip signal for over temperature indica-
tion
• IDE Reset Output and 3 PCI Reset Buffers with
Software Control Capability (SCH3112 and
SCH3114 Only)
• Power Button Control and AC Power Failure
Recovery (SCH3112 and SCH3114 Only)
• Temperature Range Available
- Industrial (+85
°C to -40°C)
- Commercial (+70
°C to 0°C)
• 128 Pin VTQFP RoHS Compliant Package
TO OUR VALUED CUSTOMERS
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The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for cur-
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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2014 Microchip Technology Inc.
DS00001872A-page 3
SCH3112/SCH3114/SCH3116
1.0 General Description ........................................................................................................................................................................ 4
2.0 Pin Layout ....................................................................................................................................................................................... 6
3.0 Block Diagram ............................................................................................................................................................................... 23
4.0 Power Functionality ....................................................................................................................................................................... 24
5.0 SIO Overview ................................................................................................................................................................................ 27
6.0 LPC Interface ................................................................................................................................................................................ 28
7.0 Floppy Disk Controller ................................................................................................................................................................... 30
8.0 Serial Port (UART) ........................................................................................................................................................................ 63
9.0 Parallel Port .................................................................................................................................................................................. 82
10.0 Power Management .................................................................................................................................................................. 100
11.0 Serial IRQ ................................................................................................................................................................................. 101
12.0 8042 Keyboard Controller Description ...................................................................................................................................... 104
13.0 General Purpose I/O (GPIO) ..................................................................................................................................................... 113
14.0 System Management Interrupt (SMI) ........................................................................................................................................ 122
15.0 PME Support ............................................................................................................................................................................. 123
16.0 Watchdog Timer ........................................................................................................................................................................ 128
17.0 Programmable Clock Output ..................................................................................................................................................... 129
18.0 Reset Generation ...................................................................................................................................................................... 130
19.0 Buffered PCI Outputs ................................................................................................................................................................ 133
20.0 Power Control Features ............................................................................................................................................................ 135
21.0 Low Battery Detection Logic ..................................................................................................................................................... 148
22.0 Battery Backed Security Key Register ...................................................................................................................................... 150
23.0 Temperature Monitoring and Fan Control ................................................................................................................................. 152
24.0 Hardware Monitoring Register Set ............................................................................................................................................ 186
25.0 Config Registers ....................................................................................................................................................................... 224
26.0 Runtime Register ...................................................................................................................................................................... 245
27.0 Valid Power Modes ................................................................................................................................................................... 286
28.0 Operational Description ............................................................................................................................................................ 287
29.0 Timing Diagrams ....................................................................................................................................................................... 295
30.0 Package Outline ........................................................................................................................................................................ 317
Appendix A: ADC Voltage Conversion .............................................................................................................................................. 318
Appendix B: Example Fan Circuits ................................................................................................................................................... 319
Appendix C: Test Mode .................................................................................................................................................................... 322
Appendix D: Revision History ........................................................................................................................................................... 325
Product Identification System ........................................................................................................................................................... 326
The Microchip Web Site .................................................................................................................................................................... 327
Customer Change Notification Service ............................................................................................................................................. 327
Customer Support ............................................................................................................................................................................. 327
SCH3112/SCH3114/SCH3116
DS00001872A-page 4
2014 Microchip Technology Inc.
1.0
GENERAL DESCRIPTION
The SCH3112/SCH3114/SCH3116 Product Family is a 3.3V (Super I/O Block is 5V tolerant) PC99/PC2001 compliant
Super I/O controller with an LPC interface. The SCH3112/SCH3114/SCH3116 Product Family also includes Hardware
Monitoring capabilities, enhanced Security features, Power Control logic and Motherboard Glue logic.
The SCH3112/SCH3114/SCH3116 Product Family's hardware monitoring capability includes temperature, voltage and
fan speed monitoring. It has the ability to alert the system of out-of-limit conditions and automatically control the speeds
of multiple fans. There are four analog inputs for monitoring external voltages of +5V, +2.5V, +12V and Vccp (core pro-
cessor voltage), as well as internal monitoring of the SIO's VCC, VTR, and Vbat power supplies. The
SCH3112/SCH3114/SCH3116 Product Family includes support for monitoring two external temperatures via thermal
diode inputs and an internal sensor for measuring ambient temperature. The nHWM_INT pin is implemented to indicate
out-of-limit temperature, voltage, and FANTACH conditions. The hardware monitoring block of the
SCH3112/SCH3114/SCH3116 Product Family is accessible via the LPC bus. The same interrupt event reported on the
nHWM_INT pin also creates PME wakeup events. A separate THERMTRIP output is available, which generates a pulse
output on a programmed over temperature condition. This can be used to generate an reset or shutdown indicator to
the system.
The hardware monitoring capability also has programmable automatic FAN control. Three fan tachometer inputs and
three pulse width modulator (PWM) outputs are available.
The Motherboard Glue logic includes various power management and system logic including generation of nRSMRST,
a programmable Clock output, and reset generation. The reset generation includes a watchdog timer which can be used
to generate a reset pulse. The width of this pulse is selectable via an external strapping option.
The SCH3112/SCH3114/SCH3116 Product Family incorporates complete legacy Super I/O functionality including an
8042 based keyboard and mouse controller, an IEEE 1284, EPP, and ECP compatible parallel port, multiple serial ports,
one IrDA 1.0 infrared ports, and a floppy disk controller with Microchip's true CMOS 765B core and enhanced digital
data separator, The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures and
is software and register compatible with Microchip's proprietary 82077AA core. System related functionality, which offers
flexibility to the system designer, General Purpose I/O control functions, and control of two LED's.
The serial ports are fully functional NS16550 compatible UARTs that support data rates up to 1.5 Mbps. There are four,
8 pin Serial Ports and two, 4pin Serial Ports. The reduced pin serial ports have selectable input and output controls. The
Serial Ports contain programmable direction control, which will automatically Drive nRTS when the Output Buffer is
loaded, then Drive nRTS when the Output Buffer is Empty.
The SCH3112/SCH3114/SCH3116 Product Family is ACPI 1.0/2.0 compatible and therefore supports multiple low
power-down modes. It incorporates sophisticated power control circuitry (PCC), which includes support for keyboard.
The SCH3112/SCH3114/SCH3116 Product Family supports the ISA Plug-and-Play Standard register set (Version 1.0a).
The I/O Address, DMA Channel and hardware IRQ of each logical device in the SCH3112/SCH3114/SCH3116 Product
Family may be reprogrammed through the internal configuration registers. There are up to 480 (960 - Parallel Port) I/O
address location options, a Serialized IRQ interface, and Three DMA channels.
2014 Microchip Technology Inc.
DS00001872A-page 5
SCH3112/SCH3114/SCH3116
Note 1: Legacy Blocks include floppy disk, parallel port, watchdog timer and keyboard controller
2: 2 of the 6 serial ports have 4 pin interfaces
1.1
Reference Documents
1.
Intel Low Pin Count Specification, Revision 1.0, September 29, 1997
2.
PCI Local Bus Specification, Revision 2.2, December 18, 1998
3.
Advanced Configuration and Power Interface Specification, Revision 1.0b, February 2, 1999
4.
IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993.
5.
Hardware Description of the 8042, Intel 8 bit Embedded Controller Handbook.
6.
SMSC Application Note (AN 8-8) “Keyboard and Mouse Wakeup Functionality”, dated 03/23/02.
TABLE 1-1:
DEVICE SPECIFIC SUMMARY
Function
SCH3112
SCH3114
SCH3116
LPC Bus Interface
YES
YES
YES
Legacy functional
Blocks
(
1
)
YES
YES
YES
Floppy on Parallel
Port Option
YES
YES
YES
Reset Generator
YES
YES
YES
Serial Ports
2
4
6
(
2
)
Programmable Clock
Output
YES
YES
YES
IDE / PCI Reset
Outputs
YES
YES
NO
Power Button / AC
Fail Support
YES
YES
NO
GPIOs
40
40
40
GPIO with VID
Compatible Inputs
6
6
6
Dedicated GPIOs
16
0
0
Hardware Monitor
YES
YES
YES
SCH3112/SCH3114/SCH3116
DS00001872A-page 6
2014 Microchip Technology Inc.
2.0
PIN LAYOUT
FIGURE 2-1:
SCH3112 PIN DIAGRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
12
8
12
7
12
6
12
5
12
4
12
3
12
2
12
1
12
0
11
9
11
8
11
7
11
6
11
5
11
4
11
3
11
2
11
1
11
0
10
9
10
8
10
7
10
6
10
5
10
4
10
3
10
2
10
1
10
0
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
SCH3112
128 PIN VTQFP
nP
CI
RS
T
3
/ G
P
4
7
AV
S
S
VB
AT
G
P
2
7
/ n
IO
_
S
M
I /
P
1
7
KDA
T /
G
P
2
1
KCL
K /
G
P
2
2
MD
A
T
/
G
P
3
2
MC
L
K
/ G
P
3
3
GP
3
6
/
n
KBDR
ST
G
P
37 /
A
20M
VS
S
VT
R
nI
NI
T /
nD
IR
n
S
CL
TI
N /
nS
TE
P
PD
0
/
n
IND
E
X
PD
1 /
nT
RK
0
PD2
/
nW
RT
PR
T
PD3
/
n
R
D
A
TA
P
D
4 /
nDSK
CHG
PD
5
PD
6 /
nM
TR
0
PD
7
VS
S
SL
C
T
/
n
W
G
A
TE
PE
/
n
W
DA
T
A
B
U
S
Y /
nM
TR
1
nA
CK
/
nDS
1
nE
R
R
OR
/
nHDS
EL
nA
LF
/
D
R
VDE
N
0
n
S
TR
O
B
E
/
nDS
0
nRI
1
nD
C
D
1
+12V_IN
+5V_IN
GP40 /DRVDEN0
VTR
nMTR0
nDSKCHG
nDS0
VSS
nDIR
nSTEP
nWDATA
nWGATE
nHDSEL
nINDEX
nTRK0
nWRTPRT
nRDATA
CLOCKI
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ#
PCI_RESET#
PCI_CLK
SER_IRQ
VSS
VCC
nIDE_RSTDRV/GP44
nPCRST1 / GP45
nPCIRST2 / GP46
+2
.5
V
_
IN
VCCP
_
IN
REMO
T
E
1
+
REMO
T
E
1
-
REMO
T
E
2
+
REMO
T
E
2
-
HVTR
HVSS
F
A
NT
A
C
H1
F
A
NT
A
C
H2
F
A
NT
A
C
H3
PW
M
1
PW
M
2
PW
M
3
nH
W
M
_
IN
T
n
T
HE
RM
T
R
IP
VSS
VT
R
n
F
PR
ST
/G
P3
0
PW
RGD
_
PS
PW
RGD
_
OUT
GP
3
4
GP
6
2
*
GP
6
7
*
GP
6
6
*
GP
6
5
*
GP
6
4
*
VSS
nR
S
M
R
S
T
CL
K
I3
2
GP
6
3
*
GP
3
1
GP12
GP13
GP60 / nLED1 / WDT
GP61 / nLED2/ CLKO
GP15
VTR
GP42 / nIO_PME
GP16
GP17
GP14
GP11
GP10
SLP_SX#
PB_IN#
PS_ON#
PB_OUT#
GP57 / nDTR2
GP56/ nCTS2
GP55/nRTS2/RESGEN
GP54 / nDSR2
GP53 / TXD2 (IRTX2)
GP52 / RXD2 (IRRX2)
GP51 / nDCD2
VSS
VTR
GP50 / nRI2
nDTR1 / SYSOPT1
nCTS1
nRTS1 / SYSOPT0
nDSR1
TXD1 /SIOXNOROUT
RXD1
HVTR
VTR
V
C
C
VCC
V
C
C
Note:
SYSOPT1 Pin 68
SYSOPT0 Pin 70 and
RESGEN Pin 78 are only sampled during power on configuration
VBAT
HVTR
VTR
VCC
VCC
VCC
V
T
R
V
T
R
2014 Microchip Technology Inc.
DS00001872A-page 7
SCH3112/SCH3114/SCH3116
2.1
SCH311X Pin Layout Summary
TABLE 2-1:
SCH3112 SUMMARY - 2 SERIAL PORTS
PIN#
NAME
PIN#
NAME
PIN#
NAME
PIN#
NAME
1
+12V_IN
33
nPCIRST3 /
GP47
65
RXD1
97
GP31
2
+5V_IN
34
AVSS
66
TXD1/
SIO XNOR_OUT
98
GP63*
3
GP40 /
DRVDEN0
35
VBAT
67
nDSR1
99
CLKI32
4
VTR
36
GP27/nIO_SMI/P17
68
nRTS1/SYSOPT0
100
nRSMRST
5
nMTR0
37
KDAT/GP21
69
nCTS1
101
VSS
6
nDSKCHG
38
KCLK/GP22
70
nDTR1/SYSOPT1
102
GP64*
7
nDS0
39
MDAT/GP32
71
GP50 / nRI2
103
GP65*
8
VSS
40
MCLK/GP33
72
VTR
104
GP66*
9
nDIR
41
GP36/nKBDRST
73
VSS
105
GP67*
10
nSTEP
42
GP37/A20M
74
GP51 / nDCD2
106
GP62*
11
nWDATA
43
VSS
75
GP52 /
RXD2(IRRX2)
107
GP34
12
nWGATE
44
VTR
76
GP53 /
TXD2(IRTX2)
108
PWRGD_OUT
13
nHDSEL
45
nINIT / nDIR
77
GP54 / nDSR2
109
PWRGD_PS
14
nINDEX
46
nSLCTIN / nSTEP
78
GP55 / nRTS2 /
RESGEN
110
nFPRST / GP30
15
nTRK0
47
PD0 / nINDEX
79
GP56 / nCTS2
111
VTR
16
nWRTPRT
48
PD1 / nTRK0
80
GP 57 / nDTR2
112
VSS
17
nRDATA
49
PD2 / nWRTPRT
81
PB_OUT#
113
nTHERMTRIP
18
CLOCKI
50
PD3 / nRDATA
82
PS_ON#
114
nHWM_INT
19
LAD0
51
PD4 / nDSKCHG
83
PB_IN#
115
PWM3
20
LAD1
52
PD5
84
SLP_SX# 116
PWM2
21
LAD2
53
PD6 / nMTR0
85
GP10
117
PWM1
22
LAD3
54
PD7
86
GP11
118
FANTACH3
23
LFRAME#
55
VSS 87
GP14
119
FANTACH2
24
LDRQ#
56
SLCT / nWGATE
88
GP17
120
FANTACH1
25
PCI_RESET#
57
PE / nWDATA
89
GP16
121
HVSS
26
PCI_CLK
58
BUSY / nMTR1
90
GP42/nIO_PME_
122
HVTR
27
SER_IRQ
59
nACK / nDS1
91
VTR
123
REMOTE2-
28
VSS
60
nERROR / nHDSEL 92
GP15
124
REMOTE2+
29
VCC
61
nALF / DRVDEN0
93
GP61/nLED2/CLKO 125
REMOTE1-
30
nIDE_RSTDRV /
GP44
62
nSTROBE / nDS0
94
GP60/nLED1/WDT
126
REMOTE1+
31
nPCIRST1 /
GP45
63
nRI1
95
GP13
127
VCCP_IN
32
nPCIRST2 /
GP46
64
nDCD1
96
GP12 128
+2.5V_IN
SCH3112/SCH3114/SCH3116
DS00001872A-page 8
2014 Microchip Technology Inc.
FIGURE 2-2:
SCH3114 PIN DIAGRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
SCH3114
128 PIN VTQFP
nPCI
RST 3
/ GP
4
7
A
VSS
VBAT
G
P
2
7
/ n
IO
_
S
M
I /
P
1
7
K
DAT /
GP
2
1
K
C
L
K
/ G
P
2
2
M
DAT /
GP
3
2
MC
L
K
/ G
P
3
3
GP3
6
/
n
KB
DRST
G
P
37 /
A
20M
VSS
VTR
nI
NI
T /
nDI
R
nSCLTI
N /
nSTEP
PD
0
/
n
IND
E
X
PD1
/
nTRK0
PD2 /
nW
RTPRT
PD
3
/
nRD
A
TA
P
D
4
/
nD
SKCH
G
PD5
PD6 /
nM
TR0
PD7
VSS
SLC
T
/
nW
G
A
TE
P
E
/
nW
D
A
TA
BU
SY /
nM
TR1
nA
CK /
nDS1
nER
R
OR
/
nH
DSEL
nALF /
DRV
DEN0
nSTRO
B
E /
nDS0
nR
I1
n
D
CD1
+12V_IN
+5V_IN
GP40 /DRVDEN0
VTR
nMTR0
nDSKCHG
nDS0
VSS
nDIR
nSTEP
nWDATA
nWGATE
nHDSEL
nINDEX
nTRK0
nWRTPRT
nRDATA
CLOCKI
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ#
PCI_RESET#
PCI_CLK
SER_IRQ
VSS
VCC
nIDE_RSTDRV/GP44
nPCRST1 / GP45
nPCIRST2 / GP46
+
2
.5
V
_
IN
VC
CP_I
N
RE
MO
TE1
+
RE
MO
TE1
-
RE
MO
TE2
+
RE
MO
TE2
-
HV
TR
HV
SS
FAN
T
ACH
1
FAN
T
ACH
2
FAN
T
ACH
3
PW
M
1
PW
M
2
PW
M
3
nHW
M
_I
NT
nTHE
R
M
T
R
IP
VS
S
VTR
nFPR
S
T/
GP30
PW
R
G
D_P
S
PW
R
G
D_O
U
T
G
P
34 /
nD
T
R
4
G
P
62*
/
n
C
TS4
G
P
67*
/
n
R
TS4
G
P
66*
/
n
D
SR
4
G
P
65*
/
T
X
D
4
G
P
6
4
* /
RXD4
VS
S
nRS
M
R
S
T
CLK
I3
2
G
P
63*
/
n
D
C
D
4
G
P
31 /
nR
I4
GP12 / nDCD3
GP13 / nRI3
GP60 / nLED1 / WDT
GP61 / nLED2/ CLKO
GP15 / nDTR3
VTR
GP42 / nIO_PME
GP16 / nCTS3
GP17 / nRTS3
GP14 / nDSR3
GP11 / TXD3
GP10 / RXD3
SLP_SX#
PB_IN#
PS_ON#
PB_OUT#
GP57 / nDTR2
GP56/ nCTS2
GP55/nRTS2/RESGEN
GP54 / nDSR2
GP53 / TXD2 (IRTX2)
GP52 / RXD2 (IRRX2)
GP51 / nDCD2
VSS
VTR
GP50 / nRI2
nDTR1 / SYSOPT1
nCTS1
nRTS1 / SYSOPT0
nDSR1
TXD1 /SIOXNOROUT
RXD1
HVTR
V
C
C
VCC
V
C
C
Note:
SYSOPT1 Pin 68
SYSOPT0 Pin 70 and
RESGEN Pin 78 are only sampled during power on cinfiguration
VBAT
HVTR
VTR
VCC
VCC
VCC
V
T
R
V
T
R
2014 Microchip Technology Inc.
DS00001872A-page 9
SCH3112/SCH3114/SCH3116
TABLE 2-2:
SCH3114 SUMMARY - 4 SERIAL PORTS
PIN#
NAME
PIN#
NAME
PIN#
NAME
PIN#
NAME
1
+12V_IN
33
nPCIRST3 /
GP47
65
RXD1
97
GP31 / nRI4
2
+5V_IN
34
AVSS
66
TXD1/
SIO XNOR_OUT
98
GP63* / nDCD4
3
GP40/DRVDEN0
35
VBAT
67
nDSR1
99
CLKI32
4
VTR
36
GP27/nIO_SMI/P17
68
nRTS1/SYSOPT0
100
nRSMRST
5
nMTR0
37
KDAT/GP21
69
nCTS1
101
VSS
6
nDSKCHG
38
KCLK/GP22
70
nDTR1/SYSOPT1
102
GP64* / RXD4
7
nDS0
39
MDAT/GP32
71
GP50 / nRI2
103
GP65* / TXD4
8
VSS
40
MCLK/GP33
72
VTR
104
GP66* / nDSR4
9
nDIR
41
GP36/nKBDRST
73
VSS
105
GP67* / nRTS4
10
nSTEP
42
GP37/A20M
74
GP51 / nDCD2
106
GP62* / nCTS4
11
nWDATA
43
VSS
75
GP52 /
RXD2(IRRX2)
107
GP34 / nDTR4
12
nWGATE
44
VTR
76
GP53 /
TXD2(IRTX2)
108
PWRGD_OUT
13
nHDSEL
45
nINIT / nDIR
77
GP54 / nDSR2
109
PWRGD_PS
14
nINDEX
46
nSLCTIN / nSTEP
78
GP55 / nRTS2 /
RESGEN
110
nFPRST / GP30
15
nTRK0
47
PD0 / nINDEX
79
GP56 / nCTS2
111
VTR
16
nWRTPRT
48
PD1 / nTRK0
80
GP 57 / nDTR2
112
VSS
17
nRDATA
49
PD2 / nWRTPRT
81
PB_OUT#
113
nTHERMTRIP
18
CLOCKI
50
PD3 / nRDATA
82
PS_ON#
114
nHWM_INT
19
LAD0
51
PD4 / nDSKCHG
83
PB_IN#
115
PWM3
20
LAD1
52
PD5
84
SLP_SX# 116
PWM2
21
LAD2
53
PD6 / nMTR0
85
GP10/RXD3
117
PWM1
22
LAD3
54
PD7
86
GP11 / TXD3
118
FANTACH3
23
LFRAME#
55
VSS
87
GP14 / nDSR3
119
FANTACH2
24
LDRQ#
56
SLCT / nWGATE
88
GP17 / nRTS3
120
FANTACH1
25
PCI_RESET#
57
PE / nWDATA
89
GP16 / nCTS3
121
HVSS
26
PCI_CLK
58
BUSY / nMTR1
90
GP42/nIO_PME_
122
HVTR
27
SER_IRQ
59
nACK / nDS1
91
VTR
123
REMOTE2-
28
VSS
60
nERROR / nHDSEL 92
GP15 / nDTR3
124
REMOTE2+
29
VCC
61
nALF / DRVDEN0
93
GP61/nLED2/CLKO 125
REMOTE1-
30
nIDE_RSTDRV /
GP44
62
nSTROBE / nDS0
94
GP60/nLED1/WDT
126
REMOTE1+
31
nPCIRST1 /
GP45
63
nRI1
95
GP13 / nRI3
127
VCCP_IN
32
nPCIRST2 /
GP46
64
nDCD1
96
GP12 / nDCD3
128
+2.5V_IN
SCH3112/SCH3114/SCH3116
DS00001872A-page 10
2014 Microchip Technology Inc.
FIGURE 2-3:
SCH116 PIN DIAGRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
SCH3116
128 PIN VTQFP
GP
4
7
/n
SC
OU
T
6
AV
SS
VBA
T
G
P
2
7
/
n
IO
_
S
M
I
/
P
1
7
K
DAT
/
GP
2
1
KC
L
K
/
G
P
2
2
M
DAT
/
GP
3
2
MC
L
K
/ G
P
3
3
GP3
6
/
n
K
B
DRS
T
G
P
37 /
A
20
M
VS
S
VT
R
nI
NI
T /
n
D
IR
nS
CLTI
N /
n
S
TE
P
PD
0 /
n
IND
EX
P
D
1
/
n
T
RK0
PD
2
/
nW
R
T
P
R
T
PD3
/
nR
DA
TA
P
D
4
/
n
D
SKCH
G
PD5
PD6 /
nM
TR0
PD7
VS
S
SL
CT /
n
W
GA
TE
PE /
n
W
DA
TA
B
U
SY /
nM
TR1
nA
CK
/
nDS1
n
E
R
R
O
R
/
n
H
D
S
E
L
nAL
F
/
DRV
DEN0
nST
R
O
B
E
/
nDS0
nRI
1
n
D
CD1
+12V_IN
+5V_IN
GP40 /DRVDEN0
VTR
nMTR0
nDSKCHG
nDS0
VSS
nDIR
nSTEP
nWDATA
nWGATE
nHDSEL
nINDEX
nTRK0
nWRTPRT
nRDATA
CLOCKI
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ#
PCI_RESET#
PCI_CLK
SER_IRQ
VSS
VCC
GP44 / TXD6
GP45 / RXD6
GP46 / nSCIN6
+2
.5
V
_
IN
V
CCP
_
IN
RE
MO
TE1+
RE
MO
TE1-
RE
MO
TE2+
RE
MO
TE2-
HV
T
R
H
VSS
FAN
T
ACH
1
FAN
T
ACH
2
FAN
T
ACH
3
PW
M
1
PW
M
2
PW
M
3
nHW
M
_
INT
nT
HE
RM
TR
IP
VS
S
VTR
nF
PR
ST
/G
P
3
0
P
W
RG
D_
PS
P
W
RG
D_
OU
T
G
P
3
4
/
n
D
T
R
4
GP
6
2
* /
n
C
T
S
4
GP
6
7
* /
n
R
T
S
4
GP
6
6
* /
n
D
SR
4
GP
6
5
* /
T
X
D4
G
P
64
* /
RXD4
VS
S
nRS
M
R
S
T
CLK
I3
2
GP
6
3
* /
n
D
CD
4
G
P
3
1
/
n
R
I4
GP12 / nDCD3
GP13 / nRI3
GP60 / nLED1 / WDT
GP61 / nLED2/ CLKO
GP15 / nDTR3
VTR
GP42 / nIO_PME
GP16 / nCTS3
GP17 / nRTS3
GP14 / nDSR3
GP11 / TXD3
GP10 / RXD3
nSCIN5
nSCOUT5
TXD5
RXD5
GP57 / nDTR2
GP56/ nCTS2
GP55/nRTS2/RESGEN
GP54 / nDSR2
GP53 / TXD2 (IRTX2)
GP52 / RXD2 (IRRX2)
GP51 / nDCD2
VSS
VTR
GP50 / nRI2
nDTR1 / SYSOPT1
nCTS1
nRTS1 / SYSOPT0
nDSR1
TXD1 /SIOXNOROUT
RXD1
HVTR
V
C
C
VCC
V
C
C
Note:
SYSOPT1 Pin 68
SYSOPT0 Pin 70 and
RESGEN Pin 78 are only sampled during power on configuration
VBAT
HVTR
VTR
VCC
VCC
VCC
V
T
R
V
T
R
2014 Microchip Technology Inc.
DS00001872A-page 1
Product Features
• General Features
- 3.3 Volt Operation (SIO Block is 5 Volt Toler-
ant)
- Programmable Wake-up Event (PME) Inter-
face
- PC99, PC2001 Compliant
- ACPI 2.0 Compliant
- Serial IRQ Interface Compatible with Serial-
ized IRQ Support for PCI Systems
- ISA Plug-and-Play Compatible Register Set
- Four Address Options for Power On Configu-
ration Port
- System Management Interrupt (SMI)
- 40 General Purpose I/O pins
- 6 GPIO with VID compatible inputs
- Support for power button on PS/2 Keyboard
- Security Key Register (32 byte) for Device
Authentication
• Low Pin Count Bus (LPC) Interface
- Supports LPC Bus frequencies of 19MHz to
33MHz
• Watchdog Timer
• Resume and Main Power Good Generator
• Programmable Clock Output to 16 HZ.
• 2.88MB Super I/O Floppy Disk Controller
- Licensed CMOS 765B Floppy Disk Controller
- Supports Two Floppy Drives
- Configurable Open Drain/Push-Pull
- Supports Vertical Recording Format
- 16-Byte Data FIFO
- 100% IBM® Compatibility
- Detects All Overrun and Underrun Conditions
- Sophisticated Power Control Circuitry (PCC)
Including Multiple Powerdown Modes for
Reduced Power Consumption
- DMA Enable Logic
- Data Rate and Drive Control Registers
- 480 Address, Up to Eight IRQ and Four DMA
Options
- Support FDD Interface on Parallel Port Pins
• Enhanced Digital Data Separator
- 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250
Kbp Data Rates
- Programmable Precompensation Modes
• Keyboard Controller
- 8042 Software Compatible
- 8 Bit Microcomputer
- 2k Bytes of Program ROM
- 256 Bytes of Data RAM
- Four Open Drain Outputs Dedicated for Key-
board/Mouse Interface
- Asynchronous Access to Two Data Registers
and One Status Register
- Supports Interrupt and Polling Access
- 8 Bit Counter Timer
- Port 92 Support
- Fast Gate A20 and KRESET Outputs
- Phoenix Keyboard BIOS ROM
• Multiple Serial Ports
- SCH3112 - 2 Full Function Serial Ports
- SCH3114 - 4 Full Function Serial Ports
- SCH3116 - 4 Full Function and 2 Four-Pin
Serial Ports
- High Speed NS16C550A Compatible UARTs
with
- Send/Receive 16-Byte FIFOs
- Supports 230k, 460k, 921k and 1.5M Baud
- Programmable Baud Rate Generator
- Modem Control Circuitry
- 480 Address and 15 IRQ Options
- Support IRQ Sharing among serial ports
- RS485 Auto Direction Control Mode
• Infrared Port
- Multiprotocol Infrared Interface
- IrDA 1.0 Compliant
- SHARP ASK IR
- 480 Addresses, Up to 15 IRQ
• Multi-Mode™ Parallel Port with ChiProtect™
- Standard Mode IBM PC/XT
®,
PC/AT
®
, and
PS/2™ Compatible Bi-directional Parallel
Port
- Enhanced Parallel Port (EPP) Compatible -
EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant)
SCH3112/SCH3114/SCH3116
LPC IO with 8042 KBC, Reset Generation, HWM and
Multiple Serial Ports
SCH3112/SCH3114/SCH3116
DS00001872A-page 2
2014 Microchip Technology Inc.
- IEEE 1284 Compliant Enhanced Capabilities
Port (ECP)
- ChiProtect Circuitry for Protection
- 960 Address, Up to 15 IRQ and Four DMA
Options
• Hardware Monitor
- Monitor Power supplies (+2.5V, +5V, +12V,
Vccp (processor voltage), VCC, Vbat and Vtr.
- Remote Thermal Diode Sensing for Two
External Temperature Measurements accu-
rate to 1.5
o
C
- Internal Ambient Temperature Measurement
- Limit Comparison of all Monitored Values
- Programmable Automatic FAN control based
on temperature
- nHWM_INT Pin for out-of-limit Temperature
or Voltage Indication
- Thermtrip signal for over temperature indica-
tion
• IDE Reset Output and 3 PCI Reset Buffers with
Software Control Capability (SCH3112 and
SCH3114 Only)
• Power Button Control and AC Power Failure
Recovery (SCH3112 and SCH3114 Only)
• Temperature Range Available
- Industrial (+85
°C to -40°C)
- Commercial (+70
°C to 0°C)
• 128 Pin VTQFP RoHS Compliant Package
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
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. We welcome your feedback.
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The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for cur-
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are
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2014 Microchip Technology Inc.
DS00001872A-page 3
SCH3112/SCH3114/SCH3116
1.0 General Description ........................................................................................................................................................................ 4
2.0 Pin Layout ....................................................................................................................................................................................... 6
3.0 Block Diagram ............................................................................................................................................................................... 23
4.0 Power Functionality ....................................................................................................................................................................... 24
5.0 SIO Overview ................................................................................................................................................................................ 27
6.0 LPC Interface ................................................................................................................................................................................ 28
7.0 Floppy Disk Controller ................................................................................................................................................................... 30
8.0 Serial Port (UART) ........................................................................................................................................................................ 63
9.0 Parallel Port .................................................................................................................................................................................. 82
10.0 Power Management .................................................................................................................................................................. 100
11.0 Serial IRQ ................................................................................................................................................................................. 101
12.0 8042 Keyboard Controller Description ...................................................................................................................................... 104
13.0 General Purpose I/O (GPIO) ..................................................................................................................................................... 113
14.0 System Management Interrupt (SMI) ........................................................................................................................................ 122
15.0 PME Support ............................................................................................................................................................................. 123
16.0 Watchdog Timer ........................................................................................................................................................................ 128
17.0 Programmable Clock Output ..................................................................................................................................................... 129
18.0 Reset Generation ...................................................................................................................................................................... 130
19.0 Buffered PCI Outputs ................................................................................................................................................................ 133
20.0 Power Control Features ............................................................................................................................................................ 135
21.0 Low Battery Detection Logic ..................................................................................................................................................... 148
22.0 Battery Backed Security Key Register ...................................................................................................................................... 150
23.0 Temperature Monitoring and Fan Control ................................................................................................................................. 152
24.0 Hardware Monitoring Register Set ............................................................................................................................................ 186
25.0 Config Registers ....................................................................................................................................................................... 224
26.0 Runtime Register ...................................................................................................................................................................... 245
27.0 Valid Power Modes ................................................................................................................................................................... 286
28.0 Operational Description ............................................................................................................................................................ 287
29.0 Timing Diagrams ....................................................................................................................................................................... 295
30.0 Package Outline ........................................................................................................................................................................ 317
Appendix A: ADC Voltage Conversion .............................................................................................................................................. 318
Appendix B: Example Fan Circuits ................................................................................................................................................... 319
Appendix C: Test Mode .................................................................................................................................................................... 322
Appendix D: Revision History ........................................................................................................................................................... 325
Product Identification System ........................................................................................................................................................... 326
The Microchip Web Site .................................................................................................................................................................... 327
Customer Change Notification Service ............................................................................................................................................. 327
Customer Support ............................................................................................................................................................................. 327
SCH3112/SCH3114/SCH3116
DS00001872A-page 4
2014 Microchip Technology Inc.
1.0
GENERAL DESCRIPTION
The SCH3112/SCH3114/SCH3116 Product Family is a 3.3V (Super I/O Block is 5V tolerant) PC99/PC2001 compliant
Super I/O controller with an LPC interface. The SCH3112/SCH3114/SCH3116 Product Family also includes Hardware
Monitoring capabilities, enhanced Security features, Power Control logic and Motherboard Glue logic.
The SCH3112/SCH3114/SCH3116 Product Family's hardware monitoring capability includes temperature, voltage and
fan speed monitoring. It has the ability to alert the system of out-of-limit conditions and automatically control the speeds
of multiple fans. There are four analog inputs for monitoring external voltages of +5V, +2.5V, +12V and Vccp (core pro-
cessor voltage), as well as internal monitoring of the SIO's VCC, VTR, and Vbat power supplies. The
SCH3112/SCH3114/SCH3116 Product Family includes support for monitoring two external temperatures via thermal
diode inputs and an internal sensor for measuring ambient temperature. The nHWM_INT pin is implemented to indicate
out-of-limit temperature, voltage, and FANTACH conditions. The hardware monitoring block of the
SCH3112/SCH3114/SCH3116 Product Family is accessible via the LPC bus. The same interrupt event reported on the
nHWM_INT pin also creates PME wakeup events. A separate THERMTRIP output is available, which generates a pulse
output on a programmed over temperature condition. This can be used to generate an reset or shutdown indicator to
the system.
The hardware monitoring capability also has programmable automatic FAN control. Three fan tachometer inputs and
three pulse width modulator (PWM) outputs are available.
The Motherboard Glue logic includes various power management and system logic including generation of nRSMRST,
a programmable Clock output, and reset generation. The reset generation includes a watchdog timer which can be used
to generate a reset pulse. The width of this pulse is selectable via an external strapping option.
The SCH3112/SCH3114/SCH3116 Product Family incorporates complete legacy Super I/O functionality including an
8042 based keyboard and mouse controller, an IEEE 1284, EPP, and ECP compatible parallel port, multiple serial ports,
one IrDA 1.0 infrared ports, and a floppy disk controller with Microchip's true CMOS 765B core and enhanced digital
data separator, The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures and
is software and register compatible with Microchip's proprietary 82077AA core. System related functionality, which offers
flexibility to the system designer, General Purpose I/O control functions, and control of two LED's.
The serial ports are fully functional NS16550 compatible UARTs that support data rates up to 1.5 Mbps. There are four,
8 pin Serial Ports and two, 4pin Serial Ports. The reduced pin serial ports have selectable input and output controls. The
Serial Ports contain programmable direction control, which will automatically Drive nRTS when the Output Buffer is
loaded, then Drive nRTS when the Output Buffer is Empty.
The SCH3112/SCH3114/SCH3116 Product Family is ACPI 1.0/2.0 compatible and therefore supports multiple low
power-down modes. It incorporates sophisticated power control circuitry (PCC), which includes support for keyboard.
The SCH3112/SCH3114/SCH3116 Product Family supports the ISA Plug-and-Play Standard register set (Version 1.0a).
The I/O Address, DMA Channel and hardware IRQ of each logical device in the SCH3112/SCH3114/SCH3116 Product
Family may be reprogrammed through the internal configuration registers. There are up to 480 (960 - Parallel Port) I/O
address location options, a Serialized IRQ interface, and Three DMA channels.
2014 Microchip Technology Inc.
DS00001872A-page 5
SCH3112/SCH3114/SCH3116
Note 1: Legacy Blocks include floppy disk, parallel port, watchdog timer and keyboard controller
2: 2 of the 6 serial ports have 4 pin interfaces
1.1
Reference Documents
1.
Intel Low Pin Count Specification, Revision 1.0, September 29, 1997
2.
PCI Local Bus Specification, Revision 2.2, December 18, 1998
3.
Advanced Configuration and Power Interface Specification, Revision 1.0b, February 2, 1999
4.
IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993.
5.
Hardware Description of the 8042, Intel 8 bit Embedded Controller Handbook.
6.
SMSC Application Note (AN 8-8) “Keyboard and Mouse Wakeup Functionality”, dated 03/23/02.
TABLE 1-1:
DEVICE SPECIFIC SUMMARY
Function
SCH3112
SCH3114
SCH3116
LPC Bus Interface
YES
YES
YES
Legacy functional
Blocks
(
1
)
YES
YES
YES
Floppy on Parallel
Port Option
YES
YES
YES
Reset Generator
YES
YES
YES
Serial Ports
2
4
6
(
2
)
Programmable Clock
Output
YES
YES
YES
IDE / PCI Reset
Outputs
YES
YES
NO
Power Button / AC
Fail Support
YES
YES
NO
GPIOs
40
40
40
GPIO with VID
Compatible Inputs
6
6
6
Dedicated GPIOs
16
0
0
Hardware Monitor
YES
YES
YES
SCH3112/SCH3114/SCH3116
DS00001872A-page 6
2014 Microchip Technology Inc.
2.0
PIN LAYOUT
FIGURE 2-1:
SCH3112 PIN DIAGRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
12
8
12
7
12
6
12
5
12
4
12
3
12
2
12
1
12
0
11
9
11
8
11
7
11
6
11
5
11
4
11
3
11
2
11
1
11
0
10
9
10
8
10
7
10
6
10
5
10
4
10
3
10
2
10
1
10
0
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
SCH3112
128 PIN VTQFP
nP
CI
RS
T
3
/ G
P
4
7
AV
S
S
VB
AT
G
P
2
7
/ n
IO
_
S
M
I /
P
1
7
KDA
T /
G
P
2
1
KCL
K /
G
P
2
2
MD
A
T
/
G
P
3
2
MC
L
K
/ G
P
3
3
GP
3
6
/
n
KBDR
ST
G
P
37 /
A
20M
VS
S
VT
R
nI
NI
T /
nD
IR
n
S
CL
TI
N /
nS
TE
P
PD
0
/
n
IND
E
X
PD
1 /
nT
RK
0
PD2
/
nW
RT
PR
T
PD3
/
n
R
D
A
TA
P
D
4 /
nDSK
CHG
PD
5
PD
6 /
nM
TR
0
PD
7
VS
S
SL
C
T
/
n
W
G
A
TE
PE
/
n
W
DA
T
A
B
U
S
Y /
nM
TR
1
nA
CK
/
nDS
1
nE
R
R
OR
/
nHDS
EL
nA
LF
/
D
R
VDE
N
0
n
S
TR
O
B
E
/
nDS
0
nRI
1
nD
C
D
1
+12V_IN
+5V_IN
GP40 /DRVDEN0
VTR
nMTR0
nDSKCHG
nDS0
VSS
nDIR
nSTEP
nWDATA
nWGATE
nHDSEL
nINDEX
nTRK0
nWRTPRT
nRDATA
CLOCKI
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ#
PCI_RESET#
PCI_CLK
SER_IRQ
VSS
VCC
nIDE_RSTDRV/GP44
nPCRST1 / GP45
nPCIRST2 / GP46
+2
.5
V
_
IN
VCCP
_
IN
REMO
T
E
1
+
REMO
T
E
1
-
REMO
T
E
2
+
REMO
T
E
2
-
HVTR
HVSS
F
A
NT
A
C
H1
F
A
NT
A
C
H2
F
A
NT
A
C
H3
PW
M
1
PW
M
2
PW
M
3
nH
W
M
_
IN
T
n
T
HE
RM
T
R
IP
VSS
VT
R
n
F
PR
ST
/G
P3
0
PW
RGD
_
PS
PW
RGD
_
OUT
GP
3
4
GP
6
2
*
GP
6
7
*
GP
6
6
*
GP
6
5
*
GP
6
4
*
VSS
nR
S
M
R
S
T
CL
K
I3
2
GP
6
3
*
GP
3
1
GP12
GP13
GP60 / nLED1 / WDT
GP61 / nLED2/ CLKO
GP15
VTR
GP42 / nIO_PME
GP16
GP17
GP14
GP11
GP10
SLP_SX#
PB_IN#
PS_ON#
PB_OUT#
GP57 / nDTR2
GP56/ nCTS2
GP55/nRTS2/RESGEN
GP54 / nDSR2
GP53 / TXD2 (IRTX2)
GP52 / RXD2 (IRRX2)
GP51 / nDCD2
VSS
VTR
GP50 / nRI2
nDTR1 / SYSOPT1
nCTS1
nRTS1 / SYSOPT0
nDSR1
TXD1 /SIOXNOROUT
RXD1
HVTR
VTR
V
C
C
VCC
V
C
C
Note:
SYSOPT1 Pin 68
SYSOPT0 Pin 70 and
RESGEN Pin 78 are only sampled during power on configuration
VBAT
HVTR
VTR
VCC
VCC
VCC
V
T
R
V
T
R
2014 Microchip Technology Inc.
DS00001872A-page 7
SCH3112/SCH3114/SCH3116
2.1
SCH311X Pin Layout Summary
TABLE 2-1:
SCH3112 SUMMARY - 2 SERIAL PORTS
PIN#
NAME
PIN#
NAME
PIN#
NAME
PIN#
NAME
1
+12V_IN
33
nPCIRST3 /
GP47
65
RXD1
97
GP31
2
+5V_IN
34
AVSS
66
TXD1/
SIO XNOR_OUT
98
GP63*
3
GP40 /
DRVDEN0
35
VBAT
67
nDSR1
99
CLKI32
4
VTR
36
GP27/nIO_SMI/P17
68
nRTS1/SYSOPT0
100
nRSMRST
5
nMTR0
37
KDAT/GP21
69
nCTS1
101
VSS
6
nDSKCHG
38
KCLK/GP22
70
nDTR1/SYSOPT1
102
GP64*
7
nDS0
39
MDAT/GP32
71
GP50 / nRI2
103
GP65*
8
VSS
40
MCLK/GP33
72
VTR
104
GP66*
9
nDIR
41
GP36/nKBDRST
73
VSS
105
GP67*
10
nSTEP
42
GP37/A20M
74
GP51 / nDCD2
106
GP62*
11
nWDATA
43
VSS
75
GP52 /
RXD2(IRRX2)
107
GP34
12
nWGATE
44
VTR
76
GP53 /
TXD2(IRTX2)
108
PWRGD_OUT
13
nHDSEL
45
nINIT / nDIR
77
GP54 / nDSR2
109
PWRGD_PS
14
nINDEX
46
nSLCTIN / nSTEP
78
GP55 / nRTS2 /
RESGEN
110
nFPRST / GP30
15
nTRK0
47
PD0 / nINDEX
79
GP56 / nCTS2
111
VTR
16
nWRTPRT
48
PD1 / nTRK0
80
GP 57 / nDTR2
112
VSS
17
nRDATA
49
PD2 / nWRTPRT
81
PB_OUT#
113
nTHERMTRIP
18
CLOCKI
50
PD3 / nRDATA
82
PS_ON#
114
nHWM_INT
19
LAD0
51
PD4 / nDSKCHG
83
PB_IN#
115
PWM3
20
LAD1
52
PD5
84
SLP_SX# 116
PWM2
21
LAD2
53
PD6 / nMTR0
85
GP10
117
PWM1
22
LAD3
54
PD7
86
GP11
118
FANTACH3
23
LFRAME#
55
VSS 87
GP14
119
FANTACH2
24
LDRQ#
56
SLCT / nWGATE
88
GP17
120
FANTACH1
25
PCI_RESET#
57
PE / nWDATA
89
GP16
121
HVSS
26
PCI_CLK
58
BUSY / nMTR1
90
GP42/nIO_PME_
122
HVTR
27
SER_IRQ
59
nACK / nDS1
91
VTR
123
REMOTE2-
28
VSS
60
nERROR / nHDSEL 92
GP15
124
REMOTE2+
29
VCC
61
nALF / DRVDEN0
93
GP61/nLED2/CLKO 125
REMOTE1-
30
nIDE_RSTDRV /
GP44
62
nSTROBE / nDS0
94
GP60/nLED1/WDT
126
REMOTE1+
31
nPCIRST1 /
GP45
63
nRI1
95
GP13
127
VCCP_IN
32
nPCIRST2 /
GP46
64
nDCD1
96
GP12 128
+2.5V_IN
SCH3112/SCH3114/SCH3116
DS00001872A-page 8
2014 Microchip Technology Inc.
FIGURE 2-2:
SCH3114 PIN DIAGRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
SCH3114
128 PIN VTQFP
nPCI
RST 3
/ GP
4
7
A
VSS
VBAT
G
P
2
7
/ n
IO
_
S
M
I /
P
1
7
K
DAT /
GP
2
1
K
C
L
K
/ G
P
2
2
M
DAT /
GP
3
2
MC
L
K
/ G
P
3
3
GP3
6
/
n
KB
DRST
G
P
37 /
A
20M
VSS
VTR
nI
NI
T /
nDI
R
nSCLTI
N /
nSTEP
PD
0
/
n
IND
E
X
PD1
/
nTRK0
PD2 /
nW
RTPRT
PD
3
/
nRD
A
TA
P
D
4
/
nD
SKCH
G
PD5
PD6 /
nM
TR0
PD7
VSS
SLC
T
/
nW
G
A
TE
P
E
/
nW
D
A
TA
BU
SY /
nM
TR1
nA
CK /
nDS1
nER
R
OR
/
nH
DSEL
nALF /
DRV
DEN0
nSTRO
B
E /
nDS0
nR
I1
n
D
CD1
+12V_IN
+5V_IN
GP40 /DRVDEN0
VTR
nMTR0
nDSKCHG
nDS0
VSS
nDIR
nSTEP
nWDATA
nWGATE
nHDSEL
nINDEX
nTRK0
nWRTPRT
nRDATA
CLOCKI
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ#
PCI_RESET#
PCI_CLK
SER_IRQ
VSS
VCC
nIDE_RSTDRV/GP44
nPCRST1 / GP45
nPCIRST2 / GP46
+
2
.5
V
_
IN
VC
CP_I
N
RE
MO
TE1
+
RE
MO
TE1
-
RE
MO
TE2
+
RE
MO
TE2
-
HV
TR
HV
SS
FAN
T
ACH
1
FAN
T
ACH
2
FAN
T
ACH
3
PW
M
1
PW
M
2
PW
M
3
nHW
M
_I
NT
nTHE
R
M
T
R
IP
VS
S
VTR
nFPR
S
T/
GP30
PW
R
G
D_P
S
PW
R
G
D_O
U
T
G
P
34 /
nD
T
R
4
G
P
62*
/
n
C
TS4
G
P
67*
/
n
R
TS4
G
P
66*
/
n
D
SR
4
G
P
65*
/
T
X
D
4
G
P
6
4
* /
RXD4
VS
S
nRS
M
R
S
T
CLK
I3
2
G
P
63*
/
n
D
C
D
4
G
P
31 /
nR
I4
GP12 / nDCD3
GP13 / nRI3
GP60 / nLED1 / WDT
GP61 / nLED2/ CLKO
GP15 / nDTR3
VTR
GP42 / nIO_PME
GP16 / nCTS3
GP17 / nRTS3
GP14 / nDSR3
GP11 / TXD3
GP10 / RXD3
SLP_SX#
PB_IN#
PS_ON#
PB_OUT#
GP57 / nDTR2
GP56/ nCTS2
GP55/nRTS2/RESGEN
GP54 / nDSR2
GP53 / TXD2 (IRTX2)
GP52 / RXD2 (IRRX2)
GP51 / nDCD2
VSS
VTR
GP50 / nRI2
nDTR1 / SYSOPT1
nCTS1
nRTS1 / SYSOPT0
nDSR1
TXD1 /SIOXNOROUT
RXD1
HVTR
V
C
C
VCC
V
C
C
Note:
SYSOPT1 Pin 68
SYSOPT0 Pin 70 and
RESGEN Pin 78 are only sampled during power on cinfiguration
VBAT
HVTR
VTR
VCC
VCC
VCC
V
T
R
V
T
R
2014 Microchip Technology Inc.
DS00001872A-page 9
SCH3112/SCH3114/SCH3116
TABLE 2-2:
SCH3114 SUMMARY - 4 SERIAL PORTS
PIN#
NAME
PIN#
NAME
PIN#
NAME
PIN#
NAME
1
+12V_IN
33
nPCIRST3 /
GP47
65
RXD1
97
GP31 / nRI4
2
+5V_IN
34
AVSS
66
TXD1/
SIO XNOR_OUT
98
GP63* / nDCD4
3
GP40/DRVDEN0
35
VBAT
67
nDSR1
99
CLKI32
4
VTR
36
GP27/nIO_SMI/P17
68
nRTS1/SYSOPT0
100
nRSMRST
5
nMTR0
37
KDAT/GP21
69
nCTS1
101
VSS
6
nDSKCHG
38
KCLK/GP22
70
nDTR1/SYSOPT1
102
GP64* / RXD4
7
nDS0
39
MDAT/GP32
71
GP50 / nRI2
103
GP65* / TXD4
8
VSS
40
MCLK/GP33
72
VTR
104
GP66* / nDSR4
9
nDIR
41
GP36/nKBDRST
73
VSS
105
GP67* / nRTS4
10
nSTEP
42
GP37/A20M
74
GP51 / nDCD2
106
GP62* / nCTS4
11
nWDATA
43
VSS
75
GP52 /
RXD2(IRRX2)
107
GP34 / nDTR4
12
nWGATE
44
VTR
76
GP53 /
TXD2(IRTX2)
108
PWRGD_OUT
13
nHDSEL
45
nINIT / nDIR
77
GP54 / nDSR2
109
PWRGD_PS
14
nINDEX
46
nSLCTIN / nSTEP
78
GP55 / nRTS2 /
RESGEN
110
nFPRST / GP30
15
nTRK0
47
PD0 / nINDEX
79
GP56 / nCTS2
111
VTR
16
nWRTPRT
48
PD1 / nTRK0
80
GP 57 / nDTR2
112
VSS
17
nRDATA
49
PD2 / nWRTPRT
81
PB_OUT#
113
nTHERMTRIP
18
CLOCKI
50
PD3 / nRDATA
82
PS_ON#
114
nHWM_INT
19
LAD0
51
PD4 / nDSKCHG
83
PB_IN#
115
PWM3
20
LAD1
52
PD5
84
SLP_SX# 116
PWM2
21
LAD2
53
PD6 / nMTR0
85
GP10/RXD3
117
PWM1
22
LAD3
54
PD7
86
GP11 / TXD3
118
FANTACH3
23
LFRAME#
55
VSS
87
GP14 / nDSR3
119
FANTACH2
24
LDRQ#
56
SLCT / nWGATE
88
GP17 / nRTS3
120
FANTACH1
25
PCI_RESET#
57
PE / nWDATA
89
GP16 / nCTS3
121
HVSS
26
PCI_CLK
58
BUSY / nMTR1
90
GP42/nIO_PME_
122
HVTR
27
SER_IRQ
59
nACK / nDS1
91
VTR
123
REMOTE2-
28
VSS
60
nERROR / nHDSEL 92
GP15 / nDTR3
124
REMOTE2+
29
VCC
61
nALF / DRVDEN0
93
GP61/nLED2/CLKO 125
REMOTE1-
30
nIDE_RSTDRV /
GP44
62
nSTROBE / nDS0
94
GP60/nLED1/WDT
126
REMOTE1+
31
nPCIRST1 /
GP45
63
nRI1
95
GP13 / nRI3
127
VCCP_IN
32
nPCIRST2 /
GP46
64
nDCD1
96
GP12 / nDCD3
128
+2.5V_IN
SCH3112/SCH3114/SCH3116
DS00001872A-page 10
2014 Microchip Technology Inc.
FIGURE 2-3:
SCH116 PIN DIAGRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
SCH3116
128 PIN VTQFP
GP
4
7
/n
SC
OU
T
6
AV
SS
VBA
T
G
P
2
7
/
n
IO
_
S
M
I
/
P
1
7
K
DAT
/
GP
2
1
KC
L
K
/
G
P
2
2
M
DAT
/
GP
3
2
MC
L
K
/ G
P
3
3
GP3
6
/
n
K
B
DRS
T
G
P
37 /
A
20
M
VS
S
VT
R
nI
NI
T /
n
D
IR
nS
CLTI
N /
n
S
TE
P
PD
0 /
n
IND
EX
P
D
1
/
n
T
RK0
PD
2
/
nW
R
T
P
R
T
PD3
/
nR
DA
TA
P
D
4
/
n
D
SKCH
G
PD5
PD6 /
nM
TR0
PD7
VS
S
SL
CT /
n
W
GA
TE
PE /
n
W
DA
TA
B
U
SY /
nM
TR1
nA
CK
/
nDS1
n
E
R
R
O
R
/
n
H
D
S
E
L
nAL
F
/
DRV
DEN0
nST
R
O
B
E
/
nDS0
nRI
1
n
D
CD1
+12V_IN
+5V_IN
GP40 /DRVDEN0
VTR
nMTR0
nDSKCHG
nDS0
VSS
nDIR
nSTEP
nWDATA
nWGATE
nHDSEL
nINDEX
nTRK0
nWRTPRT
nRDATA
CLOCKI
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ#
PCI_RESET#
PCI_CLK
SER_IRQ
VSS
VCC
GP44 / TXD6
GP45 / RXD6
GP46 / nSCIN6
+2
.5
V
_
IN
V
CCP
_
IN
RE
MO
TE1+
RE
MO
TE1-
RE
MO
TE2+
RE
MO
TE2-
HV
T
R
H
VSS
FAN
T
ACH
1
FAN
T
ACH
2
FAN
T
ACH
3
PW
M
1
PW
M
2
PW
M
3
nHW
M
_
INT
nT
HE
RM
TR
IP
VS
S
VTR
nF
PR
ST
/G
P
3
0
P
W
RG
D_
PS
P
W
RG
D_
OU
T
G
P
3
4
/
n
D
T
R
4
GP
6
2
* /
n
C
T
S
4
GP
6
7
* /
n
R
T
S
4
GP
6
6
* /
n
D
SR
4
GP
6
5
* /
T
X
D4
G
P
64
* /
RXD4
VS
S
nRS
M
R
S
T
CLK
I3
2
GP
6
3
* /
n
D
CD
4
G
P
3
1
/
n
R
I4
GP12 / nDCD3
GP13 / nRI3
GP60 / nLED1 / WDT
GP61 / nLED2/ CLKO
GP15 / nDTR3
VTR
GP42 / nIO_PME
GP16 / nCTS3
GP17 / nRTS3
GP14 / nDSR3
GP11 / TXD3
GP10 / RXD3
nSCIN5
nSCOUT5
TXD5
RXD5
GP57 / nDTR2
GP56/ nCTS2
GP55/nRTS2/RESGEN
GP54 / nDSR2
GP53 / TXD2 (IRTX2)
GP52 / RXD2 (IRRX2)
GP51 / nDCD2
VSS
VTR
GP50 / nRI2
nDTR1 / SYSOPT1
nCTS1
nRTS1 / SYSOPT0
nDSR1
TXD1 /SIOXNOROUT
RXD1
HVTR
V
C
C
VCC
V
C
C
Note:
SYSOPT1 Pin 68
SYSOPT0 Pin 70 and
RESGEN Pin 78 are only sampled during power on configuration
VBAT
HVTR
VTR
VCC
VCC
VCC
V
T
R
V
T
R