2017 Microchip Technology Inc.
DS20005746A-page 1
MD1812
Features
• 6 ns Rise and Fall Time
• 2A Peak Output Source and Sink Currents
• 1.8V to 5V Input CMOS Compatible
• Smart Logic Threshold
• Low-jitter Design
• Four Matched Channels
• Drives Two P-channel and Two N-channel
MOSFETs
• Outputs can Swing below Ground
• Built-in Level Translator for Negative Gate Bias
• User-defined damping for Return-to-zero
Application
• Low-inductance Quad-flat No-lead Package
• High-performance Thermally Enhanced Package
Applications
• Ultrasound PN Code Transmitter
• Medical Ultrasound Imaging
• Piezoelectric Transducer Drivers
• Non-destructive Testing
• High-speed Level Translator
• High-voltage Bipolar Pulser
General Description
The MD1812 is a high-speed quad-MOSFET driver
designed to drive two P-channel and two N-channel
high-voltage MOSFETs for medical ultrasound
applications and other applications requiring a
high-output current for a capacitive load. The input
stage of the MD1812 is a high-speed level translator
that is able to operate from logic input signals of 1.8V
to 5V amplitude. An adaptive threshold circuit is used
to set the level translator switch threshold to the
average of the input logic 0 and logic 1 levels. The
level translator uses a proprietary circuit which
provides DC coupling together with high-speed
operation.
The output stage of the MD1812 has separate power
connections, enabling the output signal L and H levels
to be chosen independently from the supply voltages
used for the majority of the circuit. As an example, the
input logic levels may be 0V and 1.8V, the control logic
may be powered by +5V and –5V, and the
output L and H levels may be varied anywhere over the
range of –5V to +5V. The output stage is capable of
peak currents of up to ±2A, depending on the supply
voltages used and load capacitance present.
The OE pin serves a dual purpose. First, its logic
H level is used to compute the threshold voltage level
for the channel input level translators. Second, when
OE is low, the outputs are disabled, with the A and C
outputs high and the B and D outputs low. This assists
in properly pre-charging the AC coupling capacitors
that may be used in series in the gate drive circuit of an
external PMOS and NMOS transistor pair. A built-in
level shifter provides PMOS gate negative bias drive.
This enables the user-defined damping control to
generate return-to-zero bipolar output pulses.
Package Type
16-lead QFN
(Top view)
See
Table 2-1
for pin information.
1
High-Speed Quad-MOSFET Driver
Logic
Inputs
OUTA
OUTB
OUTC
OUTD
+10V
0.22 µF
V
DD
V
H
+10V
0.47µF
V
SS
V
L
V
NEG
GND
INA
INB
INC
IND
OE
-8V
0.47µF
LT
MD1812
OUTG
MD1812
DS20005746A-page 2
2017 Microchip Technology Inc.
Functional Block Diagram
2017 Microchip Technology Inc.
DS20005746A-page 3
MD1812
Typical Application Circuit
OUTA
OUTB
OUTC
OUTD
VDD
VH
VSS
VL
VNEG
GND
-8V
LT
2k
Ω
OUTG
MD1812
TC2320
TC6320
1.0μF
1.0μF
10nF
10nF
10nF
0.47μF
0.47μF
INA
INB
INC
IND
3.3V CMOS
Logic Inputs
OE
0.22μF
+10V
+10V
+100V
-100V
MD1812
DS20005746A-page 4
2017 Microchip Technology Inc.
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
Supply Voltage, V
DD
–V
SS
...................................................................................................................... –0.5V to +13.5V
Output High Supply Voltage, V
H
................................................................................................... V
L
–0.5V to V
DD
+0.5V
Output Low Supply Voltage, V
L
.................................................................................................... V
SS
–0.5V to V
H
+0.5V
Low-side Supply Voltage, V
SS
.................................................................................................................... –7V to +0.5V
Supply Voltage, V
DD
–V
NEG
...................................................................................................................... –0.5V to +20V
Negative Supply Voltage, V
NEG
–V
SS
......................................................................................... V
SS
–10V to V
SS
+0.5V
Logic Input Levels ....................................................................................................................... V
SS
–0.5V to GND +7V
Operating Junction Temperature, T
J
.................................................................................................... –25°C to +125°C
Storage Temperature, T
S
...................................................................................................................... –65°C to +150°C
Power Dissipation .................................................................................................................................................. 2.2W
ESD Rating (
Note 1
) ................................................................................................................................ ESD Sensitive
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions above those
indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Note 1: Device is ESD sensitive. Handling precautions are recommended.
DC ELECTRICAL CHARACTERISTICS
Electrical Specifications: V
H
= V
DD
= 12V, V
L
= V
SS
= GND = 0V, V
NEG
= –6V, V
OE
= 3.3V and T
J
= 25°C
Parameter
Sym.
Min.
Typ.
Max.
Unit
Conditions
Supply Voltage
V
DD
–V
SS
4.5
—
13
V
2.5V ≤ V
DD
≤ 13V
Supply Voltage
V
DD
–V
NEG
—
—
18
V
Low-side Supply Voltage
V
SS
–5.5
—
0
V
Output High Supply Voltage
V
H
V
SS
+2
—
V
DD
V
Output Low Supply Voltage
V
L
V
SS
—
V
DD
–
2
V
Negative Supply Voltage
V
NEG
–9
—
V
SS
–2
V
May be connected to V
SS
if OUTG is not used
V
DD
Quiescent Current
I
DDQ
—
1.5
—
mA
No input transitions,
OE = 1
V
H
Quiescent Current
I
HQ
—
—
10
µA
V
NEG
Quiescent Current
I
NEGQ
—
150
—
µA
V
DD
Average Current
I
DD
—
7
—
mA One channel on at 5
MHz,
no load
V
H
Average Current
I
H
—
22
—
mA
V
NEG
Average Current
I
NEG
—
1.5
—
mA
Input Logic Voltage High
V
IH
V
OE
–0.3
—
5
V
For logic inputs INA, INB,
INC and IND
Input Logic Voltage Low
V
IL
0
—
0.3
V
Input Logic Current High
I
IH
—
—
1
µA
Input Logic Current Low
I
IL
—
—
1
µA
OE Input Logic Voltage High
V
IH
1.7
—
5
V
For logic input OE
OE Input Logic Voltage Low
V
IL
0
—
0.3
V
OE Input Resistance
R
IN
10
20
30
kΩ
Logic Input Capacitance
C
IN
—
5
10
pF
Output Sink Resistance
OUTA-D
R
SINK
—
—
12.5
Ω
I
SINK
= 50 mA
OUTG
—
—
200
I
SINK
= 5 mA
Output Source
Resistance
OUTA-D
R
SOURCE
—
—
12.5
Ω
I
SOURCE
= 50 mA
OUTG
—
—
200
I
SOURCE
= 5 mA
2017 Microchip Technology Inc.
DS20005746A-page 5
MD1812
TEMPERATURE SPECIFICATIONS
Parameter
Sym.
Min.
Typ.
Max.
Unit
Conditions
TEMPERATURE RANGE
Operating Junction Temperature
T
J
–25
—
125
°C
Storage Temperature
T
S
–65
—
150
°C
PACKAGE THERMAL RESISTANCE
16-lead QFN
JA
—
25
—
°C/W
Note 1
Note 1: 1 oz. 4-layer 3” x 4” PCB
Peak Output Sink Current
I
SINK
—
2
—
A
Peak Output Source Current
I
SOURCE
—
2
—
A
AC ELECTRICAL CHARACTERISTICS
Electrical Specifications: V
H
= V
DD
= 12V, V
L
= V
SS
= GND = 0V, V
NEG
= –6V, V
OE
= 3.3V and T
A
= 25°C
Parameter
Sym.
Min.
Typ.
Max.
Unit
Conditions
Input or OE Rise and Fall Time
t
irf
—
—
10
ns
Logic input edge speed
requirement
Propagation Delay INC to OUTG
t
PCG
—
40
—
ns
10 MΩ load to GND
Propagation Delay when Output is
from Low to High for OUTA-D
t
PLH
—
7
—
ns
C
LOAD
= 1000 pF, input signal
rise/fall time of 2 ns
Propagation Delay when Output is
from High to Low for OUTA-D
t
PHL
—
7
—
ns
Output Rise Time
t
r
—
6
—
ns
Output Fall Time
t
f
—
6
—
ns
Rise and Fall Time Matching
l t
r
–t
f
l
—
1
—
ns
For each channel
Propagation Low-to-high and
High-to-low Matching
l t
PLH
–t
PHL
l
—
1
—
ns
Propagation Delay Matching
∆t
dm
—
±2
—
ns
Device-to-device delay match
Output Enable Time
t
OE_ON
—
200
—
ns
t
OE_OFF
—
9
—
ns
DC ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: V
H
= V
DD
= 12V, V
L
= V
SS
= GND = 0V, V
NEG
= –6V, V
OE
= 3.3V and T
J
= 25°C
Parameter
Sym.
Min.
Typ.
Max.
Unit
Conditions
INPUT
t
PLH
10%
90%
50%
50%
OUTPUT
t
PHL
t
r
90%
10%
t
f
MD1812
DS20005746A-page 6
2017 Microchip Technology Inc.
Timing Diagram
TABLE 1-1:
TRUTH FUNCTION TABLE
Logic Inputs
Outputs
OE
INA
INB
OUTA
OUTB
H
L
L
V
H
V
H
H
L
H
V
H
V
L
H
H
L
V
L
V
H
H
H
H
V
L
V
L
L
X
X
V
H
V
L
OE
INC
IND
OUTC
OUTG
OUTD
H
L
L
V
H
V
SS
V
H
H
L
H
V
H
V
SS
V
L
H
H
L
V
L
V
NEG
V
H
H
H
H
V
L
V
NEG
V
L
L
X
X
V
H
V
SS
V
L
2017 Microchip Technology Inc.
DS20005746A-page 7
MD1812
2.0
PIN DESCRIPTION
The details on the pins of MD1812 are listed on
Table 2-1
. See
Package Type
for the location of pins.
TABLE 2-1:
PIN FUNCTION TABLE
Pin Number
Pin Name
Description
1
INB
Logic input. Controls OUTB when OE is high.
2
VL
Supply voltage for N-channel output stage
3
GND
Device ground
4
VNEG
Supply voltage for the auxiliary gate drive (
Note 1
)
5
INC
Logic input. Controls OUTC when OE is high.
6
IND
Logic input. Controls OUTD when OE is high.
7
VSS
Supply voltage for low-side analog, level shifter and gate drive circuit
8
OUTD
Output driver
9
OUTC
Output driver
10
OUTG
Auxiliary output driver
11
VH
Supply voltage for P-channel output stage
12
OUTB
Output driver
13
OUTA
Output driver
14
VDD
Supply voltage for high-side analog, level shifter and gate drive circuit
15
INA
Logic input. Controls OUTA when OE is high.
16
OE
Output enable logic input
Note 1: Thermal pad and pin 4, VNEG must be connected externally.
MD1812
DS20005746A-page 8
2017 Microchip Technology Inc.
3.0
APPLICATION INFORMATION
For proper operation of the MD1812, low-inductance
bypass capacitors should be used on the various
supply pins. The GND input pin should be connected to
the logic ground. The INA, INB, INC, IND and OE pins
should be connected to a logic source with a swing of
GND to V
CC
, where V
CC
is 1.8V to 5V. When the input
logic(s) is high, the output(s) will swing to V
L
, and when
the input(s) logic is low, the output(s) will swing to V
H
.
All inputs must be kept low until the device is powered
up. Good trace practices should be followed
corresponding to the desired operating speed. The
internal circuitry of the MD1812 is capable of operating
up to 100 MHz, with the primary speed limitation being
the loading effect of the load capacitance. Because of
this speed and the high transient currents due to the
capacitive loads, the bypass capacitors should be as
close to the chip pins as possible. Unless the load
specifically requires bipolar drive, the V
SS
and V
L
pins
should have a low-inductance bypass capacitor to
GND and supply power connections. If these voltages
are not zero, they need bypass capacitors in a manner
similar to the positive power supplies. The power
connection V
DD
should have a ceramic bypass
capacitor to the ground plane with short leads and
decoupling components to prevent resonance in the
power leads.
Output drivers OUTA and OUTC drive the gate of an
external P-channel MOSFET, while output drivers
OUTB and OUTD drive the gate of an external
N-channel MOSFET, and they all swing from V
H
to V
L
.
The auxiliary output drive, OUTG, swings from V
SS
to
V
NEG
and drives the gate of an external P-channel
MOSFET through a 2 kΩ series resistor.
The voltages of V
H
and V
L
decide the output logic
levels. These two pins can draw fast transient currents
of up to 2A, so they should be provided with a suitable
bypass capacitor located next to the chip pins.
A ceramic capacitor of up to 1 µF may be appropriate,
with a series ferrite bead to prevent resonance in the
power supply lead going to the capacitor. Pay particular
attention to minimizing trace lengths, current loop area
and using sufficient trace width to reduce inductance.
Surface-mount components are highly recommended.
Since the output impedance of this driver is very low, in
some cases, it may be desirable to add a small series
resistor in series with the output signal to obtain better
waveform transitions at the load terminals. This will
reduce the output voltage slew rate at the terminals of
a capacitive load.
The OE pin sets the threshold level of logic for inputs
(V
OE
+ V
GND
)/2. When OE is low, OUTA and OUTC are
at V
H
, while OUTB and OUTD are at V
L
. Auxiliary
output OUTG is at V
SS
, regardless of the inputs INA
and INB.
Ensure that parasitic couplings are minimized from the
driver output to the input signal terminals. The parasitic
feedback may cause oscillations or spurious waveform
shapes on the edges of signal transitions. Since the
input operates with signals down to 1.8V, even small
coupled voltages may cause problems. The use of a
solid ground plane and good power and signal layout
practices will prevent this problem. Make sure that the
circulating ground return current from a capacitive load
will not react with common inductance and cause noise
voltages in the input logic circuitry. Best timing
performance is obtained for OUTC when the voltage of
V
SS
–V
NEG
= V
H
–V
L
.
2017 Microchip Technology Inc.
DS20005746A-page 9
MD1812
4.0
PACKAGING INFORMATION
4.1
Package Marking Information
Legend: XX...X
Product Code or Customer-specific information
Y
Year code (last digit of calendar year)
YY
Year code (last 2 digits of calendar year)
WW
Week code (week of January 1 is week ‘01’)
NNN
Alphanumeric traceability code
Pb-free JEDEC
®
designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note:
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available characters
for product code or customer-specific information. Package may or not include
the corporate logo.
3
e
3
e
16-lead QFN
Example
XXXXXX
XXXXXX
YYWW
NNN
e3
MD
1812K6
1710
265
e3
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
MD1812
DS20005746A-page 10
2017 Microchip Technology Inc.