2011 Microchip Technology Inc.
DS21697F-page 1
MCP3302/04
Features
• Full Differential Inputs
• 2 Differential or 4 Single-ended inputs (MCP3302)
• 4 Differential or 8 Single-ended Inputs (MCP3304)
• ±1 LSB maximum DNL
• ±1 LSB maximum INL (MCP3302/04-B)
• ±2 LSB maximum INL (MCP3302/04-C)
• Single supply operation: 4.5V to 5.5V
• 100 ksps sampling rate with 5V supply voltage
• 50 nA typical standby current, 1 µA maximum
• 450 µA maximum active current at 5V
• Industrial Temperature Range: -40°C to +85°C
• 14 and 16-pin PDIP, SOIC, and TSSOP packages
• Mixed Signal PICtail™ Demo Board (P/N:
MXSIGDM) compatible
Applications
• Remote Sensors
• Battery-operated Systems
• Transducer Interface
General Description
The MCP3302/04 13-bit A/D converter features full
differential inputs and low-power consumption in a
small package that is ideal for battery-powered
systems and remote data acquisition applications.
The MCP3302 is user-programmable to provide two
differential input pairs or four single-ended inputs.
The MCP3304 is also user-programmable to configure
into four differential input pairs or eight single-ended
inputs.
Incorporating a successive approximation architecture
with on-board sample and hold circuitry, these 13-bit
A/D converters are specified to have ±1 LSB
Differential Nonlinearity (DNL); ±1 LSB Integral
Nonlinearity (INL) for B-grade and ±2 LSB for C-grade
devices. The industry-standard SPI serial interface
enables 13-bit A/D converter capability to be added to
any PIC
®
microcontroller.
The MCP3302/04 devices feature low current design
that permits operation with typical standby and active
currents of only 50 nA and 300 µA, respectively. The
device is capable of conversion rates of up to 100 ksps
with tested specifications over a 4.5V to 5.5V supply
range. The reference voltage can be varied from
400 mV to 5V, yielding input-referred resolution
between 98 µV and 1.22 mV.
The MCP3302 is available in 14-pin PDIP, 150 mil
SOIC and TSSOP packages. The MCP3304 is
available in 16-pin PDIP and 150 mil SOIC packages.
The full differential inputs of these devices enable a
wide variety of signals to be used in applications such
as remote data acquisition, portable instrumentation,
and battery-operated applications.
Package Types
V
DD
CLK
D
OUT
MC
P3
302
1
2
3
4
14
13
12
11
10
9
8
5
6
7
V
REF
D
IN
CH0
CH1
CH2
CH3
CS/SHDN
DGND
AGND
NC
V
DD
CLK
D
OUT
MC
P3
30
4
1
2
3
4
16
15
14
13
12
11
10
9
5
6
7
8
V
REF
D
IN
CS/SHDN
DGND
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
NC
AGND
PDIP, SOIC, TSSOP
PDIP, SOIC
13-Bit Differential Input, Low Power A/D Converter
with SPI Serial Interface
MCP3302/04
DS21697F-page 2
2011 Microchip Technology Inc.
Functional Block Diagram
Comparator
13-Bit SAR
CDAC
Control Logic
CS/SHDN
V
REF
AGND
V
DD
CLK
D
OUT
Shift
Register
CH0
Channel
Mux
Input
CH1
CH7*
* Channels 5-7 available on
MCP3304 Only
D
IN
+
-
& Hold
Circuits
Sample
DGND
2011 Microchip Technology Inc.
DS21697F-page 3
MCP3302/04
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
V
DD
...................................................................................7.0V
All inputs and outputs w.r.t. V
SS
............... -0.3V to V
DD
+0.3V
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-65°C to +125°C
Maximum Junction Temperature .................................. 150°C
ESD protection on all pins (HBM)
4 kV
† Notice: Stresses above those listed under “Maximum
ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification
is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise noted, all parameters apply at V
DD
= 5V, V
SS
= 0V, and V
REF
= 5V. Full differential
input configuration (
Figure 1-5
) with fixed common mode voltage of 2.5V. All parameters apply over temperature with
T
A
= -40°C to +85°C (
Note 7
). Conversion speed (F
SAMPLE
) is 100 ksps with F
CLK
= 21*F
SAMPLE
Parameter
Symbol
Min
Typ
Max
Units
Conditions
Conversion Rate
Maximum Sampling Frequency
F
SAMPLE
—
—
100
ksps
See F
CLK
specification.
Note 8
Conversion Time
T
CONV
13
CLK
periods
Acquisition Time
T
ACQ
1.5
CLK
periods
DC Accuracy
Resolution
12 data bits + sign
bits
Integral Nonlinearity
INL
—
±0.5
±1
LSB
MCP3302/04-B
—
±1
±2
LSB
MCP3302/04-C
Differential Nonlinearity
DNL
—
±0.5
±1
LSB
Monotonic over temperature
Positive Gain Error
-3
-0.75
+2
LSB
Negative Gain Error
-3
-0.5
+2
LSB
Offset Error
-3
+3
+6
LSB
Dynamic Performance
Total Harmonic Distortion
THD
—
-91
—
dB
Note 3
Signal-to-Noise and Distortion
SINAD
—
78
—
dB
Note 3
Spurious Free Dynamic Range
SFDR
—
92
—
dB
Note 3
Common Mode Rejection
CMRR
—
79
—
dB
Note 6
Channel to Channel Crosstalk
CT
—
> -110
—
dB
Note 6
Power Supply Rejection
PSR
—
74
—
dB
Note 4
Reference Input
Voltage Range
0.4
—
V
DD
V
Note 2
Current Drain
—
100
150
µA
—
0.001
3
µA
CS = V
DD
= 5V
Note 1: This specification is established by characterization and not 100% tested.
2: See characterization graphs that relate converter performance to V
REF
level.
3: V
IN
= 0.1V to 4.9V @ 1 kHz.
4: V
DD
=5V
DC ±500 mV
P-P
@ 1 kHz, see test circuit
Figure 1-4
.
5: Maximum clock frequency specification must be met.
6: V
REF
= 400 mV, V
IN
= 0.1V to 4.9V @ 1 kHz.
7: TSSOP devices are only specified at 25°C and +85°C.
8: For slow sample rates, see
Section 5.2 “Driving the Analog Input”
for limitations on clock frequency.
9: 4.5V - 5.5V is the supply voltage range for specified performance.
MCP3302/04
DS21697F-page 4
2011 Microchip Technology Inc.
Analog Inputs
Full Scale Input Span
CH0 - CH7
-V
REF
—
V
REF
V
Absolute Input Voltage
CH0 - CH7
-0.3
—
V
DD
+ 0.3
V
Leakage Current
—
0.001
±1
µA
Switch Resistance
R
S
—
1
—
k
Ω
See
Figure 5-3
Sample Capacitor
C
SAMPLE
—
25
—
pF
See
Figure 5-3
Digital Input/Output
Data Coding Format
Binary Two’s Complement
High Level Input Voltage
V
IH
0.7 V
DD
—
—
V
Low Level Input Voltage
V
IL
—
—
0.3 V
DD
V
High Level Output Voltage
V
OH
4.1
—
—
V
I
OH
= -1 mA, V
DD
= 4.5V
Low Level Output Voltage
V
OL
—
—
0.4
V
I
OL
= 1 mA, V
DD
= 4.5V
Input Leakage Current
I
LI
-10
—
10
µA
V
IN
= V
SS
or V
DD
Output Leakage Current
I
LO
-10
—
10
µA
V
OUT
= V
SS
or V
DD
Pin Capacitance
C
IN
, C
OUT
—
—
10
pF
T
A
= +25°C, F = 1 MHz,
Note 1
Timing Specifications:
Clock Frequency
(Note 8)
F
CLK
0.105
—
2.1
MHz
V
DD
= 5V, F
SAMPLE
= 100 ksps
Clock High Time
T
HI
210
—
—
ns
Note 5
Clock Low Time
T
LO
210
—
—
ns
Note 5
CS Fall To First Rising CLK Edge
T
SUCS
100
—
—
ns
Data In Setup time
T
SU
50
—
—
ns
Data In Hold Time
T
HD
50
—
—
ns
CLK Fall To Output Data Valid
T
DO
—
—
125
ns
V
DD
= 5V, see
Figure 1-2
—
—
200
ns
V
DD
= 2.7V, see
Figure 1-2
CLK Fall To Output Enable
T
EN
—
—
125
ns
V
DD
= 5V, see
Figure 1-2
—
—
200
ns
V
DD
= 2.7V, see
Figure 1-2
CS Rise To Output Disable
T
DIS
—
—
100
ns
See test circuits,
Figure 1-2
Note 1
CS Disable Time
T
CSH
475
—
—
ns
D
OUT
Rise Time
T
R
—
—
100
ns
See test circuits,
Figure 1-2
Note 1
D
OUT
Fall Time
T
F
—
—
100
ns
See test circuits,
Figure 1-2
Note 1
ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise noted, all parameters apply at V
DD
= 5V, V
SS
= 0V, and V
REF
= 5V. Full differential
input configuration (
Figure 1-5
) with fixed common mode voltage of 2.5V. All parameters apply over temperature with
T
A
= -40°C to +85°C (
Note 7
). Conversion speed (F
SAMPLE
) is 100 ksps with F
CLK
= 21*F
SAMPLE
Parameter
Symbol
Min
Typ
Max
Units
Conditions
Note 1: This specification is established by characterization and not 100% tested.
2: See characterization graphs that relate converter performance to V
REF
level.
3: V
IN
= 0.1V to 4.9V @ 1 kHz.
4: V
DD
=5V
DC ±500 mV
P-P
@ 1 kHz, see test circuit
Figure 1-4
.
5: Maximum clock frequency specification must be met.
6: V
REF
= 400 mV, V
IN
= 0.1V to 4.9V @ 1 kHz.
7: TSSOP devices are only specified at 25°C and +85°C.
8: For slow sample rates, see
Section 5.2 “Driving the Analog Input”
for limitations on clock frequency.
9: 4.5V - 5.5V is the supply voltage range for specified performance.
2011 Microchip Technology Inc.
DS21697F-page 5
MCP3302/04
TEMPERATURE CHARACTERISTICS
FIGURE 1-1:
Timing Parameters.
Power Requirements:
Operating Voltage
V
DD
4.5
—
5.5
V
Note 9
Operating Current
I
DD
—
300
450
µA
V
DD
, V
REF
= 5V, D
OUT
unloaded
—
200
—
µA
V
DD
, V
REF
= 2.7V, D
OUT
unloaded
Standby Current
I
DDS
—
0.05
1
µA
CS = V
DD
= 5.0V
Electrical Specifications: Unless otherwise indicated, V
DD
= +2.7V to +5.5V, V
SS
= GND.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Temperature Ranges
Specified Temperature Range
T
A
-40
—
+125
°C
Operating Temperature Range
T
A
-40
—
+125
°C
Storage Temperature Range
T
A
-65
—
+150
°C
Thermal Package Resistances
Thermal Resistance, 14L-PDIP
JA
—
70
—
°C/W
Thermal Resistance, 14L-SOIC
JA
—
95.3
—
°C/W
Thermal Resistance, 14L-TSSOP
JA
—
100
—
°C/W
Thermal Resistance, 16L-PDIP
JA
—
70
—
°C/W
Thermal Resistance, 16L-SOIC
JA
—
86.1
—
°C/W
ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise noted, all parameters apply at V
DD
= 5V, V
SS
= 0V, and V
REF
= 5V. Full differential
input configuration (
Figure 1-5
) with fixed common mode voltage of 2.5V. All parameters apply over temperature with
T
A
= -40°C to +85°C (
Note 7
). Conversion speed (F
SAMPLE
) is 100 ksps with F
CLK
= 21*F
SAMPLE
Parameter
Symbol
Min
Typ
Max
Units
Conditions
Note 1: This specification is established by characterization and not 100% tested.
2: See characterization graphs that relate converter performance to V
REF
level.
3: V
IN
= 0.1V to 4.9V @ 1 kHz.
4: V
DD
=5V
DC ±500 mV
P-P
@ 1 kHz, see test circuit
Figure 1-4
.
5: Maximum clock frequency specification must be met.
6: V
REF
= 400 mV, V
IN
= 0.1V to 4.9V @ 1 kHz.
7: TSSOP devices are only specified at 25°C and +85°C.
8: For slow sample rates, see
Section 5.2 “Driving the Analog Input”
for limitations on clock frequency.
9: 4.5V - 5.5V is the supply voltage range for specified performance.
CS
CLK
D
IN
MSB IN
T
SU
T
HD
T
SUCS
T
CSH
T
HI
T
LO
D
OUT
T
EN
T
DO
T
LSB
Sign BIT
T
DIS
Null Bit
T
F
MCP3302/04
DS21697F-page 6
2011 Microchip Technology Inc.
1.1
Test Circuits
FIGURE 1-2:
Load Circuit for T
R
, T
F
,
T
DO
.
FIGURE 1-3:
Load circuit for T
DIS
and
T
EN
.
FIGURE 1-4:
Power Supply Sensitivity
Test Circuit (PSRR).
FIGURE 1-5:
Full Differential Test
Configuration Example.
FIGURE 1-6:
Pseudo Differential Test
Configuration Example.
Test Point
1.4V
D
OUT
3 kΩ
C
L
= 100 pF
MC
P3
30
X
*Waveform 1 is for an output with internal
conditions such that the output is high, unless
disabled by the output control.
†Waveform 2 is for an output with internal
conditions such that the output is low, unless
disabled by the output control.
Test Point
D
OUT
3 kΩ
100 pF
T
DIS
Waveform 2
T
DIS
Waveform 1
T
EN
Waveform
V
DD
V
DD
/2
V
SS
V
IH
T
DIS
CS
D
OUT
Waveform 1*
D
OUT
Waveform 2†
90%
10%
Voltage Waveforms for T
DIS
MC
P3
30X
2.63V
-
+
1 k
5V ±500 mV
P-P
5V
P-P
1 k
20 kΩ
To V
DD
on DUT
1 k
1/2
MCP602
V
DD
= 5V
0.1 µF
IN(+)
IN(-)
MCP330X
5V
P-P
V
REF
= 5V
5V
P-P
V
CM
= 2.5V
1 µF
0.1 µF
V
REF
V
DD
V
SS
0.1µF
IN(+)
IN(-)
MCP330X
V
DD
= 5V
V
CM
= 2.5V
5V
P-P
V
REF
= 2.5V
1µF
0.1µF
V
REF
V
DD
V
SS
2011 Microchip Technology Inc.
DS21697F-page 7
MCP3302/04
2.0
TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, V
DD
= V
REF
= 5V, full differential input configuration, V
SS
= 0V, F
SAMPLE
= 100 ksps,
F
CLK
= 21*F
SAMPLE
, T
A
= +25°C.
.
FIGURE 2-1:
Integral Nonlinearity (INL)
vs. Sample Rate.
FIGURE 2-2:
Integral Nonlinearity (INL)
vs. V
REF.
FIGURE 2-3:
Integral Nonlinearity (INL)
vs. Code (Representative Part).
FIGURE 2-4:
Integral Nonlinearity (INL)
vs. Temperature.
FIGURE 2-5:
Differential Nonlinearity
(DNL) vs. Sample Rate.
FIGURE 2-6:
Differential Nonlinearity
(DNL) vs. V
REF
.
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
0
50
100
150
200
Sample Rate (ksps)
INL
(L
SB)
Positive INL
Negative INL
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
0
1
2
3
4
5
V
REF
(V)
IN
L
(L
SB
)
Positive INL
Negative INL
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
-4096 -3072 -2048 -1024
0
1024
2048
3072
4096
Code
IN
L
(L
SB
)
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
-50
-25
0
25
50
75
100
125
150
Temperature(°C)
IN
L
(L
SB
)
Positive INL
Negative INL
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
0
50
100
150
200
Sample Rate (ksps)
DN
L
(L
SB)
Positive DNL
Negative DNL
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
0
1
2
3
4
5
6
V
REF
(V)
D
N
L(
LSB
)
Positive DNL
Negative DNL
MCP3302/04
DS21697F-page 8
2011 Microchip Technology Inc.
Note: Unless otherwise indicated, V
DD
= V
REF
= 5V, Full differential input configuration, V
SS
= 0V, F
SAMPLE
= 100 ksps,
F
CLK
= 21*F
SAMPLE
, T
A
= +25°C.
FIGURE 2-7:
Differential Nonlinearity
(DNL) vs. Code (Representative Part).
FIGURE 2-8:
Differential Nonlinearity
(DNL) vs. Temperature.
FIGURE 2-9:
Positive Gain Error vs. V
REF
.
FIGURE 2-10:
Offset Error vs. V
REF
.
FIGURE 2-11:
Positive Gain Error vs.
Temperature.
FIGURE 2-12:
Signal-to-Noise Ratio (SNR)
vs. Input Frequency.
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
-4096 -3072 -2048 -1024
0
1024
2048
3072
4096
Code
DN
L
(L
SB
)
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
-50
-25
0
25
50
75
100
125
150
Temperature (°C)
DN
L
(L
SB
)
Positive DNL
Negaitive DNL
-1
0
1
2
3
4
itiv
e Gain Error (LSB)
-3
-2
-1
0
1
2
3
4
5
6
Pos
V
REF
(V)
6
8
10
12
14
16
18
20
2
II
VH
W
(
UU
R
U
/
6
%
0
2
4
6
0
1
2
3
4
5
6
V
REF
(V)
-0.8
-0.6
-0.4
-0.2
0
tiv
e Gain Error (LSB)
-1.2
-1
-50
0
50
100
150
Posi
t
Temperature (°C)
30
40
50
60
70
80
90
100
SNR (db)
0
10
20
30
1
10
100
Input Frequency (kHz)
2011 Microchip Technology Inc.
DS21697F-page 9
MCP3302/04
Note: Unless otherwise indicated, V
DD
= V
REF
= 5V, Full differential input configuration, V
SS
= 0V, F
SAMPLE
= 100 ksps,
F
CLK
= 21*F
SAMPLE
, T
A
= +25°C.
FIGURE 2-13:
Total Harmonic Distortion
(THD) vs. Input Frequency.
FIGURE 2-14:
Offset Error vs.
Temperature.
FIGURE 2-15:
Signal-to-Noise and
Distortion (SINAD) vs. Input Frequency.
FIGURE 2-16:
Signal-to-Noise and
Distortion (SINAD) vs. Input Signal Level.
FIGURE 2-17:
Effective Number of Bits
(ENOB) vs. V
REF
.
FIGURE 2-18:
Spurious Free Dynamic
Range (SFDR) vs. Input Frequency.
-70
-60
-50
-40
-30
-20
-10
0
THD (dB)
-100
-90
-80
70
1
10
100
Input Frequency (kHz)
2.7
2.8
2.9
3
3.1
Offset Error
(LSB)
2.5
2.6
-50
0
50
100
150
Temperature (°C)
72
73
74
75
76
77
78
79
SINAD (dB)
69
70
71
72
1
10
100
Input Frequency (kHz)
30
40
50
60
70
80
SINAD (dB)
0
10
20
-40
-30
-20
-10
0
Input Signal Level (dB)
9
10
11
12
13
ENOB (rms)
7
8
0
1
2
3
4
5
6
V
REF
(V)
30
40
50
60
70
80
90
100
SFDR (dB)
0
10
20
30
1
10
100
Input Frequency (kHz)
MCP3302/04
DS21697F-page 10
2011 Microchip Technology Inc.
Note: Unless otherwise indicated, V
DD
= V
REF
= 5V, Full differential input configuration, V
SS
= 0V, F
SAMPLE
= 100 ksps,
F
CLK
= 21*F
SAMPLE
, T
A
= +25°C.
FIGURE 2-19:
Frequency Spectrum of
10 kHz Input (Representative Part).
FIGURE 2-20:
Effective Number of Bits
(ENOB) vs. Input Frequency.
FIGURE 2-21:
Power Supply Rejection
(PSR) vs. Ripple Frequency. A 0.1 µF bypass
capacitor is connected to the V
DD
pin.
FIGURE 2-22:
I
DD
vs. V
DD
.
FIGURE 2-23:
I
DD
vs. Sample Rate.
FIGURE 2-24:
I
DD
vs. Temperature.
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0
10000
20000
30000
40000
50000
Frequency (Hz)
A
m
pl
itude
(dB
)
12.7
12.75
12.8
12.85
ENOB (rms)
12.6
12.65
1
10
100
Input Frequency (kHz)
-65
-60
-55
-50
-45
-40
-35
-30
PSR(dB)
-80
-75
-70
-65
1
10
100
1000
10000
Ripple Frequency (kHz)
0
50
100
150
200
250
300
350
400
450
2
2.5
3
3.5
4
4.5
5
5.5
6
V
DD
(V)
I
DD
(µ
A)
200
300
400
500
600
I
DD
(µA)
0
100
0
50
100
150
200
Sample Rate (ksps)
340
350
360
370
380
390
I
DD
(µA)
320
330
340
-50
0
50
100
150
Temperature (°C)