2012-2014 Microchip Technology Inc.
DS20002306B-page 1
MCP2025
Features:
• Compliant with LIN Bus Specifications Version
1.3, 2.1 and with SAE J2602-2
• Supports Baud Rates up to 20 kBaud
• 43V Load Dump Protected
• Maximum Continuous Input Voltage: 30V
• Wide LIN-Compliant Supply Voltage: 6.0-18.0V
• Extended Temperature Range: -40°C to +125°C
• Interface to PIC
®
EUSART and Standard USARTs
• Wake-Up on LIN Bus Activity or Local Wake Input
• Local Interconnect Network (LIN) Bus Pin:
- Internal Pull-Up Termination Resistor and
Diode for Slave Node
- Protected Against V
BAT
Shorts
- Protected Against Loss of Ground
- High-Current Drive
• T
XD
and LIN Bus Dominant Time-Out Function
• Two Low-Power Modes:
- Transmitter Off: 90 µA (typical)
- Power Down: 4.5 µA (typical)
• MCP2025 On-Chip Voltage Regulator:
- Output Voltage of 5.0V or 3.3V
at 70 mA Capability with Tolerances of ±3%
Over the Temperature Range
- Internal Short-Circuit Current Limit
- External Components Limited to Filter
Capacitor and Load Capacitor
• Automatic Thermal Shutdown
• High Electromagnetic Immunity (EMI), Low
Electromagnetic Emission (EME)
• Robust ESD Performance: ±15 kV for L
BUS
and
V
BB
Pin (IEC61000-4-2)
• Transient Protection for L
BUS
and V
BB
pins in
Automotive Environment (ISO7637)
• Meets Stringent Automotive Design Requirements,
including “OEM Hardware Requirements for LIN,
CAN and FlexRay Interfaces in Automotive
Applications”, Version 1.3, May 2012
• Multiple Package Options, Including Small
4x4 mm DFN Package
Description:
The MCP2025 provides a bidirectional, half-duplex
communication physical interface to meet the LIN bus
specification Revision 2.1 and SAE J2602-2. The
device incorporates a voltage regulator with 5V or 3.3V
at 70 mA regulated power supply output. The device
has been designed to meet the stringent quiescent
current requirements of the automotive industry, and
will survive +4
3
V load dump transients and double
battery jumps.
The MCP2025 family members include:
- MCP2025-500, 8-pin, LIN driver with 5.0V
regulator
- MCP2025-330, 8-pin, LIN driver with 3.3V
regulator
Package Types
MCP2025
PDIP, SOIC
V
SS
CS/LWAKE
L
BUS
1
2
3
4
8
7
6
5
V
BB
V
REG
RESET
T
XD
R
XD
MCP2025
4x4 DFN
1
2
3
4
8
7
6
5
EP
9
V
SS
CS/LWAKE
L
BUS
V
BB
V
REG
RESET
T
XD
R
XD
LIN Transceiver with Voltage Regulator
MCP2025
DS20002306B-page 2
2012-2014 Microchip Technology Inc.
MCP2025 Block Diagram
V
REG
R
XD
T
XD
CS/LWAKE
Short-Circuit
Protection
Thermal
Protection
Voltage
Regulator
Internal Circuits
V
REG
4.2V
Wake-Up Logic
and
Power Control
Ratiometric
Reference
Bus Wake-Up
Slope Control
Thermal and
Short-Circuit
Protection
Bus
Dominant
Timer
~ 30 k
RESET
V
BB
L
BUS
V
SS
2012-2014 Microchip Technology Inc.
DS20002306B-page 3
MCP2025
1.0
DEVICE OVERVIEW
The MCP2025 provides a physical interface between a
microcontroller and a LIN half-duplex bus. It is intended
for automotive and industrial applications with serial
bus baud rates up to 20 kBaud. This device will
translate the CMOS/TTL logic levels to LIN logic levels,
and vice versa.
The device offers optimum EMI and ESD performance
and it can withstand high voltage on the LIN bus. The
device supports two low-power modes to meet
automotive industry power consumption requirements.
The MCP2025 also provides a +5V or 3.3V regulated
power output at 70 mA.
1.1
Modes of Operation
The MCP2025 works in five modes: Power-On Reset,
Power-Down, Ready, Operation and Transmitter Off.
For an overview of all operational modes, please refer
to
Table 1-1
. For the operational mode transition,
please refer to
Figure 1-1
.
FIGURE 1-1:
STATE DIAGRAM
Note 1:
VREG_OK: Regulator Output Voltage > 0.8V
REG
_
NOM
.
2:
If the voltage on pin V
BB
falls below V
OFF
, the device will enter Power-On Reset mode from all other
modes, which is not shown in the figure.
3:
Faults include T
XD
/L
BUS
permanent dominant, L
BUS
short to V
BB
, thermal protection and VREG_OK is
false.
POR
(2)
V
REG
OFF
RX OFF
TX OFF
READY
V
REG
ON
RX ON
TX OFF
TX OFF
V
REG
ON
RX ON
TX OFF
POWER-DOWN
V
REG
OFF
RX OFF
TX OFF
OPERATION
V
REG
ON
RX ON
TX ON
V
BB
> V
ON
CS =
1 &T
XD
=
0&
CS/LWAKE =
0
&T
XD
=
0
CS/LWAKE =
1 &T
XD
=
1
VREG_OK =
1
(1)
CS/LWAKE =
1&
T
XD
=
1&
No Fault
(3)
CS/LWAKE =
0 or
Fault detected
(3)
CS/LWAKE =
1 OR
Voltage Rising Edge on L
BUS
CS/LWAKE =
0
MCP2025
DS20002306B-page 4
2012-2014 Microchip Technology Inc.
1.1.1
POWER-ON RESET MODE
Upon application of V
BB
, or whenever the voltage on
V
BB
is below the threshold of regulator turn-off voltage
V
OFF
(typically 4.50V), the device enters Power-On
Reset (POR) mode. During this mode, the device
maintains the digital section in a Reset mode and waits
until the voltage on the V
BB
pin rises above the
threshold of regulator turn-on voltage V
ON
(typically
5.75V) to enter Ready mode. In Power-On Reset
mode, the LIN physical layer and voltage regulator are
disabled and the RESET pin is switched to ground.
1.1.2
READY MODE
The device enters Ready mode from POR mode after
the voltage on V
BB
rises above the threshold of
regulator turn-on voltage V
ON
, or from Power-Down
mode when a remote or local wake-up event happens.
Upon entering Ready mode, the voltage regulator and
the receiver section of the transceiver are powered-up.
The transmitter remains in an off state. The device is
ready to receive data, but not to transmit. In order to
minimize the power consumption, the regulator
operates in a reduced-power mode. It has a lower
GBW product and it is thus slower. However, the 70 mA
drive capability is unchanged.
The device stays in Ready mode until the output of the
voltage regulator has stabilized and the CS/LWAKE pin
is high (‘1’).
1.1.3
OPERATION MODE
If the CS/LWAKE pin changes to high while V
REG
is OK
(V
REG
> 0.8*V
REG
_
NOM
) and the T
XD
pin is high, the
part enters Operation mode from either Ready or
Transmitter Off mode.
In this mode, all internal modules are operational. The
internal pull-up resistor between L
BUS
and V
BB
is
connected only in this mode.
The device goes into Transmitter Off mode at the falling
edge on the CS/LWAKE pin or when a fault is detected.
1.1.4
TRANSMITTER OFF MODE
If V
REG
is OK (V
REG
> 0.8*V
REG
_
NOM
), the Transmitter
Off mode can be reached from Ready mode by setting
CS/LWAKE to high when the T
XD
pin is low, or from
Operation mode by pulling down CS/LWAKE to low.
In Transmitter Off mode, the receiver is enabled but the
L
BUS
transmitter is off. It is a lower-power mode.
In order to minimize power consumption, the regulator
operates in a reduced-power mode. It has a lower
GBW product and it is thus slower. However, the 70 mA
drive capability is unchanged.
The transmitter is also turned off whenever the voltage
regulator is unstable or recovering from a fault. This
prevents unwanted disruption on the bus during times
of uncertain operation.
1.1.5
POWER-DOWN MODE
Power-Down mode is entered by pulling down both the
CS/LWAKE pin and the T
XD
pin to low from Transmitter
Off mode. In Power-Down mode, the transceiver and
the voltage regulator are both off. Only the bus wake-up
section and the CS/LWAKE pin wake-up circuits are in
operation. This is the lowest-power mode.
If any bus activity (e.g., a Break character) occurs or
CS/LWAKE is set to high during Power-Down mode,
the device will immediately enter Ready mode and
enable the voltage regulator. Then, once the regulator
output has stabilized (approximately 0.3 ms to 1.2 ms),
it can go into either Operation mode or Transmitter Off
mode. Refer to
Section 1.1.6 “Remote Wake-Up”
for
more details.
1.1.6
REMOTE WAKE-UP
The Remote Wake-Up sub-module observes the L
BUS
in order to detect bus activity. In Power-Down mode,
the normal LIN recessive/dominant threshold is
disabled and the LIN bus wake-up voltage threshold
V
WK
(
LBUS
) is used to detect bus activities. Bus activity
is detected when the voltage on the L
BUS
falls below
the LIN bus wake-up voltage threshold V
WK
(
LBUS
)
(approximately 3.4V) for at least t
BDB
(a typical duration
of 80 µs) followed by a rising edge. Such a condition
causes the device to leave Power-Down mode.
Note:
The T
XD
pin needs to be set high before
setting the CS/LWAKE pin to low in order
to jump and stay in Transmitter Off mode.
If the T
XD
pin is set or maintained low
before setting the CS/LWAKE pin to low,
the part will transition to Transmitter Off
mode and then jump to Power-Down
mode after a deglitch delay of about
20 µs.
2012-2014 Microchip Technology Inc.
DS20002306B-page 5
MCP2025
TABLE 1-1:
OVERVIEW OF OPERATIONAL MODES
State
Transmitter Receiver
Internal
Wake
Module
Voltage
Regulator
Operation
Comments
POR
OFF
OFF
OFF
OFF
Proceed to Ready mode after
V
BB
> V
ON
.
—
Ready
OFF
ON
OFF
ON
If CS/LWAKE is high, then proceed to
Operation or Transmitter Off mode.
Bus Off
state
Operation
ON
ON
OFF
ON
If CS/LWAKE is low, then proceed to
Transmitter Off mode.
Normal
Operation
mode
Power-Down
OFF
OFF
ON
Activity
Detect
OFF
On LIN bus rising edge or CS/LWAKE
high level, go to Ready mode.
Lowest-
Power
mode
Transmitter Off
OFF
ON
OFF
ON
If T
XD
and CS/LWAKE are low, then
proceed to Power-Down mode.
If T
XD
and CS/LWAKE are high, then
proceed to Operation mode.
Bus Off
state,
lower-power
mode
MCP2025
DS20002306B-page 6
2012-2014 Microchip Technology Inc.
1.2
Pin Descriptions
The descriptions of the pins are listed in
Table 1-2
.
1.2.1
BATTERY POSITIVE SUPPLY
VOLTAGE (V
BB
)
Battery Positive Supply Voltage pin. An external diode
is connected in series to prevent the device from being
reversely powered (refer to
Figure 1-7
).
1.2.2
CHIP SELECT AND LOCAL
WAKE-UP INPUT (CS/LWAKE)
Chip Select and Local Wake-Up Input pin (TTL level,
high-voltage tolerant). This pin controls the device state
transition. Refer to
Figure 1-1
.
An internal pull-down resistor will keep the CS/LWAKE
pin low to ensure that no disruptive data will be present
on the bus while the microcontroller is executing a
Power-On Reset and I/O initialization sequence. When
CS/LWAKE is ‘1’, a weak pull-down (~600 kΩ) is used
to reduce current. When CS/LWAKE is ‘0’, a stronger
pull-down (~300 kΩ) is used to maintain the logic level.
This pin may also be used as a local wake-up input
(see
Figure 1-7
). The microcontroller will set the I/O pin
to control the CS/LWAKE. An external switch or
another source can then wake up both the transceiver
and the microcontroller.
1.2.3
GROUND (V
SS
)
Ground pin.
1.2.4
LIN BUS (L
BUS
)
LIN Bus pin. L
BUS
is a bidirectional LIN bus interface
pin and is controlled by the signal T
XD
. It has an open
collector output with a current limitation. To reduce
electromagnetic emission, the slopes during signal
changes are controlled and the L
BUS
pin has
corner-rounding control for both falling and rising
edges.
The internal LIN receiver observes the activities on the
LIN bus and generates the output signal R
XD
that
follows the state of the L
BUS
. A 1
st
degree 160 kHz
low-pass input filter optimizes electromagnetic
immunity.
1.2.5
RECEIVE DATA OUTPUT (R
XD
)
Receive Data Output pin. The R
XD
pin is a standard
CMOS output pin and it follows the state of the L
BUS
pin.
1.2.6
TRANSMIT DATA INPUT (T
XD
)
Transmit Data Input pin (TTL level, HV-compliant,
adaptive pull-up). The transmitter reads the data
stream on the T
XD
pin and sends it to the LIN bus. The
L
BUS
pin is low (dominant) when T
XD
is low, and high
(recessive) when T
XD
is high.
T
XD
is internally pulled-up to approximately 4.2V. When
T
XD
is ‘0’, a weak pull-up (~900 kΩ) is used to reduce
current. When T
XD
is ‘1’, a stronger pull-up (~300 kΩ)
is used to maintain the logic level. A series
reverse-blocking diode allows applying T
XD
input
voltages greater than the internally generated 4.2V and
renders the T
XD
pin HV-compliant up to 30V (see
MCP2025 Block Diagram
).
TABLE 1-2:
PIN FUNCTION TABLE
Pin Name
Pin Number
Pin Type
Description
8-lead PDIP
4x4 DFN
V
BB
1
1
Power
Battery
CS/LWAKE
2
2
TTL input, HV-tolerant
Chip Select and Local Wake-up Input
V
SS
3
3
Power
Ground
L
BUS
4
4
I/O, HV
LIN Bus
R
XD
5
5
Output
Receive Data Output
T
XD
6
6
Input, HV-tolerant
Transmit Data Input
RESET
7
7
Open-drain output, HV-tolerant
Reset Output
V
REG
8
8
Output
Voltage Regulator Output
EP
—
9
—
Exposed Thermal Pad
Note:
CS/LWAKE should NOT be tied directly to
the V
REG
pin, as this could force the
MCP2025 into Operation mode before the
microcontroller is initialized.
2012-2014 Microchip Technology Inc.
DS20002306B-page 7
MCP2025
1.2.7
RESET
Reset output pin. This is an open-drain output pin. It
indicates the internal voltage has reached a valid,
stable level. As long as the internal voltage is valid
(above 0.8 V
REG
), this pin will present high impedance;
otherwise, the RESET pin switches to ground.
1.2.8
POSITIVE SUPPLY VOLTAGE
REGULATOR OUTPUT (V
REG
)
Positive Supply Voltage Regulator Output pin. An
on-chip Low Dropout Regulator (LDO) gives +5.0 or
+3.3V at 70 mA regulated voltage on this pin.
1.2.9
EXPOSED THERMAL PAD (EP)
There is an internal electrical connection between the
Exposed Thermal Pad (EP) and the V
SS
pin; they must
be connected to the same potential on the Printed
Circuit Board (PCB).
This pad can be connected to a PCB ground plane to
provide a larger heat sink. This improves the package
thermal resistance (
JA
).
1.3
Fail-Safe Features
1.3.1
GENERAL FAIL-SAFE FEATURES
• An internal pull-down resistor on the CS/LWAKE
pin disables the transmitter if the pin is floating.
• An internal pull-up resistor on the T
XD
pin places
T
XD
in high and the L
BUS
in recessive if the T
XD
pin is floating.
• High-Impedance and low-leakage current on L
BUS
during loss of power or ground.
• The current limit on L
BUS
protects the transceiver
from being damaged if the pin is shorted to V
BB
.
1.3.2
THERMAL PROTECTION
The thermal protection circuit monitors the die
temperature and is able to shut down the
LIN
transmitter and voltage regulator.
There are three causes for a thermal overload. A
thermal shutdown can be triggered by any one, or a
combination of, the following thermal overload
conditions:
• Voltage regulator overload
• LIN bus output overload
• Increase in die temperature due to increase in
environment temperature
The recovery time from the thermal shutdown is equal
to adequate cooling time.
Driving the T
XD
and checking the R
XD
pin make it
possible to determine whether there is a bus contention
(T
XD
= high, R
XD
= low) or a thermal overload
condition (T
XD
= low, R
XD
= high).
FIGURE 1-2:
THERMAL SHUTDOWN
STATE DIAGRAMS
1.3.3
T
XD
/L
BUS
TIME-OUT TIMER
The LIN bus can be driven to a dominant level, either
from the T
XD
pin or externally. An internal timer
deactivates the L
BUS
transmitter if a dominant status
(low) on the LIN bus lasts longer than Bus Dominant
Time-Out Time, t
TO
(
LIN
) (approximately
20 milliseconds). At the same time, the R
XD
output is
put in recessive (high) and the internal pull-up resistor
between L
BUS
and V
BB
is disconnected. The timer is
reset on any recessive L
BUS
status or POR mode. The
recessive status on L
BUS
can be caused either by the
bus being externally pulled-up or by the T
XD
pin being
returned high.
1.4
Internal Voltage Regulator
The MCP2025 has a positive regulator capable of
supplying +5.00 or +3.30 V
DC
±3% at up to 70 mA of
load current over the entire operating temperature
range of -40°C to +125°C. The regulator uses an LDO
design, is short-circuit-protected and will turn the
regulator output off if its output falls below the shutdown
voltage threshold, V
SD
.
With a load current of 70 mA, the minimum
input-to-output voltage differential required for the
output to remain in regulation is typically +0.5V (+1V
maximum over the full operating temperature range).
Quiescent current is less than 100 µA with a full 70 mA
load current when the input-to-output voltage
differential is greater than +3.00V.
Regarding the correlation between V
BB
, V
REG
and I
DD
,
please refer to
Figures 1-4
and
1-5
. When the input
voltage (V
BB
) drops below the differential needed to
provide stable regulation, the voltage regulator output,
V
REG
, will track the input down to approximately V
OFF
,
at which point the regulator will turn off the output. This
will allow PIC
®
microcontrollers with internal POR
circuits to generate a clean arming of the POR trip
point. The MCP2025 will then monitor V
BB
and turn on
the regulator when V
BB
is above the threshold of
regulator turn-on voltage, V
ON
.
In Power-Down mode, the V
BB
monitor is turned off.
Voltage
Regulator
Shutdown
Operation
Mode
Transmitter
Shutdown
Output
Overload
LIN Bus
Shorted to
V
BB
Temp < SHUTDOWN
TEMP
Temp < SHUTDOWN
TEMP
MCP2025
DS20002306B-page 8
2012-2014 Microchip Technology Inc.
Under specific ambient temperature and battery
voltage range, the voltage regulator can output as high
as 150 mA current. For current load capability of the
voltage regulator, refer to
Figures 2-8
and
2-9
.
The regulator requires an external output bypass
capacitor for stability. See
Figure 2-1
for correct
capacity and ESR for stable operation.
In worst-case scenarios, the ceramic capacitor may
derate by 50%, based on tolerance, voltage and
temperature. Therefore, in order to ensure stability,
ceramic capacitors smaller than 10 µF may require a
small series resistance to meet the ESR requirements,
as shown in
Table 1-3
.
FIGURE 1-3:
VOLTAGE REGULATOR BLOCK DIAGRAM
Note:
The regulator has an overload current limit
of approximately 250 mA. The regulator
output voltage, V
REG
, is monitored. If
output voltage V
REG
is lower than V
SD
, the
voltage regulator will turn off. After a
recovery time of about 3 ms, the V
REG
will
be checked again. If there is no short
circuit, (V
REG
> V
SD
), then the voltage
regulator remains on.
Note:
A ceramic capacitor of at least 10 µF or a
tantalum capacitor of at least 2.2 µF is
recommended for stability.
TABLE 1-3:
RECOMMENDED SERIES
RESISTANCE FOR CERAMIC
CAPACITORS
Resistance
Capacitor
1
1 µF
0.47
2.2 µF
0.22
4.7 µF
0.1
6.8 µF
Pass
Element
Sampling
Network
Buffer
V
REG
V
BB
V
SS
Fast
Transient
Loop
V
REF
2012-2014 Microchip Technology Inc.
DS20002306B-page 9
MCP2025
FIGURE 1-4:
VOLTAGE REGULATOR OUTPUT ON POWER-ON RESET
FIGURE 1-5:
VOLTAGE REGULATOR OUTPUT ON OVERCURRENT SITUATION
5
3
2
0
(1)
(2)
(3)
t
0
t
6
2
8
4
V
BB
V
V
REG
V
1
4
V
ON
Minimum V
BB
to maintain regulation
V
REG
-
NOM
(4)
V
OFF
Note 1:
Start-up, V
BB
< V
ON
, regulator off.
2:
V
BB
> V
ON
, regulator on.
3:
V
BB
Minimum V
BB
to maintain regulation.
4:
V
BB
< V
OFF
, regulator will turn off.
V
SD
0
(1)
(2)
t
0
t
I
LIM
I
REG
mA
V
REG
V
V
REG
-
NOM
1
2
3
4
5
6
Note 1:
I
REG
less than l
LIM
, regulator on.
2:
After I
REG
exceeds l
LIM
, the voltage regulator output will be reduced until V
SD
is reached.
MCP2025
DS20002306B-page 10
2012-2014 Microchip Technology Inc.
1.5
Optional External Protection
1.5.1
REVERSE BATTERY PROTECTION
An external reverse-battery-blocking diode should be
used to provide polarity protection (see
Figure 1-7
).
1.5.2
TRANSIENT VOLTAGE
PROTECTION (LOAD DUMP)
An external 43V transient suppressor (TVS) diode,
between V
BB
and ground, with a transient protection
resistor (R
TP
) in series with the battery supply and the
V
BB
pin, protects the device from power transients and
ESD events greater than 43V (see
Figure 1-7
). The
maximum value for the R
TP
protection resistor depends
upon two parameters: the minimum voltage the part will
start at and the impacts of this R
TP
resistor on the V
BB
value, thus on the bus recessive level and slopes.
This leads to a set of three equations to fulfill.
Equation 1-1
provides a maximum R
TP
value according
to the minimum battery voltage the user wants.
Equation 1-2
provides a maximum R
TP
value
according to the maximum error on the recessive level,
thus V
BB
,
since the part uses V
BB
as the reference
value for the recessive level.
Equation 1-3
provides a maximum R
TP
value
according to the maximum relative variation the user
can accept on the slope when I
REG
varies.
Since both
Equations 1-1
and
1-2
must be fulfilled, the
maximum allowed value for R
TP
is thus the smaller of the
two values found when solving
Equations 1-1
and
1-2
.
Usually,
Equation 1-1
gives the higher constraint
(smaller value) for R
TP
, as shown in the following
example where V
BATMIN
is 8V.
However, the user needs to verify that the value found
with
Equation 1-1
fulfills
Equations 1-2
and
1-3
.
While this protection is optional, it should be
considered as good engineering practice.
EQUATION 1-1:
Assume that V
BATMIN
= 8V.
Equation 1-1
gives 10
.
EQUATION 1-2:
Assume that
V
RECCESSIVE
= 1V and
I
REGMAX
= 50 mA.
Equation 1-2
gives 20
.
EQUATION 1-3:
Assume that
Slope = 15%, V
BATMIN
= 8V and
I
REGMAX
= 50 mA.
Equation 1-3
gives 20
.
1.5.3
C
BAT
CAPACITOR
Selecting C
BAT
= 10 x C
REG
is recommended.
However, this leads to a high-value capacitor. Lower
values for C
BAT
capacitor can be used with respect to
some rules. In any case, the voltage at the V
BB
pin
should remain above V
OFF
when the device is turned
on.
The current peak at start-up (due to the fast charge of
the C
REG
and C
BAT
capacitors) may induce a
significant drop on the V
BB
pin. This drop is
proportional to the impedance of the V
BAT
connection
(see
Figure 1-7
).
The V
BAT
connection is mainly inductive and resistive.
Therefore, it can be modeled as a resistor (R
TOT
) in
series with an inductor (L). R
TOT
and L can be
measured.
The following formula gives an indication of the
minimum value of C
BAT
using R
TOT
and L:
EQUATION 1-4:
Equation 1-4
allows lower C
BAT
/C
REG
values than the
10x ratio we recommend.
R
TP
V
BATMIN
5.5V
–
250 mA
----------------------------------------
5.5V
V
OFF
1.0V
+
=
Where:
250 mA = Peak current at power-on when
V
BB
= 5.5V
R
TP
V
RECESSIVE
I
REGMAX
----------------------------------
Where:
V
RECESSIVE
= Maximum variation tolerated on
the recessive level
R
TP
Slope
V
BA TMIN
1V
–
I
REGMAX
-----------------------------------------------------------------
Where:
Slope = Maximum variation tolerated on the
slope level
I
REGMAX
= Maximum current the current will
provide to the load
V
BATMIN
> V
OFF
+ 1.0V
C
BAT
C
REG
--------------
100L
2
R
TOT
2
+
1
L
2
R
TOT
2
100
-------------
+
+
------------------------------------
=
Where:
L = Inductor (measured in mH)
R
TOT
= R
LINE
+ R
TP
(measured in
)