LND01 Lateral N-Channel Depletion-Mode MOSFET Data Sheet

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 2017 Microchip Technology Inc.

DS20005696A-page  1

LND01

Features

• Bi-directional
• Low On-resistance
• Low Input Capacitance
• Fast Switching Speeds
• High Input Impedance and High Gain
• Low Power Drive Requirement
• Ease of Paralleling

Applications

• Normally-on Switches
• Solid-state Relays
• Converters
• Constant Current Sources
• Analog Switches

General Description

The  LND01 is a low-threshold, Depletion-mode 
(normally-on) transistor that uses an advanced lateral 
DMOS structure and a well-proven silicon gate 
manufacturing process. This combination produces a 
device with the power handling capabilities of bipolar 
transistors as well as the high input impedance and 
positive temperature coefficient inherent in 
MOS devices. Characteristic of all MOS structures, this 
device is free from thermal runaway and thermally 
induced secondary breakdown.
The body of the transistor is connected to the gate pin. 
The channel is therefore being pinched off by both the 
gate and body. The gate pin has a diode connected to 
the drain terminal and another diode connected to the 
source terminal.

Package Type

5-lead SOT-23

See 

Table 2-1

 for pin information.

DRAIN

SOURCE

GATE

N/C

N/C

Lateral N-Channel Depletion-Mode MOSFET

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LND01

DS20005696A-page  2

 2017 Microchip Technology Inc.

1.0

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings†

Drain-to-source Voltage ....................................................................................................................................... BV

DSX

Source-to-drain Voltage........................................................................................................................................ BV

SDX

Gate-to-source Voltage ............................................................................................................................ –12V to +0.6V
Gate-to-drain Voltage ............................................................................................................................... –12V to +0.6V
Operating Ambient Temperature, T

A

 ................................................................................................... –25°C to +125°C

 Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the 
device. This is a stress rating only, and functional operation of the device at those or any other conditions above those 
indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for 
extended periods may affect device reliability. 

DC ELECTRICAL CHARACTERISTICS 

Electrical Specifications: T

A

 = 25°C unless otherwise specified. (

Note 1

)

Parameter

Sym.

Min.

Typ.

Max.

Unit

Conditions 

Drain-to-source Breakdown Voltage

BV

DSX

9

V

V

GS

 = –3V, I

DS 

= 10 µA

Source-to-drain Breakdown Voltage

BV

SDX

9

V

V

GD

 = –3V, I

SD 

= 10 µA

Gate-to-source Off Voltage

V

GS(OFF)

–0.8

–3

V

V

DS

 = 9V, I

DS

 = 1 µA

Source-to-gate Off Voltage

V

SG(OFF)

–0.8

–3

V

V

SD

 = 9V, I

SD

 = 1 µA

Gate-to-source Diode

V

GS

–12

0.6

V

I

GS

 = ±1 µA

Gate-to-drain Diode

V

GD

–12

0.6

V

I

GD

 = ±1 µA

Drain-to-source Leakage Current

I

DS(OFF)

1

µA

V

GS

 = –3V, V

DS

 = 9V

Source-to-drain Leakage Current

I

SD(OFF)

1

µA

V

GD

 = –3V, V

SD

 = 9V

Saturated Drain-to-source Current

I

DSS

300

mA

V

GS

 = 0V, V

DS

 = 9V

Saturated Source-to-drain Current

I

SDD

300

mA

V

GD

 = 0V, V

SD

 = 9V

Static Drain-to-source On-state      
Resistance

R

DS(ON)

0.9

1.4

V

GS

 = 0V, I

DS

 = 100 mA

Static Source-to-drain On-state     
Resistance

R

SD(ON)

0.9

1.4

V

GD

 = 0V, I

SD

 = 100 mA

Note 1: All DC parameters are 100% tested at 25°C unless otherwise stated. 

(Pulse test: 300 µs pulse, 2% duty cycle)

2: Specification is obtained by characterization and is not 100% tested.

AC ELECTRICAL CHARACTERISTICS 

Electrical Specifications: T

A

 = 25°C unless otherwise specified. (

Note 2

)

Parameter

Sym.

Min.

Typ.

Max.

Unit

Conditions 

Forward Transconductance

G

FS

200

mmho V

DS

 = 9V, I

DS

 = 50 mA

Input Capacitance

C

ISS

46

pF

V

GS

 = –3V, V

DS

 = 5V, 

f = 1 MHz

Common Source Output Capacitance

C

OSS

32

pF

Reverse Transfer Capacitance

C

RSS

23

pF

Turn-on Delay Time

t

d(ON)

3.8

ns

V

DD 

= 9V, I

DS

 = 100 mA,          

R

GEN

 = 25Ω

Rise Time

t

r

11

ns

Turn-off Delay Time

t

d(OFF)

1

ns

Fall Time

t

f

6.4

ns

Note 1: All DC parameters are 100% tested at 25°C unless otherwise stated. 

(Pulse test: 300 µs pulse, 2% duty cycle)

2: Specification is obtained by characterization and is not 100% tested.

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TEMPERATURE SPECIFICATIONS

Electrical Characteristics: Unless otherwise specified, for all specifications T

A

 =T

J

 = +25°C.

Parameter

Sym.

Min.

Typ.

Max.

Unit

Conditions

TEMPERATURE RANGE
Operating Ambient Temperature

T

A

–25

+125

°C

PACKAGE THERMAL RESISTANCE
5-lead SOT-23 

JA

253

°C/W

THERMAL CHARACTERISTICS

Package

 I

(

 1

)

(Continuous)

(mA)

 I

D

(Pulsed)

(mA)

Power Dissipation at T

= 25°C 

(W)

5-lead SOT-23 

330

600

0.36

Note 1: I

D

 (continuous) is limited by maximum T

J

.

 2017 Microchip Technology Inc.

DS20005696A-page  3

LND01

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LND01

DS20005696A-page  4

 2017 Microchip Technology Inc.

2.0

PIN DESCRIPTION

Table 2-1

 shows the description of pins in LND01. 

Refer to 

Package Type

 for the location of pins.

 

TABLE 2-1:

PIN FUNCTION TABLE 

Pin Number

Pin Name

Description

1

N/C

Not connected

2

Gate

Gate

3

N/C

Not connected

4

Drain

Drain

5

Source

Source

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 2017 Microchip Technology Inc.

DS20005696A-page  5

LND01

3.0

FUNCTIONAL DESCRIPTION

Figure 3-1

 illustrates the switching waveforms and test 

circuit for LND01.

 

90%

10%

90%

90%

10%

10%

Pulse

Generator

VDD

R

L

OUTPUT

D.U.T.

t

(ON)

t

d(ON)

t

(OFF)

t

d(OFF)

t

r

INPUT

0V

INPUT

-3.0V

VDD

OUTPUT

0V

R

GEN

t

f

SOURCE

GATE

DRAIN

FIGURE 3-1:

Switching Waveforms and Test Circuit.

 

TABLE 3-1:

PRODUCT SUMMARY

BV

DSX

/BV

SDX

(V)

R

DS(ON)

/R

SD(ON)

(Maximum) 

(Ω)

I

DSS

/I

SSD

 

(Maximum) 

(mA) 

9

1.4

300

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LND01

DS20005696A-page  6

 2017 Microchip Technology Inc.

4.0

PACKAGING INFORMATION

4.1

Package Marking Information

Legend: XX...X

Product Code or Customer-specific information

Y

Year code (last digit of calendar year)

YY

Year code (last 2 digits of calendar year)

WW

Week code (week of January 1 is week ‘01’)

NNN

Alphanumeric traceability code

 Pb-free 

JEDEC

®

 designator for Matte Tin (Sn)

*

This package is Pb-free. The Pb-free JEDEC designator (     )

can be found on the outer packaging for this package.

              Pre-plated

Note:

In the event the full Microchip part number cannot be marked on one line, it will 
be carried over to the next line, thus limiting the number of available 
characters for product code or customer-specific information. Package may or 
not include the corporate logo.

3

e

3

e

WWNNN

XXXXY

15241

NDU7

5-lead SOT-23

Example 

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5-Lead SOT-23 Package Outline (K1)

2.90x1.60mm body, 1.45mm height (max), 0.95mm pitch 

Symbol

A

A1

A2

b

D

E

E1

e

e1

L

L1

L2

ș

ș

Dimension

(mm)

MIN

0.90*

0.00

0.90

0.30

2.75*

2.60*

1.45*

0.95

BSC

1.90

BSC

0.30

0.60

REF

0.25

BSC

0

O

5

O

NOM

-

-

1.15

-

2.90

2.80

1.60

0.45

4

O

10

O

MAX

1.45

0.15

1.30

0.50

3.05*

3.00*

1.75*

0.60

8

O

15

O

JEDEC Registration MO-178, Variation AA, Issue C, Feb. 2000.
7KLVGLPHQVLRQLVQRWVSHFL¿HGLQWKH-('(&GUDZLQJ
Drawings not to scale.

1

5

D

Seating

Plane

Gauge

Plane

L

L1

L2

Top View

Side View

View A - A

View B

View B

θ1

θ

E1 E

A

A2

A1

A

A

Seating

Plane

e

b

Note 1

(Index Area

D/2 x E1/2)

e1

Note:

1.

$3LQLGHQWL¿HUPXVWEHORFDWHGLQWKHLQGH[DUHDLQGLFDWHG7KH3LQLGHQWL¿HUFDQEHDPROGHGPDUNLGHQWL¿HUDQHPEHGGHGPHWDOPDUNHURU
a printed indicator.

Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.

Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.

 2017 Microchip Technology Inc.

DS20005696A-page  7

LND01

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LND01

DS20005696A-page  8

 2017 Microchip Technology Inc.

NOTES:

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 2017 Microchip Technology Inc.

DS20005696A-page  9

LND01

APPENDIX A: REVISION HISTORY

Revision A (June 2017)

• Converted Supertex Doc# DSFP-LND01                

to Microchip DS20005696A

• Changed the package marking format
• Changed the quantity of the 5-lead SOT-23 K1 

package from 2500/Reel to 3000/Reel

• Made minor text changes throughout the docu-

ment

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LND01

DS20005696A-page  10

 2017 Microchip Technology Inc.

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office

.

Example:

a)  LND01K1-G

:         Lateral N‐Channel Depletion‐Mode 

MOSFET, 5‐lead SOT‐23,                        
3000/Reel 

PART NO.

Device

Device:

LND01

=

Lateral N-Channel Depletion-Mode MOSFET

Package:

K1

=

5-lead SOT-23

Environmental:

G

=

Lead (Pb)-free/RoHS-compliant Package

Media Type: 

(blank)

=

3000/Reel for a K1 Package

      XX

          Package

-           

X            -                  X

               Environmental    Media Type

          Options

Maker
Microchip Technology Inc.