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Highlights
• Optimized for medium performance applications
• Efficient architecture with low CPU overhead
• Easily interfaces to most 16-bit embedded CPU’s
• Integrated PHY with HP Auto-MDIX support
• Supports audio & video streaming over Ethernet:
multiple standard-definition (SD) MPEG2 streams
Target Applications
• Basic cable, satellite, and IP set-top boxes
• Digital video recorders
• Video-over IP solutions, IP PBX & video phones
• Wireless routers & access points
• Audio distribution systems
• Printers, kiosks, security systems
• General embedded applications
Key Benefits
• Non-PCI Ethernet controller for medium perfor-
mance applications
- 16-bit interface
- Burst-mode read support
- External MII Interface
• Eliminates dropped packets
- Internal buffer memory can store over 200
packets
- Automatic PAUSE and back-pressure flow
control
• Minimizes CPU overhead
- Supports Slave-DMA
- Interrupt Pin with Programmable Hold-off
timer
• Reduces system cost and increases design flexi-
bility
• SRAM-like interface easily interfaces to most
embedded CPU’s or SoC’s
• Reduced Power Modes
- Numerous power management modes
- Wake on LAN
- Magic packet wakeup
- Wakeup indicator event signal
- Link Status Change
• Single chip Ethernet controller
- Fully compliant with IEEE 802.3/802.3u stan-
dards
- Integrated Ethernet MAC and PHY
- 10BASE-T and 100BASE-TX support
- Full- and Half-duplex support
- Full-duplex flow control
- Backpressure for half-duplex flow control
- Preamble generation and removal
- Automatic 32-bit CRC generation and
checking
- Automatic payload padding and pad removal
- Loop-back modes
• Flexible address filtering modes
- One 48-bit perfect address
- 64 hash-filtered multicast addresses
- Pass all multicast
- Promiscuous mode
- Inverse filtering
- Pass all incoming with status report
- Disable reception of broadcast packets
• Integrated 10/100 Ethernet PHY
- Supports HP Auto-MDIX
- Auto-negotiation
- Supports energy-detect power down
• Host bus interface
- Simple, SRAM-like interface
- 16-bit data bus
- 16Kbyte FIFO with flexible TX/RX allocation
- One configurable host interrupt
• Miscellaneous features
- Low-profile 100-pin TQFP, RoHS Compliant
package
- Integrated 1.8V regulator
- General Purpose Timer
- Optional EEPROM interface
- Support for 3 status LEDs multiplexed with
Programmable GPIO signals
• Single 3.3V Power Supply with 5V tolerant
I/O
• -40
C to +85C Industrial Temperature Support
LAN9215i
16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX
and Industrial Temperature Support
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2006-2017 Microchip Technology Inc.
TO OUR VALUED CUSTOMERS
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The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
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LAN9215i
Table of Contents
1.0 General Description ........................................................................................................................................................................ 4
2.0 Pin Description and Configuration .................................................................................................................................................. 9
3.0 Functional Description .................................................................................................................................................................. 18
4.0 Internal Ethernet PHY ................................................................................................................................................................... 53
5.0 Register Description ...................................................................................................................................................................... 62
6.0 Timing Diagrams ......................................................................................................................................................................... 108
7.0 Operational Characteristics ......................................................................................................................................................... 119
8.0 Package Information ................................................................................................................................................................... 126
Appendix A: Data Sheet Revision History ......................................................................................................................................... 127
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1.0
GENERAL DESCRIPTION
The LAN9215i is a full-featured, single-chip 10/100 Ethernet controller designed for embedded applications where per-
formance, flexibility, ease of integration and system cost control are required. The LAN9215i has been architected to
provide the best price-performance ratio for any 16-bit application with medium performance requirements. The
LAN9215i is fully IEEE 802.3 10BASE-T and 802.3u 100BASE-TX compliant, and supports HP Auto-MDIX.
The LAN9215i includes an integrated Ethernet MAC and PHY with a high-performance SRAM-like slave interface. The
simple, yet highly functional host bus interface provides a glue-less connection to most common 16-bit microprocessors
and microcontrollers as well as 32-bit microprocessors with a 16-bit external bus. The LAN9215i includes large transmit
and receive data FIFOs to accommodate high latency applications. In addition, the LAN9215i memory buffer architec-
ture allows highly efficient use of memory resources by optimizing packet granularity.
Applications
The LAN9215i is well suited for many medium-performance embedded applications, including:
• Printers, kiosks, POS terminals and security systems
• Audio distribution systems
• General embedded systems
• Basic cable, satellite and IP set-top boxes
• Voice-over-IP solutions
The LAN9215i also supports features which reduce or eliminate packet loss. Its internal 16-KByte SRAM can hold over
200 received packets. If the receive FIFO gets too full, the LAN9215i can automatically generate flow control packets to
the remote node, or assert back-pressure on the remote node by generating network collisions.
The LAN9215i supports numerous power management and wakeup features. The LAN9215i can be placed in a reduced
power mode and can be programmed to issue an external wake signal via several methods, including “Magic Packet”,
“Wake on LAN” and “Link Status Change”. This signal is ideal for triggering system power-up using remote Ethernet
wakeup events. The device can be removed from the low power state via a host processor command.
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LAN9215i
1.1
Block Diagram
The Microchip LAN9215i integrated 10/100 MAC/PHY controller is a peripheral chip that performs the function of trans-
lating parallel data from a host controller into Ethernet packets. The LAN9215i Ethernet MAC/PHY controller is designed
and optimized to function in an embedded environment. All communication is performed with programmed I/O transac-
tions using the simple SRAM-like host interface bus.
The diagram shown above, describes a typical system configuration of the LAN9215i in a typical embedded environ-
ment.
The LAN9215i is a general purpose, platform independent, Ethernet controller. The LAN9215i consists of four major
functional blocks. The four blocks are:
• 10/100 Ethernet PHY
• 10/100 Ethernet MAC
• RX/TX FIFOs
• Host Bus Interface (HBI)
FIGURE 1-1:
SYSTEM BLOCK DIAGRAM
Microprocessor/
Microcontroller
LAN9215i
System
Peripherals
System Memory
EEPROM
(Optional)
25MHz
XTAL
System Bus
Magnetics
Ethernet
LEDS/GPIO
External
PHY
MII
Magnetics
Optional
Optional
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1.2
Compatibility with First-generation LAN9118 Family Devices
The LAN9215i is driver-, register-, and footprint-compatible with previous generation LAN9118 Family devices. Drivers
written for these products will work with the LAN9215i. However, in order to support HP Auto-MDIX, other components
such as the magnetics and the passive components around the magnetics need to change, and supporting these
changes does require a minor PCB change. A reference design for the LAN9215i will be available on Microchip’s web-
site.
1.3
Internal Block Overview
This section provides an overview of each of these functional blocks as shown in Figure 1-2, "Internal Block Diagram".
FIGURE 1-2:
INTERNAL BLOCK DIAGRAM
1.4
10/100 Ethernet PHY
The LAN9215i integrates an IEEE 802.3 physical layer for twisted pair Ethernet applications. The PHY can be config-
ured for either 100 Mbps (100BASE-TX) or 10 Mbps (10BASE-T) Ethernet operation in either full or half duplex config-
urations. The PHY block supports HP Auto-MDIX and auto-negotiation.
Minimal external components are required for the utilization of the Integrated PHY.
1.5
10/100 Ethernet MAC
The transmit and receive data paths are separate within the MAC allowing the highest performance especially in full
duplex mode. The data paths connect to the PIO interface Function via separate busses to increase performance. Pay-
load data as well as transmit and receive status is passed on these busses.
A third internal bus is used to access the MAC’s Control and Status Registers (CSR’s). This bus is accessible from the
host through the PIO interface function.
On the backend, the MAC interfaces with the internal 10/100 PHY through a MII (Media Independent Interface) port
internal to the LAN9215i. The MAC CSR's also provide a mechanism for accessing the PHY’s internal registers through
the internal SMI (Serial Management Interface) bus. The Ethernet MAC can also communicate with an external PHY.
This mode however, is optional.
10/100
Ethernet
MAC
2kB to 14kB
Configurable TX FIFO
2kB to 14kB
Configurable RX FIFO
Interrupt
Controller
GP Timer
PIO
Controller
3.3V to 1.8V
Core Regulator
25MHz
+3.3V
EEPROM
Controller
EEPROM
(Optional)
RX Status FIFO
TX Status FIFO
MIL - TX Elastic
Buffer - 2K bytes
MIL - RX Elastic
Buffer - 128 bytes
Power
Management
IRQ
FIFO_SEL
PME
Wakup Indicator
Host Bus Interface
(HBI)
16-bit SRAM I/F
PLL
+3.3V
3.3V to 1.8V
PLL Regulator
10/100
Ethernet
PHY
LAN
Optional
External PHY - MII
Interface
MU
X
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LAN9215i
The MAC Interface Layer (MIL), within the MAC, contains a 2K Byte transmit and a 128 Byte receive FIFO which is sep-
arate from the TX and RX FIFOs. The FIFOs within the MAC are not directly accessible from the host interface. The
differentiation between the TX/RX FIFO memory buffers and the MAC buffers is that when the transmit or receive pack-
ets are in the MAC buffers, the host no longer can control or access the TX or RX data. The MAC buffers (both TX and
RX) are in effect the working buffers of the Ethernet MAC logic. In the case of reception, the data must be moved first
to the RX FIFOs for the host to access the data. For TX operations, the MIL operates in store-and-forward mode and
will queue an entire frame before beginning transmission.
1.6
Receive and Transmit FIFOs
The Receive and Transmit FIFOs allow increased packet buffer storage to the MAC. The FIFOs are a conduit between
the host interface and the MAC through which all transmitted and received data and status information is passed. Deep
FIFOs allow a high degree of latency tolerance relative to the various transport and OS software stacks thus reducing
or minimizing overrun conditions. Like the MAC, the FIFOs have separate receive and transmit data paths. In addition,
the RX and TX FIFOs are configurable in size, allowing increased flexibility.
1.7
Interrupt Controller
The LAN9215i supports a single programmable interrupt. The programmable nature of this interrupt allows the user the
ability to optimize performance dependent upon the application requirement. Both the polarity and buffer type of the
interrupt pin are configurable for the external interrupt processing. The interrupt line can be configured as an open-drain
output to facilitate the sharing of interrupts with other devices. In addition, a programmable interrupt de-assertion interval
is provided.
1.8
GPIO Interface
A 3-bit GPIO and 2-bit GPO (Multiplexed on the EEPROM and LED Pins) interface is included in the LAN9215i. It is
accessible through the host bus interface via the CSRs. The GPIO signals can function as inputs, push-pull outputs and
open drain outputs. The GPIO’s (GPO’s are not configurable) can also be configured to trigger interrupts with program-
mable polarity.
1.9
Serial EEPROM Interface
A serial EEPROM interface is included in the LAN9215i. The serial EEPROM is optional and can be programmed with
the LAN9215i MAC address. The LAN9215i can optionally load the MAC address automatically after power-on reset,
hardware reset, or soft reset.
1.10
Power Management Controls
The LAN9215i supports comprehensive array of power management modes to allow use in power sensitive applica-
tions. Wake on LAN, Link Status Change and Magic Packet detection are supported by the LAN9215i. An external PME
(Power Management Event) interrupt is provided to indicate detection of a wakeup event.
1.11
General Purpose Timer
The general-purpose timer has no dedicated function within the LAN9215i and may be programmed to issue a timed
interrupt.
1.12
Host Bus Interface (SRAM Interface)
The host bus interface provides a FIFO interface for the transmit and receive data paths, as well as an interface for the
LAN9215i Control and Status Registers (CSR’s).
The host bus interface is the primary bus for connection to the embedded host system. This interface models an asyn-
chronous SRAM. TX FIFO, RX FIFO, and CSR’s are accessed through this interface. Programmed I/O transactions are
supported.
The LAN9215i host bus interface supports 16-bit bus transfers. Internally, all data paths are 32-bits wide. The LAN9215i
can be interfaced to either Big-Endian or Little-Endian processors.
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1.13
External MII Interface
The LAN9215i also supports the ability to interface to an external PHY device. This interface is compatible with all IEEE
802.3 MII compliant physical layer devices. For additional information on the MII interface and associated signals,
please refer to
Section 3.11, "MII Interface - External MII Switching," on page 36
for more information.
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LAN9215i
2.0
PIN DESCRIPTION AND CONFIGURATION
FIGURE 2-1:
PIN CONFIGURATION (TOP VIEW)
**Denotes a multifunction pin
NOTE 1: When HP Auto -MDIX is activated, the TPO+/- pins function as TPI +/- and vice -versa.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
G
N
D_
CO
RE
VR
EG
V
D
D_
CO
RE
VS
S_
P
L
L
XT
A
L
2
XT
A
L
1
VD
D
_
P
L
L
VD
D
_
R
E
F
AT
ES
T
RB
IA
S
VS
S
_
R
E
F
A7
A6
A5
A4
A3
A2
A1
GN
D
_
IO
VD
D
_
IO
TX
_
E
N
RX
D
1
RX
D
2
RX
D
3
RX
_
E
R
RX
D
0
SP
EE
D
_
S
E
L
A
M
D
IX_
EN
IR
Q
NC
PM
E
EE
C
L
K*
*
EE
C
S
EE
D
IO
**
G
N
D_
CO
RE
V
D
D
_
CO
RE
D0
D1
D2
VD
D
_
IO
GN
D
_
IO
D3
D4
D5
D6
VD
D
_
IO
GN
D
_
IO
D7
D8
D9
FIFO_SEL
VSS_A
(Note 1) TPO -
(Note 1) TPO +
VSS_A
VDD_A
(Note 1) TPI -
(Note 1) TPI +
NC
VDD_A
VSS_A
EXRES1
VSS_A
VDD_A
NC
NC
nRD
nWR
nCS
nRESET
GND_IO
VDD_IO
GPIO0/nLED1**
GPIO1/nLED2**
GPIO2/nLED3**
D10
D11
VDD_IO
GND_IO
D12
D13
D14
D15
VDD_IO
GND_IO
TX_CLK
TXD0
TXD1
TXD2
TXD3
VDD_IO
GND_IO
COL
CRS
MDC
MDIO**
RX_DV
VDD_IO
GND_IO
RX_CLK
LAN9215i
100 PIN TQFP
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2.1
Pin List
TABLE 2-1:
HOST BUS INTERFACE SIGNALS
Name
Symbol
Buffer
Type
#
Pins
Description
Host Data
D[15:0]
I/O8
16
Bi-directional data port.
Host Address
A[7:1]
IS
7
7-bit Address Port. Used to select Internal CSR’s and
TX and RX FIFOs.
Read Strobe
nRD
IS
1
Active low strobe to indicate a read cycle.
Write Strobe
nWR
IS
1
Active low strobe to indicate a write cycle. This signal,
qualified with nCS, is also used to wakeup the
LAN9215i when it is in a reduced power state.
Chip Select
nCS
IS
1
Active low signal used to qualify read and write
operations. This signal qualified with nWR is also used
to wakeup the LAN9215i when it is in a reduced power
state.
Interrupt
Request
IRQ
O8/OD8
1
Programmable Interrupt request. Programmable
polarity, source and buffer types.
FIFO Select
FIFO_SEL
IS
1
When driven high all accesses to the LAN9215i are to
the RX or TX Data FIFOs. In this mode, the A[7:3]
upper address inputs are ignored.
TABLE 2-2:
DEFAULT ETHERNET SETTINGS
Default Ethernet Settings
SPEED_SEL
Speed
Duplex
Auto Neg.
0
10Mbps
Half-Duplex
Disabled
1
100Mbps
Half-Duplex
Enabled
TABLE 2-3:
LAN INTERFACE SIGNALS
Name
Symbol
Buffer
Type
# Pins
Description
TPO+
TPO+
AO
1
Transmit Positive Output (normal)
Receive Positive Input (reversed)
TPO-
TPO-
AO
1
Transmit Negative Output (normal)
Receive Negative Input (reversed)
TPI+
TPI+
AI
1
Receive Positive Input (normal)
Transmit Positive Input (reversed)
TPI-
TPI-
AI
1
Receive Negative Input (normal)
Transmit Negative Output (reversed)
PHY External Bias
Resistor
EXRES1
AI
1
Must be connected to ground through a 12.4K
ohm 1% resistor.