LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/00002266B-html.html
background image

 2005-2018 Microchip Technology Inc.

 

DS00002266B-page 1

Highlights

• Optimized for the highest data-rate applications 

such as high-definition video and multi-media 
applications

• Efficient architecture with low CPU overhead 

• Easily interfaces to most 32-bit and 16-bit embed-

ded CPU’s

• Integrated PHY

• Supports audio & video streaming over Ethernet:

multiple high-definition (HD) MPEG2 streams

• Pin compatible with other members of LAN9118 

family (LAN9117, LAN9116 and LAN9115)

Target Applications

• Video distribution systems, multi-room PVR

• High-end Cable, satellite, and IP set-top boxes

• Digital video recorders

• High definition televisions

• Digital media clients/servers

• Home gateways

Key Benefits

• Supports highest performance applications 

- Highest performing non-PCI Ethernet control-

ler in the market

- 32-bit interface with fast bus cycle times
- Burst-mode read support

• Eliminates dropped packets

- Internal buffer memory can store over 200 

packets

- Supports automatic or host-triggered PAUSE 

and back-pressure flow control

• Minimizes CPU overhead

- Supports Slave-DMA
- Interrupt Pin with Programmable Hold-off 

timer

• Reduces system cost and increases design flexi-

bility

- SRAM-like interface easily interfaces to most 

embedded CPU’s or SoC’s

- Low-cost, low--pin count non-PCI interface 

for embedded designs

• Reduced Power Modes

- Numerous power management modes
- Wake on LAN*
- Magic packet wakeup*
- Wakeup indicator event signal
- Link Status Change

• Single chip Ethernet controller

- Fully compliant with IEEE 802.3/802.3u stan-

dards

- Integrated Ethernet MAC and PHY
- 10BASE-T and 100BASE-TX support
- Full- and Half-duplex support
- Full-duplex flow control
- Backpressure for half-duplex flow control
- Preamble generation and removal
- Automatic 32-bit CRC generation and check-

ing

- Automatic payload padding and pad removal
- Loop-back modes

• Flexible address filtering modes

- One 48-bit perfect address
- 64 hash-filtered multicast addresses
- Pass all multicast
- Promiscuous mode
- Inverse filtering
- Pass all incoming with status report
- Disable reception of broadcast packets

• Integrated Ethernet PHY

- Auto-negotiation
- Automatic polarity detection and correction

• High-Performance host bus interface

- Simple, SRAM-like interface
- 32/16-bit data bus
- Large, 16Kbyte FIFO memory that can be 

allocated to RX or TX functions

- One configurable host interrupt

• Miscellaneous features

- Low profile 100-pin, TQFP RoHS Compliant 

package

- Integral 1.8V regulator
- General Purpose Timer
- Support for optional EEPROM
- Support for 3 status LEDs multiplexed with 

Programmable GPIO signals

• 3.3V Power Supply with 5V tolerant I/O

• 0 to 70

C

Third-party brands and names are the property of their 

respective owners.

LAN9118

High Performance Single-Chip 10/100 Non-PCI

Ethernet Controller

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/00002266B-html.html
background image

LAN9118

DS00002266B-page 2

 

 2005-2018 Microchip Technology Inc.

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced. 

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at 

docerrors@microchip.com

. We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. 
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for cur-
rent devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the
revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; 

http://www.microchip.com

• Your local Microchip sales office (see last page)

When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are
using.

Customer Notification System

Register on our web site at 

www.microchip.com

 to receive the most current information on all of our products.

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/00002266B-html.html
background image

 2005-2018 Microchip Technology Inc.

 

DS00002266B-page 3

LAN9118

Table of Contents

1.0 General Description  ........................................................................................................................................................................ 4
2.0 Pin Description and Configuration  .................................................................................................................................................. 8
3.0 Functional Description  .................................................................................................................................................................. 14
4.0 Internal Ethernet PHY  ................................................................................................................................................................... 46
5.0 Register Description ...................................................................................................................................................................... 53
6.0 Timing Diagrams  ........................................................................................................................................................................... 90
7.0 Operational Characteristics ......................................................................................................................................................... 100
8.0 Package Outline........................................................................................................................................................................... 104
Appendix A: Data Sheet Revision History ......................................................................................................................................... 105
The Microchip Web Site  .................................................................................................................................................................... 106
Customer Change Notification Service  ............................................................................................................................................. 106
Customer Support  ............................................................................................................................................................................. 106
Product Identification System  ........................................................................................................................................................... 107

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/00002266B-html.html
background image

LAN9118

DS00002266B-page 4

 

 2005-2018 Microchip Technology Inc.

1.0

GENERAL DESCRIPTION

The LAN9118 is a full-featured, single-chip 10/100 Ethernet controller designed for embedded applications where per-
formance, flexibility, ease of integration and system cost control are required. The LAN9118 has been specifically archi-
tected to provide the highest performance possible for any given architecture. The LAN9118 is fully IEEE 802.3
10BASE-T and 802.3u 100BASE-TX compliant.

The LAN9118 includes an integrated Ethernet MAC and PHY with a high-performance SRAM-like slave interface. The
simple, yet highly functional host bus interface provides a glue-less connection to most common 16-bit and 32-bit micro-
processors and microcontrollers. The LAN9118 includes large transmit and receive data FIFOs with a high-speed host
bus interface to accommodate high bandwidth, high latency applications. In addition, the LAN9118 memory buffer archi-
tecture allows the most efficient use of memory resources by optimizing packet granularity.

Applications

The LAN9118 is well suited for many high-performance embedded applications, including:

• High-end cable, satellite and IP set-top boxes

• Video distribution systems

• Multi-room PVR (Personal Video Recorder)

• Digital video recorders 

• High-definition televisions

• Digital media clients/servers

• Home gateways

The LAN9118 also supports features which reduce or eliminate packet loss. Its internal 16-KByte SRAM can hold over
200 received packets. If the receive FIFO gets too full, the LAN9118 can automatically generate flow control packets to
the remote node, or assert back-pressure on the remote node by generating network collisions.

The LAN9118 supports numerous power management and wakeup features. The LAN9118 can be placed in a reduced
power mode and can be programmed to issue an external wake signal via several methods, including “Magic Packet”,
“Wake on LAN” and “Link Status Change”. This signal is ideal for triggering system power-up using remote Ethernet
wakeup events. The device can be removed from the low power state via a host processor command. 

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/00002266B-html.html
background image

 2005-2018 Microchip Technology Inc.

 

DS00002266B-page 5

LAN9118

The Microchip LAN9118 integrated 10/100 MAC/PHY controller is a peripheral chip that performs the function of trans-
lating parallel data from a host controller into Ethernet packets. The LAN9118 Ethernet MAC/PHY controller is designed
and optimized to function in an embedded environment. All communication is performed with programmed I/O transac-
tions using the simple SRAM-like host interface bus.

The diagram shown above, describes a typical system configuration of the LAN9118 in a typical embedded environ-
ment.

The LAN9118 is a general purpose, platform independent, Ethernet controller. The LAN9118 consists of four major func-
tional blocks. The four blocks are:

• 10/100 Ethernet PHY

• 10/100 Ethernet MAC

• RX/TX FIFOs

• Host Bus Interface (HBI)

FIGURE 1-1:

SYSTEM BLOCK DIAGRAM UTILIZING THE MICROCHIP LAN9118

Microprocessor/

Microcontroller

LAN9118

Magnetics

Ethernet

System

Peripherals

System Memory

System Bus

EEPROM

(Optional)

LEDS/GPIO

25MHz

XTAL

System Memory

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/00002266B-html.html
background image

LAN9118

DS00002266B-page 6

 

 2005-2018 Microchip Technology Inc.

1.1

Internal Block Overview

This section provides an overview of each of these functional blocks as shown in Figure 1-2, "Internal Block Diagram".

1.2

10/100 Ethernet PHY

The LAN9118 integrates an IEEE 802.3 physical layer for twisted pair Ethernet applications. The PHY can be configured
for either 100 Mbps (100Base-TX) or 10 Mbps (10Base-T) Ethernet operation in either full or half duplex configurations.
The PHY block includes auto-negotiation.

Minimal external components are required for the utilization of the Integrated PHY.

1.3

10/100 Ethernet MAC

The transmit and receive data paths are separate within the MAC allowing the highest performance especially in full
duplex mode. The data paths connect to the PIO interface Function via separate busses to increase performance. Pay-
load data as well as transmit and receive status is passed on these busses. 

A third internal bus is used to access the MAC’s Control and Status Registers (CSR’s). This bus is accessible from the
host through the PIO interface function.

On the backend, the MAC interfaces with the internal 10/100 PHY through a the MII (Media Independent Interface) port
internal to the LAN9118. The MAC CSR's also provides a mechanism for accessing the PHY’s internal registers through
the internal SMI (Serial Management Interface) bus.

The MAC Interface Layer (MIL), within the MAC, contains a 2K Byte transmit and a 128 Byte receive FIFO which is sep-
arate from the TX and RX FIFOs. The FIFOs within the MAC are not directly accessible from the host interface. The
differentiation between the TX/RX FIFO memory buffers and the MAC buffers is that when the transmit or receive pack-
ets are in the MAC buffers, the host no longer can control or access the TX or RX data. The MAC buffers (both TX and
RX) are in effect the working buffers of the Ethernet MAC logic. In the case of reception, the data must be moved first
to the RX FIFOs for the host to access the data. For TX operations, the MIL operates in store-and-forward mode and
will queue an entire frame before beginning transmission.

FIGURE 1-2:

INTERNAL BLOCK DIAGRAM

10/100

Ethernet

PHY

10/100

Ethernet

MAC

2kB to 14kB

Configurable TX FIFO

2kB to 14kB

Configurable  RX FIFO

Interrupt

Controller

GP Timer

PIO Controller

3.3V to 1.8V

Core Regulator

25MHz

+3.3V

EEPROM
Controller

EEPROM

(Optional)

RX Status FIFO

TX Status FIFO

MIL - TX Elastic

Buffer - 2K bytes

MIL - RX Elastic

Buffer - 128 bytes

Power 

Management

IRQ

FIFO_SEL

PME

Wakup Indicator

Host Bus Interface

(HBI)

SRAM I/F

LAN

PLL

+3.3V

3.3V to 1.8V

PLL Regulator

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/00002266B-html.html
background image

 2005-2018 Microchip Technology Inc.

 

DS00002266B-page 7

LAN9118

1.4

Receive and Transmit FIFOs

The Receive and Transmit FIFOs allow increased packet buffer storage to the MAC. The FIFOs are a conduit between
the host interface and the MAC through which all transmitted and received data and status information is passed. Deep
FIFOs allow a high degree of latency tolerance relative to the various transport and OS software stacks thus reducing
or minimizing overrun conditions. Like the MAC, the FIFOs have separate receive and transmit data paths. In addition,
the RX and TX FIFOs are configurable in size, allowing increased flexibility.

1.5

Interrupt Controller

The LAN9118 supports a single programmable interrupt. The programmable nature of this interrupt allows the user the
ability to optimize performance dependent upon the application requirement. Both the polarity and buffer type of the
interrupt pin are configurable for the external interrupt processing. The interrupt line can be configured as an open-drain
output to facilitate the sharing of interrupts with other devices. In addition, a programmable interrupt de-assertion interval
is provided.

1.6

GPIO Interface

A 3-bit GPIO and 2-bit GPO (Multiplexed on the EEPROM and LED Pins) interface is included in the LAN9118. It is
accessible through the host bus interface via the CSRs. The GPIO signals can function as inputs, push-pull outputs and
open drain outputs. The GPIO’s (GPO’s are not configurable) can also be configured to trigger interrupts with program-
mable polarity.

1.7

Serial EEPROM Interface

A serial EEPROM interface is included in the LAN9118. The serial EEPROM is optional and can be programmed with
the LAN9118 MAC address. The LAN9118 can optionally load the MAC address automatically after power-on.

1.8

Power Management Controls

The LAN9118 supports comprehensive array of power management modes to allow use in power sensitive applications.
Wake on LAN, Link Status Change and Magic Packet detection are supported by the LAN9118. An external PME (Power
Management Event) interrupt is provided to indicate detection of a wakeup event.

1.9

General Purpose Timer

The general-purpose timer has no dedicated function within the LAN9118 and may be programmed to issue a timed
interrupt. 

1.10

Host Bus Interface (SRAM Interface)

The host bus interface provides a FIFO interface for the transmit and receive data paths, as well as an interface for the
LAN9118 Control and Status Registers (CSR’s). 

The host bus interface is the primary bus for connection to the embedded host system. This interface models an asyn-
chronous SRAM. TX FIFO, RX FIFO, and CSR’s are accessed through this interface. Programmed I/O transactions are
supported.

The LAN9118 host bus interface supports 32-bit and 16-bit bus transfers; internally, all data paths are 32-bits wide. The
LAN9118 can be interfaced to either Big-Endian or Little-Endian processors in either 32-bit or 16-bit external bus width
modes of operation. 

The host bus data Interface is responsible for host address decoding and data bus steering. The host bus interface han-
dles the 16 to 32-bit conversion when the LAN9118 is configured with a 16-bit host interface. Additionally, when Big
Endian mode is selected, the data path to the internal controller registers will be reorganized accordingly.

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/00002266B-html.html
background image

LAN9118

DS00002266B-page 8

 

 2005-2018 Microchip Technology Inc.

2.0

PIN DESCRIPTION AND CONFIGURATION 

FIGURE 2-1:

PIN CONFIGURATION

**Denotes a multifunction pin

*1 This NC pin can also be tied to VDD_A for backward compatibility
*2 This NC pin can also be tied to VSS_A for backward compatibility

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

D26

GND_IO

VDD_IO

D25

D24

D23

D22

D21

GND_IO

VDD_IO

D20

D19

D18

D17

D16

GND_IO

VDD_IO

D15

D14

D13

D12

GND_IO

VDD_IO

D11

D10

GPIO2/nLED3**

GPIO1/nLED2**

GPIO0/nLED1**

VDD_IO

GND_IO

nRESET

nCS

nWR

nRD

NC*1

NC*2

VDD_A

VSS_A

EXRES1

VSS_A

VDD_A

NC

TPI+

TPI-

VDD_A

VSS_A

TPO+

TPO-

VSS_A

FIFO_SEL

100 PIN TQFP

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/00002266B-html.html
background image

 2005-2018 Microchip Technology Inc.

 

DS00002266B-page 9

LAN9118

TABLE 2-1:

HOST BUS INTERFACE SIGNALS

Pin No.

Name

Symbol

Buffer 

Type

# Pins

Description

21-26,29-

33,36-40

Host Data High

D[31:16]

I/O8 (PD)

16

Bi-directional data port. 
Note that Pull-down’s are disabled in 32 
bit mode.

43-46,49-

53,56-59,62-

64

Host Data Low

D[15:0]

I/O8

16

Bi-directional data port. 

12-18

Host Address

A[7:1]

IS

7

7-bit Address Port. Used to select 
Internal CSR’s and TX and RX FIFOs.

92

Read Strobe

nRD

IS

1

Active low strobe to indicate a read 
cycle. 

93

Write Strobe

nWR

IS

1

Active low strobe to indicate a write 
cycle. This signal, qualified with nCS, is 
also used to wakeup the LAN9118 when 
it is in a reduced power state.

94

Chip Select

nCS

IS

1

Active low signal used to qualify read 
and write operations. This signal 
qualified with nWR is also used to 
wakeup the LAN9118 when it is in a 
reduced power state.

72

Interrupt 
Request

IRQ

O8/OD8

1

Programmable Interrupt request. 
Programmable polarity, source and 
buffer types.

76

FIFO Select

FIFO_SEL

IS

1

When driven high all accesses to the 
LAN9118 are to the RX or TX Data 
FIFOs. In this mode, the A[7:3] upper 
address inputs are ignored.

TABLE 2-2:

DEFAULT ETHERNET SETTINGS

 Default Ethernet Settings

SPEED_SEL

Speed

Duplex

Auto Neg.

0

10MBPS

HALF-DUPLEX

DISABLED

1

100MBPS

HALF-DUPLEX

ENABLED

TABLE 2-3:

LAN INTERFACE SIGNALS

Pin No.

Name

Symbol

Buffer 

Type

# Pins

Description

79

TXP

TPO+

AO

1

Twisted Pair Transmit Output, Positive

78

TXN

TPO-

AO

1

Twisted Pair Transmit Output, Negative

83

RXP

TPI+

AI

1

Twisted Pair Receive Input, Positive

82

RXN

TPI-

AI

1

Twisted Pair Receive Input, Negative

87

PHY External Bias 

Resistor

EXRES1

AI

1

Must be connected to ground through a 
12.4K ohm 1% resistor.

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/00002266B-html.html
background image

LAN9118

DS00002266B-page 10

 

 2005-2018 Microchip Technology Inc.

TABLE 2-4:

SERIAL EEPROM INTERFACE SIGNALS

Pin No.

Name

Symbol

Buffer 

Type

# Pins

Description

67

EEPROM Data, 

GPO3, TX_EN, 

TX_CLK, D32/nD16

EEDIO/GPO3/

TX_EN/TX_CLK

 (D32/nD16

)

I/O8

1

EEPROM Data: This bi-directional pin 
can be connected to a serial 
EEPROM DIO. This is optional.

General Purpose Output 3: This pin 
can also function as a general 
purpose output, or it can be 
configured to monitor the TX_EN or 
TX_CLK signals on the internal MII 
port. When configured as a GPO 
signal, or as a TX_EN/TX_CLK 
monitor, the EECS pin is deasserted 
so as to never unintentionally access 
the serial EEPROM. This signal 
cannot function as a general-purpose 
input.

Data Bus Width Select: This signal 
also functions as a configuration input 
on power-up and is used to select the 
host bus data width. Upon deassertion 
of reset, the value of the input is 
latched. When high, a 32-bit data bus 
is utilized. When low, a 16-bit interface 
is utilized.

68

EEPROM Chip 

Select

EECS

O8

1

Serial EEPROM chip select.

69

EEPROM Clock, 

GPO4 RX_DV, 

RX_CLK

EECLK/GPO4/

RX_DV/RX_CLK

O8

1

EEPROM Clock: Serial EEPROM 
Clock pin.

General Purpose Output 4: This pin 
can also function as a general-
purpose output, or it can be 
configured to monitor the RX_DV or 
RX_CLK signals on the internal MII 
port. When configured as a GPO 
signal, or as an RX_DV/RX_CLK 
monitor, the EECS pin is deasserted 
so as to never unintentionally access 
the serial EEPROM. This signal 
cannot function as a general-purpose 
input.

Note:

When the EEPROM inter-
face is not used, the
EECLK pin must be left
unconnected.

TABLE 2-5:

SYSTEM AND POWER SIGNALS

Pin No.

Name

Symbol

Buffer 

Type

# Pins

Description

6

Crystal 1

XTAL1

lclk

1

External 25MHz Crystal Input.
Can also be connected to single-ended 
TTL oscillator. If this method is 
implemented, XTAL2 should be left 
unconnected.

5

Crystal 2

XTAL2

Oclk

1

External 25MHz Crystal output.

Maker
Microchip Technology Inc.
Datasheet PDF Download