2009-2018 Microchip Technology Inc.
DS00001870D-page 1
Highlights
• Single-Chip Ethernet Physical Layer Transceiver
(PHY)
• Compliant with IEEE 802.3ab (1000BASE-T),
IEEE 802.3u (Fast Ethernet), and ISO 802-3/IEEE
802.3 (10BASE-T)
• HP Auto-MDIX support in accordance with IEEE
802.3ab specification at 10/100/1000 Mbps oper-
ation
• Small footprint 72-pin QFN lead-free RoHS com-
pliant package with GMII (10 x 10 x 0.9mm height)
• Flexible configurations for LED status indicators
• Implements Reduced Power Operating Modes
Target Applications
• Set-Top Boxes
• Networked Printers and Servers
• Test Instrumentation
• LAN on Motherboard
• Embedded Telecom Applications
• Video Record/Playback Systems
• Cable Modems/Routers
• DSL Modems/Routers
• Digital Video Recorders
• IP and Video Phones
• Wireless Access Points
• Digital Televisions
• Digital Media Adapters/Servers
• Gaming Consoles
• POE Applications
Key Benefits
• High-Performance 10/100/1000 Ethernet Trans-
ceiver
- Compliant with IEEE 802.3ab (1000BASE-T)
- Compliant with IEEE 802.3/802.3u (Fast
Ethernet)
- Compliant with ISO 802-3/IEEE 802.3
(10BASE-T)
- 10BASE-T, 100BASE-TX and 1000BASE-T
support
- Loop-back modes
- Auto-negotiation (NEXT page support)
- Automatic polarity detection and correction
- Link status change wake-up detection
- Vendor specific register functions
- Supports GMII interface
- Controlled impedance outputs
- Four status LED outputs and configurable
LED modes with support for tricolor operation
- Compliant with IEEE 802.3-2005 standards
- GMII pins tolerant to 3.6V
- Integrated DSP implements adaptive equal-
izer, echo cancelers, and crosstalk cancelers
- Efficient digital baseline wander correction
• Power and I/Os
- Configurable LED outputs
- Various low power modes
- Variable voltage I/O supply (2.5V/3.3V)
• Miscellaneous Features
- IEEE 1149.1 (JTAG) boundary scan
- Multiple clock options - 25MHz crystal or
25MHz single-ended clock
• Packaging
- 72-pin QFN (10x10 mm) RoHS compliant
package with GMII
• Environmental
- Commercial temperature range
(0°C to +70°C)
- Industrial temperature range (-40°C to
+85°C)
LAN8810/LAN8810i
GMII 10/100/1000 Ethernet Transceiver
with HP Auto-MDIX Support
LAN8810/LAN8810i
DS00001870D-page 2
2009-2018 Microchip Technology Inc.
TO OUR VALUED CUSTOMERS
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The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for cur-
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2009-2018 Microchip Technology Inc.
DS00001870D-page 3
LAN8810/LAN8810i
Table of Contents
1.0 Introduction ..................................................................................................................................................................................... 4
2.0 Pin Description and Configuration .................................................................................................................................................. 5
3.0 Functional Description .................................................................................................................................................................. 13
4.0 Register Descriptions .................................................................................................................................................................... 35
5.0 Operational Characteristics ........................................................................................................................................................... 60
6.0 Package Outline ............................................................................................................................................................................ 76
Appendix A: Data Sheet Revision History ........................................................................................................................................... 78
The Microchip Web Site ...................................................................................................................................................................... 81
Customer Change Notification Service ............................................................................................................................................... 81
Customer Support ............................................................................................................................................................................... 81
Product Identification System ............................................................................................................................................................. 82
LAN8810/LAN8810i
DS00001870D-page 4
2009-2018 Microchip Technology Inc.
1.0
INTRODUCTION
The LAN8810/LAN8810i is a low-power 10BASE-T/100BASE-TX/1000BASE-T Gigabit Ethernet physical layer (PHY)
transceiver with variable I/O voltage that is fully compliant with the IEEE 802.3 and 802.3ab standards.
The LAN8810/LAN8810i can be configured to communicate with an Ethernet MAC via the standard MII(IEEE 802.3u)/
GMII(IEEE 802.3z) interfaces. It contains a full-duplex transceiver for 1000 Mbps operation on four pairs of category 5
or better balanced twisted pair cable. Per IEEE 802.3-2005 standards, all digital interface pins are tolerant to 3.6V.
The LAN8810/LAN8810i is configurable via hardware and software, supporting both IEEE 802.3-2005 compliant and
vendor-specific register functions via SMI. The LAN8810/LAN8810i implements Auto-Negotiation to automatically
determine the best possible speed and duplex mode of operation. HP Auto-MDIX support allows the use of direct con-
nect or crossover cables.
An internal block diagram of the LAN8810/LAN8810i is shown in
Figure 1-1
. A typical system-level diagram is shown in
Figure 1-2
.
FIGURE 1-1:
INTERNAL BLOCK DIAGRAM
FIGURE 1-2:
SYSTEM LEVEL BLOCK DIAGRAM
LAN8810/LAN8810i
GMII
3
2
1
Active
Hybrid
0
10/100/1000
Ethernet
3
2
1
Analog
RX
0
3
2
1
Analog
TX
0
3
2
1
DSP
0
3
2
1
Spectral
Shaper
0
Digital TX
Scrambler
Trellis
4DPAM-5 Encoders
Digital RX
Descrambler
Viterbi Decoder
4DPAM-5 Decoders
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
Physical
Coding
Sublayer
TAP
Controller
LEDs
PLL
LEDs
JTAG
3
2
1
0
3
2
1
0
LAN8810/
LAN8810i
10/100/1000
Ethernet MAC
LED
Status
GMII
Crystal
MDI
Ethernet
Magnetics
JTAG
Ethernet
2009-2018 Microchip Technology Inc.
DS00001870D-page 5
LAN8810/LAN8810i
2.0
PIN DESCRIPTION AND CONFIGURATION
FIGURE 2-1:
72-QFN PIN ASSIGNMENTS (TOP VIEW)
VSS
NOTE: Exposed pad (VSS) on bottom of package must be connected to ground
LAN8810/LAN8810i
72 PIN QFN
(TOP VIEW)
TR0N
TXD1
21
22
23
24
25
26
27
28
29
30
31
32
33
34
70
69
68
67
66
65
64
63
62
61
60
59
58
57
TR0P
VDD12A
TR1N
TR1P
VDD12A
VDD12BIAS
VDD12PLL
TR2N
TR2P
VDD12A
TR3N
TR3P
TXD2
VDDVARIO
VDD12CORE
TXD3
TXD4
TXD5
TXD6
TXD7
NC
VDD12CORE
VDDVARIO
RXCLK
COL
56
55
nRESET
HPD
VDD12A
72
71
IRQ
TDI
19
20
CRS
RXER
35
36
TXEN
TXD0
LAN8810/LAN8810i
DS00001870D-page 6
2009-2018 Microchip Technology Inc.
TABLE 2-1:
GMII INTERFACE PINS
Num
Pins
Name
Symbols
Buffer
Type
Description
1
Transmit Data 0
TXD0
VIS
(PD)
The MAC transmits data to the PHY using this
signal.
1
Transmit Data 1
TXD1
VIS
(PD)
The MAC transmits data to the PHY using this
signal.
1
Transmit Data 2
TXD2
VIS
(PD)
The MAC transmits data to the PHY using this
signal.
1
Transmit Data 3
TXD3
VIS
(PD)
The MAC transmits data to the PHY using this
signal.
1
Transmit Data 4
TXD4
VIS
(PD)
The MAC transmits data to the PHY using this
signal.
1
Transmit Data 5
TXD5
VIS
(PD)
The MAC transmits data to the PHY using this
signal.
1
Transmit Data 6
TXD6
VIS
(PD)
The MAC transmits data to the PHY using this
signal.
1
Transmit Data 7
TXD7
VIS
(PD)
The MAC transmits data to the PHY using this
signal.
1
Transmit Error
TXER
VIS
(PD)
Indicates a transmit error condition.
Note:
This input is ignored during 10BASE-T
operation.
1
Transmit Enable
TXEN
VIS
(PD)
Indicates the presence of valid data on TXD[7:0]
1
Transmit Clock
TXCLK
VO8
Used to latch data from the MAC into the PHY.
MII (100BASE-TX): 25MHz
MII (10BASE-T): 2.5MHz
Note:
For 1000BASE-T operation, GTXCLK is
used as the transmit clock. TXCLK is not
used in 1000BASE-T mode.
1
GMII Transmit
Clock
GTXCLK
VIS
(PD)
125MHz clock used to latch data from the MAC into
the PHY in 1000BASE-T mode.
1
Receive Data 0
RXD0
VO6
The PHY transfers data to the MAC using this
signal.
1
Receive Data 1
RXD1
VO6
The PHY transfers data to the MAC using this
signal.
1
Receive Data 2
RXD2
VO6
The PHY transfers data to the MAC using this
signal.
1
Receive Data 3
RXD3
VO6
The PHY transfers data to the MAC using this
signal.
1
Receive Data 4
RXD4
VO6
The PHY transfers data to the MAC using this
signal.
1
Receive Data 5
RXD5
VO6
The PHY transfers data to the MAC using this
signal.
2009-2018 Microchip Technology Inc.
DS00001870D-page 7
LAN8810/LAN8810i
Note 2-1
Configuration strap values are latched on hardware reset. Configuration straps are identified by an
underlined symbol name. Signals that function as configuration straps must be augmented with an
external resistor when connected to a load. Refer to
Section 3.8, "Configuration," on page 22
for
additional information.
1
Receive Data 6
RXD6
VO6
The PHY transfers data to the MAC using this
signal.
1
Receive Data 7
RXD7
VO6
The PHY transfers data to the MAC using this
signal.
1
Receive Data
Valid
RXDV
VO6
Indicates that recovered and decoded data is being
presented on the receive data pins.
1
Receive Error
RXER
VO6
Asserted to indicate an error has been detected in
the frame presently being transferred from the
PHY.
1
Receive Clock
RXCLK
VO6
Used to transfer data to the MAC.
GMII (1000BASE-T): 125 MHz
MII (100BASE-TX): 25 MHz
MII (10BASE-T): 2.5 MHz
1
Collision Detect
COL
VO6
Asserted to indicate detection of a collision
condition. (used in half-duplex mode only)
1
Carrier Sense
CRS
VO6
Indicates detection of carrier. (used in half-duplex
mode only)
TABLE 2-2:
SERIAL MANAGEMENT INTERFACE (SMI) PINS
Num
Pins
Name
Symbols
Buffer
Type
Description
1
SMI Clock
MDC
VIS
(PD)
Serial Management Interface clock.
1
SMI Data Input/
Output
MDIO
VIS/VO8
(PU)
Serial Management Interface data input/output.
TABLE 2-1:
GMII INTERFACE PINS (CONTINUED)
Num
Pins
Name
Symbols
Buffer
Type
Description
LAN8810/LAN8810i
DS00001870D-page 8
2009-2018 Microchip Technology Inc.
Note 2-2
Configuration strap values are latched on hardware reset. Configuration straps are identified by an
underlined symbol name. Signals that function as configuration straps must be augmented with an
external resistor when connected to a load. Refer to
Section 3.8, "Configuration," on page 22
for
additional information.
TABLE 2-3:
LED & CONFIGURATION PINS
Num
Pins
Name
Symbols
Buffer
Type
Description
1
10BASE-T Link
LED Indicator
10_LED
VO8
10BASE-T LED link indication. Refer to
Section
3.9.1, "LEDs," on page 26
for additional
information.
1
100BASE-TX
Link LED
Indicator
100_LED
VO8
100BASE-TX LED link indication. Refer to
Section
3.9.1, "LEDs," on page 26
for additional
information.
Hardware
Power Down
(HPD) Mode
Configuration
Strap
HPD_MODE
VIS
(PD)
This configuration strap is used to select the
Hardware Power Down (HPD) mode. When pulled-
up, the PLL is not disabled when HPD is asserted.
When pulled-down, the PLL is disabled when HPD
is asserted.
Refer to
Section 3.7.3, "Hardware Power-Down,"
on page 22
for additional information.
See
Note 2-2
for more information on configuration
straps.
1
1000BASE-T
Link LED
Indicator
1000_LED
VO8
1000BASE-T LED link indication. Refer to
Section
3.9.1, "LEDs," on page 26
for additional
information.
1
Link Activity
LED Indicator
ACT_LED
VO8
Link activity LED indication. Refer to
Section 3.9.1,
"LEDs," on page 26
for additional information.
1
Configuration
Input 0
CONFIG0
VIS
(PD)
This pin sets the PHYADD[1:0] bits of the
10/100
Special Modes Register
on reset or power-up. It
must be connected to VSS, 100_LED, 1000_LED,
or VDDVARIO. Refer to
Section 3.8.1.2,
"CONFIG[3:0] Configuration Pins," on page 23
for
additional information.
1
Configuration
Input 1
CONFIG1
VIS
(PD)
This pin sets the PAUSE bit of the
Auto Negotiation
Advertisement Register
and PHYADD [2] bit of the
10/100 Special Modes Register
on reset or power-
up. It must be connected to VSS, 100_LED,
1000_LED, or VDDVARIO. Refer to
Section
3.8.1.2, "CONFIG[3:0] Configuration Pins," on
page 23
for additional information.
1
Configuration
Input 2
CONFIG2
VIS
(PD)
This pin sets the MOD[1:0] bits of the
Extended
Mode Control/Status Register
on reset or power-
up. It must be connected to VSS, 100_LED,
1000_LED, or VDDVARIO. Refer to
Section
3.8.1.2, "CONFIG[3:0] Configuration Pins," on
page 23
for additional information.
1
Configuration
Input 3
CONFIG3
VIS
(PD)
This pin sets the MOD[3] bit of the
Extended Mode
Control/Status Register
on reset or power-up. It
must be connected to 1000_LED or VDDVARIO.
Refer to
Section 3.8.1.2, "CONFIG[3:0]
Configuration Pins," on page 23
for additional
information.
2009-2018 Microchip Technology Inc.
DS00001870D-page 9
LAN8810/LAN8810i
TABLE 2-4:
ETHERNET PINS
Num Pins
Name
Symbol
Buffer
Type
Description
1
Ethernet TX/
RX Positive
Channel 0
TR0P
AIO
Transmit/Receive Positive Channel 0.
1
Ethernet TX/
RX Negative
Channel 0
TR0N
AIO
Transmit/Receive Negative Channel 0.
1
Ethernet TX/
RX Positive
Channel 1
TR1P
AIO
Transmit/Receive Positive Channel 1.
1
Ethernet TX/
RX Negative
Channel 1
TR1N
AIO
Transmit/Receive Negative Channel 1.
1
Ethernet TX/
RX Positive
Channel 2
TR2P
AIO
Transmit/Receive Positive Channel 2.
1
Ethernet TX/
RX Negative
Channel 2
TR2N
AIO
Transmit/Receive Negative Channel 2.
1
Ethernet TX/
RX Positive
Channel 3
TR3P
AIO
Transmit/Receive Positive Channel 3.
1
Ethernet TX/
RX Negative
Channel 3
TR3N
AIO
Transmit/Receive Negative Channel 3.
1
External PHY
Bias Resistor
ETHRBIAS
AI
Used for the internal bias circuits. Connect to an
external 8.06K 1.0% resistor to ground.
TABLE 2-5:
JTAG PINS
Num Pins
Name
Symbol
Buffer
Type
Description
1
JTAG Test
Data Out
TDO
VO8
JTAG (IEEE 1149.1) data output.
1
JTAG Test
Data Input
TDI
VIS
(PU)
JTAG (IEEE 1149.1) data input.
Note:
When not used, tie this pin to
VDDVARIO.
1
JTAG Test
Clock
TCK
VIS
(PD)
JTAG (IEEE 1149.1) test clock.
Note:
When not used, tie this pin to VSS.
1
JTAG Test
Mode Select
TMS
VIS
(PU)
JTAG (IEEE 1149.1) test mode select.
Note:
When not used, tie this pin to
VDDVARIO.
LAN8810/LAN8810i
DS00001870D-page 10
2009-2018 Microchip Technology Inc.
Note 2-3
Exposed pad on package bottom (
Figure 2-1
).
TABLE 2-6:
MISCELLANEOUS PINS
Num Pins
Name
Symbol
Buffer
Type
Description
1
Crystal Input
XI
ICLK
External 25 MHz crystal input.
Note:
This pin can also be driven by a 25 MHz
single-ended clock oscillator. When this
method is used, XO should be left
unconnected. Refer to
Section 5.6,
"Clock Circuit," on page 75
for additional
information.
1
Crystal
Output
XO
OCLK
External 25 MHz crystal output.
1
System Reset
nRESET
VIS
(PU)
This active-low pin allows external hardware to
reset the device.
1
Interrupt
Request
IRQ
VO8
Programmable interrupt request.
Note:
When used, this pin requires an
external 4.7K pull-up resistor.
1
Hardware
Power Down
HPD
VIS
(PD)
When asserted, this pin places the device into
Hardware Power Down (HPD) mode. Refer to
Section 3.7.3, "Hardware Power-Down," on
page 22
for additional information.
1
No Connect
NC
-
This pin must be left floating for normal device
operation.
TABLE 2-7:
POWER PINS
Num Pins
Name
Symbol
Buffer
Type
Description
6
+3.3V/+2.5V
I/O Power
Supply Input
VDDVARIO
P
+2.5V/+3.3V variable I/O power.
Refer to
Section 3.10, "Application Diagrams," on
page 33
and the LAN8810/LAN8810i reference
schematics for connection information.
6
Digital Core
+1.2V Power
Supply Input
VDD12CORE
P
Refer to
Section 3.10, "Application Diagrams," on
page 33
and the LAN8810/LAN8810i reference
schematics for connection information.
4
Ethernet
+1.2V Port
Power Supply
Input For
Channels 0-3
VDD12A
P
Refer to
Section 3.10, "Application Diagrams," on
page 33
and the LAN8810/LAN8810i reference
schematics for connection information.
1
Ethernet
+1.2V Bias
Power Supply
Input
VDD12BIAS
P
Refer to
Section 3.10, "Application Diagrams," on
page 33
and the LAN8810/LAN8810i reference
schematics for connection information.
1
Ethernet PLL
+1.2V Power
Supply Input
VDD12PLL
P
Refer to
Section 3.10, "Application Diagrams," on
page 33
and the LAN8810/LAN8810i reference
schematics for connection information.
Note 2-3
Ground
VSS
P
Common Ground