2017 Microchip Technology Inc.
DS00002436B-page 1
Features
• Single-Chip 10BASE-T/100BASE-TX/100BASE-
FX Physical Layer Solution
• Fully Compliant with IEEE 802.3u Standard
• Low Power CMOS Design, Power Consumption
of <180 mW
• HP Auto MDI/MDI-X for Reliable Detection and
Correction for Straight-Through and Crossover
Cables with Disable and Enable Option
• Robust Operation Over Standard Cables
• LinkMD
®
TDR-Based Cable Diagnostics for Iden-
tification of Faulty Copper Cabling
• Power Down and Power Saving Modes
• Fiber Support: 100BASE-FX (KSZ8041FTL Only)
• Back-to-Back Mode Support for 100 Mbps
Repeater or Media Converter
• MII Interface Support
• RMII Interface Support with External 50 MHz Sys-
tem Clock (KSZ8041TL/FTL Only)
• SMII Interface Support with External 125 MHz
System Clock and 12.5 MHz Sync Clock from
MAC (KSZ8041TL/FTL Only)
• MIIM (MDC/MDIO) Management Bus to 12.5 MHz
for Rapid PHY Register Configuration
• Interrupt Pin Option
• Programmable LED Outputs for Link, Activity, and
Speed
• Single Power Supply (3.3V)
• Built-in 1.8V Regulator for Core
• Available in 48-Pin LQFP (KSZ8041MLL) or 48-
Pin TQFP (KSZ8041TL/FTL) Packages
Applications
• Printer
• LOM
• Game Console
• IPTV
• IP Phone
• IP Set-Top Box
• Media Converter
KSZ8041TL/FTL/MLL
10BASE-T/100BASE-TX/100BASE-FX
Physical Layer Transceiver
KSZ8041TL/FTL/MLL
DS00002436B-page 2
2017 Microchip Technology Inc.
TO OUR VALUED CUSTOMERS
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The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
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2017 Microchip Technology Inc.
DS00002436B-page 3
KSZ8041TL/FTL/MLL
Table of Contents
1.0 Introduction ..................................................................................................................................................................................... 4
2.0 Pin Description and Configuration .................................................................................................................................................. 6
3.0 Functional Description .................................................................................................................................................................. 19
4.0 Register Descriptions .................................................................................................................................................................... 35
5.0 Operational Characteristics ........................................................................................................................................................... 42
6.0 Electrical Characteristics ............................................................................................................................................................... 43
7.0 Timing Specifications .................................................................................................................................................................... 44
8.0 Selection of Isolation Transformers .............................................................................................................................................. 56
9.0 Package Outline ............................................................................................................................................................................ 57
Appendix A: Data Sheet Revision History ........................................................................................................................................... 59
The Microchip Web Site ...................................................................................................................................................................... 60
Customer Change Notification Service ............................................................................................................................................... 60
Customer Support ............................................................................................................................................................................... 60
Product Identification System ............................................................................................................................................................. 61
KSZ8041TL/FTL/MLL
DS00002436B-page 4
2017 Microchip Technology Inc.
1.0
INTRODUCTION
1.1
General Description
The KSZ8041TL is a single supply 10BASE-T/100BASE-TX Physical Layer Transceiver that provides MII/RMII/SMII
interfaces to transmit and receive data. It utilizes a unique mixed-signal design to extend signaling distance while reduc-
ing power consumption.
HP Auto MDI/MDI-X provides the most robust solution for eliminating the need to differentiate between crossover and
straight-through cables.
LinkMD
®
TDR-based cable diagnostics permit identification of faulty copper cabling.
The KSZ8041TL represents a new level of features and performance and is an ideal choice of physical layer transceiver
for 10BASE-T/100BASE-TX applications.
The KSZ8041FTL has all the identical rich features of the KSZ8041TL plus 100BASE-FX support for fiber and media
converter applications.
The KSZ8041MLL is the basic 10BASE-T/100BASE-TX physical layer transceiver version with MII support.
The KSZ8041TL and KSZ8041FTL are available in 48-pin, lead-free TQFP packages. The KSZ8041MLL is provided in
the 48-pin, lead-free LQFP package.
FIGURE 1-1:
SYSTEM BLOCK DIAGRAM, KSZ8041TL/FTL
10/100
Pulse
Shaper
NRZ/NRZI
MLT3 Encoder
Parallel /Serial
Manchester Encoder
4B/5B Encoder
Scrambler
Parallel /Serial
Transmitter
TX+
TX-
Adaptive EQ
Base Line
Wander Correction
MLT3 Decoder
NRZI/NRZ
Clock
Recovery
4B/5B Decoder
Descrambler
Serial/Parallel
Auto
Negotiation
10BASE-T
Receiver
Manchester Decoder
Serial/Parallel
PLL
LED
Driver
MII/RMII/SMII
Registers
and
Controller
Interface
RX-
RX+
XI
XO
LED1
LED0
Power Down
Power Saving
TXD3
TXD0
TXD1
TXD2
RXD3
TXEN
TXC
MDC
MDIO
RXER
RXD0
RXD1
RXD2
REXT
RXC
RXDV
CRS
COL
RST#
INTRP
100BASE-FX
Signal Detect
(KSZ8041FTL Only)
FXSD/
FXEN
2017 Microchip Technology Inc.
DS00002436B-page 5
KSZ8041TL/FTL/MLL
FIGURE 1-2:
SYSTEM BLOCK DIAGRAM, KSZ8041MLL
10/100
Pulse
Shaper
NRZ/NRZI
MLT3 Encoder
Parallel /Serial
Manchester Encoder
4B/5B Encoder
Scrambler
Parallel /Serial
Transmitter
TX+
TX-
Adaptive EQ
Base Line
Wander Correction
MLT3 Decoder
NRZI/NRZ
Clock
Recovery
4B/5B Decoder
Descrambler
Serial/Parallel
Auto
Negotiation
10BASE-T
Receiver
Manchester Decoder
Serial/Parallel
PLL
LED
Driver
MII
RX-
RX+
XI
XO
LED1
LED0
Power Down
Power Saving
TXD3
TXD0
TXD1
TXD2
RXD3
TXEN
TXC
MDC
MDIO
RXER
RXD0
RXD1
RXD2
REXT
RXC
RXDV
CRS
COL
RST#
INTRP
KSZ8041TL/FTL/MLL
DS00002436B-page 6
2017 Microchip Technology Inc.
2.0
PIN DESCRIPTION AND CONFIGURATION
FIGURE 2-1:
KSZ8041TL 48-PIN TQFP ASSIGNMENT, (TOP VIEW)
1
NC
NC
TXC
RST#
INTRP
REXT
GND
RXER / RX_ER /
ISO
GND
VDD_1.8
GND
GND
GND
GND
XO
VDDA_3.3
NC
TXD1 / TXD[1] /
SYNC
TXD0 / TXD[0] /
TX
TXEN /
TX_EN
LED1 /
SPEED
LED0
/
NWA
YEN
CR
S /
CONFIG1
NC
2
3
8
13
14
16
17
29
30
31
32
33
34
35
36
41
42
43
44
45
46
47
48
RX+
TX-
RX-
9
10
11
GND
24
TXD3
TXD2
GND
CO
L /
CONFIG0
37
38
39
40
RXC
VDDIO_3.3
VDDIO_3.3
RXDV / CRSDV /
CONFIG2
25
26
27
28
R
X
D2 /
PHYAD1
R
X
D1 / R
X
D
[1] /
PHYAD2
RXD
0
/ RXD[0
] / RX
DUPLEX
21
22
23
MDIO
MD
C
RXD3
/
PHYAD0
18
19
20
XI /
REFCL
K /
CLOCK
15
TX+
12
VDDA_1.8
VDDA_1.8
4
5
V1.8_OUT
VDDA_3.3
6
7
KSZ8041TL
2017 Microchip Technology Inc.
DS00002436B-page 7
KSZ8041TL/FTL/MLL
FIGURE 2-2:
KSZ8041FTL 48-PIN TQFP ASSIGNMENT, (TOP VIEW)
1
NC
NC
TXC
RST#
INTRP
REXT
GND
RXER / RX_ER /
ISO
GND
VDD_1.8
GND
GND
GND
GND
XO
VDDA_3.3
FXSD /
FXEN
TXD1 / TXD[1] /
SYNC
TXD0 / TXD[0] /
TX
TXEN /
TX_EN
LED1 /
SPEED / no FEF
LED0
/
NWA
YEN
CR
S /
CONFIG1
NC
2
3
8
13
14
16
17
29
30
31
32
33
34
35
36
41
42
43
44
45
46
47
48
RX+
TX-
RX-
9
10
11
GND
24
TXD3
TXD2
GND
CO
L /
CONFIG0
37
38
39
40
RXC
VDDIO_3.3
VDDIO_3.3
RXDV / CRSDV /
CONFIG2
25
26
27
28
R
X
D2 /
PHYAD1
R
X
D1 / R
X
D
[1] /
PHYAD2
RXD
0
/ RXD[0
] / RX
DUPLEX
21
22
23
MDIO
MD
C
RXD3
/
PHYAD0
18
19
20
XI /
REFCL
K /
CLOCK
15
TX+
12
VDDA_1.8
VDDA_1.8
4
5
V1.8_OUT
VDDA_3.3
6
7
KSZ8041FTL
KSZ8041TL/FTL/MLL
DS00002436B-page 8
2017 Microchip Technology Inc.
TABLE 2-1:
SIGNALS FOR KSZ8041TL/FTL
Pin
Number
Pin Name
Type
(
Note
2-1
)
Description
1
GND
GND
Ground
2
GND
GND
Ground
3
GND
GND
Ground
4
VDDA_1.8
P
1.8V analog V
DD
5
VDDA_1.8
P
1.8V analog V
DD
6
V1.8_OUT
P
1.8V output voltage from chip
7
VDDA_3.3
P
3.3V analog V
DD
8
VDDA_3.3
P
3.3V analog V
DD
9
RX–
I/O
Physical receive or transmit signal (– differential)
10
RX+
I/O
Physical receive or transmit signal (+ differential)
11
TX–
I/O
Physical transmit or receive signal (– differential)
12
TX+
I/O
Physical transmit or receive signal (+ differential)
13
GND
GND
Ground
14
XO
O
Crystal feedback
This pin is used only in MII mode when a 25 MHz crystal is used.
This pin is a no connect if oscillator or external clock source is used, or if RMII
mode or SMII mode is selected.
15
XI/REFCLK/
CLOCK
I
Crystal/Oscillator/External Clock Input
MII Mode: 25 MHz ±50 ppm (crystal, oscillator, or external clock)
RMII Mode: 50 MHz ±50 ppm (oscillator, or external clock only)
SMII Mode: 125 MHz ±100 ppm (oscillator, or external clock only)
16
REXT
I/O
Set physical transmit output current
Connect a 6.49 kΩ resistor in parallel with a 100 pF capacitor to ground on
this pin. See KSZ8041TL-FTL reference schematics.
17
GND
GND
Ground
18
MDIO
I/O
Management Interface (MII) Data I/O
This pin requires an external 4.7 kΩ pull-up resistor.
19
MDC
I
Management Interface (MII) Clock Input
This pin is synchronous to the MDIO data interface.
20
RXD3/
PHYAD0
Ipu/O
MII Mode: Receive Data Output[3](
Note 2-2
)
Config. Mode: The pull-up/pull-down value is latched as PHYADDR[0] during
power-up/reset. See
Table 2-2
for details.
21
RXD2/
PHYAD1
Ipd/O
MII Mode: Receive Data Output[2](
Note 2-2
)
Config. Mode: The pull-up/pull-down value is latched as PHYADDR[1] during
power-up/reset. See
Table 2-2
for details.
2017 Microchip Technology Inc.
DS00002436B-page 9
KSZ8041TL/FTL/MLL
22
RXD1/
RXD[1]/
PHYAD2
Ipd/O
MII Mode: Receive Data Output[1](
Note 2-2
)
RMII Mode: Receive Data Output[1](
Note 2-3
)
Config. Mode: The pull-up/pull-down value is latched as PHYADDR[2] during
power-up/reset. See
Table 2-2
for details.
23
RXD0/
RXD[0]/
RX
DUPLEX
Ipu/O
MII Mode: Receive Data Output[0](
Note 2-2
)
RMII Mode: Receive Data Output[0](
Note 2-3
)
SMII Mode: Receive Data and Control(
Note 2-4
)
Config. Mode: Latched as DUPLEX (register 0h, bit 8) during power-up/reset.
See
Table 2-2
for details.
24
GND
GND
Ground
25
VDDIO_3.3
P
3.3V digital V
DD
26
VDDIO_3.3
P
3.3V digital V
DD
27
RXDV/
CRSDV/
CONFIG2
Ipd/O
MII Mode: Receive Data Valid Output
RMII Mode: Carrier Sense/Receive Data Valid Output
Config. Mode: The pull-up/pull-down value is latched as CONFIG2 during
power-up/reset. See
Table 2-2
for details.
28
RXC
O
MII Mode: Receive Clock Output.
29
RXER/
RX_ER/
ISO
Ipd/O
MII Mode: Receive Error Output
RMII Mode: Receive Error Output
Config. Mode: The pull-up/pull-down value is latched as ISOLATE during
power-up/reset. See
Table 2-2
for details.
30
GND
GND
Ground
31
VDD_1.8
P
1.8V digital V
DD
32
INTRP
Opu
Interrupt Output: Programmable Interrupt Output
Register 1Bh is the Interrupt Control/Status Register for programming the
interrupt conditions and reading the interrupt status. Register 1Fh bit 9 sets
the interrupt output to active-low (default) or active-high.
33
TXC
I/O
MII Mode: Transmit Clock Output
MII Back-to-Back Mode: Transmit Clock Input
34
TXEN/
TX_EN
I
MII Mode: Transmit Enable Input
RMII Mode: Transmit Enable Input
35
TXD0/
TXD[0]/
TX
I
MII Mode: Transmit Data Input[0](
Note 2-5
)
RMII Mode: Transmit Data Input[0](
Note 2-6
)
SMII Mode: Transmit Data and Control(
Note 2-7
)
36
TXD1/
TXD[1]/
SYNC
I
MII Mode: Transmit Data Input[1](
Note 2-5
)
RMII Mode: Transmit Data Input[1](
Note 2-6
)
SMII Mode: SYNC Clock Input
37
GND
GND
Ground
38
TXD2
I
MII Mode: Transmit Data Input[2](
Note 2-5
)
39
TXD3
I
MII Mode: Transmit Data Input[3](
Note 2-5
)
TABLE 2-1:
SIGNALS FOR KSZ8041TL/FTL (CONTINUED)
Pin
Number
Pin Name
Type
(
Note
2-1
)
Description
KSZ8041TL/FTL/MLL
DS00002436B-page 10
2017 Microchip Technology Inc.
40
COL/
CONFIG0
Ipd/O
MII Mode: Collision Detect Output
Config. Mode: The pull-up/pull-down value is latched as CONFIG0 during
power-up/reset. See
Table 2-2
for details.
41
CRS/
CONFIG1
Ipd/O
MII Mode: Carrier Sense Output
Config. Mode: The pull-up/pull-down value is latched as CONFIG1 during
power-up/reset. See
Table 2-2
for details.
42
(TL)
LED0/
NWAYEN
Ipu/O
LED Output: Programmable LED0 Output
Config. Mode: Latched as Auto-Negotiation Enable (register 0h, bit 12) during
power-up/reset. See
Table 2-2
for details.
The LED0 pin is programmable via register 1Eh bits [15:14], and is defined as
follows:
LED Mode = [00]
Link/Activity
Pin State
LED Definition
No Link
High
OFF
Link
Low
ON
Activity
Toggle
Blinking
LED Mode = [01]
Link
Pin State
LED Definition
No Link
High
OFF
Link
Low
ON
LED Mode = [10]:
Reserved
LED Mode = [11]:
Reserved
TABLE 2-1:
SIGNALS FOR KSZ8041TL/FTL (CONTINUED)
Pin
Number
Pin Name
Type
(
Note
2-1
)
Description