DS00002129C-page 1
2015 Microchip Technology Inc.
Features
• Management Capabilities
- The KSZ8775CLX includes all the functions
of a 10/100BASE-T/TX switch system, which
combines a switch engine, frame buffer
management, address look-up table, queue
management, MIB counters, media access
controllers (MAC), and PHY transceivers
- Non-blocking store-and-forward switch fabric
assures fast packet delivery by utilizing a
1024-entry forwarding table
- Port mirroring/monitoring/sniffing: ingress
and/or egress traffic to any port
- MIB counters for fully compliant statistics
gathering - 36 counters per port
- Hardware support for port-based flush and
freeze command in MIB counter.
- Multiple loopback of remote, PHY, and MAC
modes support for the diagnostics
- Rapid spanning tree support (RSTP) for
topology management and ring/linear
recovery
• Robust PHY Ports
- Four integrated IEEE 802.3/802.3u-compliant
Ethernet transceivers supporting 10Base-T
and 100BASE-TX
- 802.1az EEE supported
- On-chip termination resistors and internal
biasing for differential pairs to reduce power
- HP Auto MDI/MDI-X™ crossover support
eliminates the need to differentiate between
straight or crossover cables in applications
• MAC and GMAC Ports
- Four internal media access control (MAC1 to
MAC4) units and one internal Gigabit media
access control (GMAC5) unit
- RGMII, MII, or RMII interfaces support for the
Port 5 GMAC5 with uplink and RMII interface
for Port 4 MAC4
- 2 kb jumbo packet support
- Tail tagging mode (one byte added before
FCS) support on Port 5 to inform the
processor which ingress port receives the
packet and its priority
- Supports reduced media independent inter-
face (RMII) with 50 MHz reference clock out-
put
- Supports media independent interface (MII)
in either PHY mode or MAC mode on Port 5
- LinkMD
®
cable diagnostic capabilities for
determining cable opens, shorts, and length
• Advanced Switch Capabilities
- Non-blocking store-and-forward switch fabric
assures fast packet delivery by utilizing a
1024-entry forwarding table
- 64kb frame buffer RAM
- IEEE 802.1q VLAN support for up to 128
active VLAN groups (full-range 4096 of VLAN
IDs)
- IEEE 802.1p/q tag insertion or removal on a
per port basis (egress)
- VLAN ID tag/untag options on per port basis
- Fully compliant with IEEE 802.3/802.3u stan-
dards
- IEEE 802.3x full-duplex with force mode
option and half-duplex back-pressure colli-
sion flow control
- IEEE 802.1w rapid spanning tree protocol
support
- IGMP v1/v2/v3 snooping for multicast packet
filtering
- QoS/CoS packets prioritization support:
802.1p, DiffServ-based and re-mapping of
802.1p priority field per port basis on four
priority levels
- IPv4/IPv6 QoS support
- IPv6 multicast listener discovery (MLD)
snooping
- Programmable rate limiting at the ingress and
egress ports on a per port basis
- Jitter-free per-packet-based rate limiting
support
- Tail tagging mode (one byte added before
FCS) support on Port 5 to inform the proces-
sor which ingress port receives the packet
and its priority
- Broadcast storm protection with percentage
control (global and per port basis)
KSZ8775CLX
Integrated 5–Port 10/100 Managed Ethernet
Switch with Port 4 RMII and Port 5 RGMII/MII/
RMII Interfaces
KSZ8775CLX
2015 Microchip Technology Inc.
DS00002129C-page 2
- 1 kb entry forwarding table with 64 kb frame
buffer
- Four priority queues with dynamic packet
mapping for IEEE 802.1p, IPv4 ToS (DIFF-
SERV), IPv6 traffic class, etc.
- Supports Wake-on-LAN (WoL) using AMD’s
Magic Packet™
- VLAN and address filtering
- Supports 802.1x port-based security, authen-
tication, and MAC-based authentication via
access control lists (ACL)
- Provides port-based and rule-based ACLs to
support Layer 2 MAC SA/DA address, Layer
3 IP address and IP mask, Layer 4 TCP/UDP
port number, IP protocol, TCP flag, and com-
pensation for the port security filtering
- Ingress and egress rate limit based on bit per
second (bps) and packet-based rate limiting
(pps)
• Configuration Registers Access
- High speed (4-wire, up to 50 MHz) interface
(SPI) to access all internal registers
- MII management interface (MIIM, MDC/
MDIO 2-wire) to access all PHY registers per
clause 22.2.4.5 of the IEEE 802.3 specifica-
tion
- I/O pin strapping facility to set certain register
bits from I/O pins during reset time
- Control registers configurable on-the-fly
• Power and Power Management
- Full-chip software power down (all registers
value are not saved and strap-in value will re-
strap after release of the power down)
- Per-port software power down
- Energy detect power down (EDPD), which
disables the PHY transceiver when cables
are removed
- Supports IEEE P802.3az Energy Efficient
Ethernet to reduce power consumption in
transceivers in LPI state even though cables
are not removed
- Dynamic clock tree control to reduce clocking
in areas not in use
- Low power consumption without extra power
consumption on transformers
- Voltages: Using external LDO power sup-
plies.
- Analog VDDAT 3.3V
- VDDIO support
- s 3.3V, 2.5V, and 1.8V
- Low 1.2V voltage for analog and digital core
power
- Wake-on-LAN support with configurable
packet control
• Additional Features
- Single 25 MHz +50 ppm reference clock
requirement
• Comprehensive programmable two LED indicator
support for link, activity, full/half-duplex, and 10/
100 speed
• Packaging and Environmental
- Commercial temperature range: 0°C to
+70°C
• Industrial temperature range: –40°C to +85°C
- Package available in an 80-pin lead free
(RoHS) LQFP form factor
- Supports HBM ESD rating of 5 kV
- 0.065 µm CMOS technology for lower power
consumption
• Applications
- Set-Top Boxes
- Networked Printers and Servers
- Test Instrumentation
- LAN on Motherboard
- Embedded Telecom Applications
- Video Record/Playback Systems
- Cable Modems/Routers
- DSL Modems/Routers
- Digital Video Recorders
- IP and Video Phones
- Wireless Access Points
- Digital Televisions
- Digital Media Adapters/Servers
- Gaming Consoles
2015 Microchip Technology Inc.
DS00002129C-page 3
KSZ8775CLX
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at
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. We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for cur-
rent devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the
revision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are
using.
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KSZ8775CLX
DS00002129C-page 4
2015 Microchip Technology Inc.
Table of Contents
1.0 Introduction ..................................................................................................................................................................................... 5
2.0 Pin Description and Configuration ................................................................................................................................................... 6
3.0 Functional Description ................................................................................................................................................................... 16
4.0 Register Descriptions .................................................................................................................................................................... 49
5.0 Operational Characteristics ......................................................................................................................................................... 114
6.0 Electrical Characteristics ............................................................................................................................................................. 115
7.0 Package Outline .......................................................................................................................................................................... 117
Appendix A: Data Sheet Revision History ......................................................................................................................................... 126
The Microchip Web Site .................................................................................................................................................................... 128
Customer Change Notification Service ............................................................................................................................................. 129
Customer Support ............................................................................................................................................................................. 129
Product Identification System ............................................................................................................................................................ 130
2015 Microchip Technology Inc.
DS00002129C-page 5
KSZ8775CLX
1.0
INTRODUCTION
1.1
General Description
The KSZ8775CLX is a highly integrated, Layer 2-managed, five-port switch with numerous features designed to reduce
system cost. It is intended for cost-sensitive applications requiring three 10/100 Mbps copper ports, one RMII on Port
4, and one 10/100/1000Mbps Gigabit uplink port on Port 5. The KSZ8775CLX incorporates a small package outline, the
lowest power consumption with internal biasing, and on-chip termination. Its extensive set of features include enhanced
power management, programmable rate limiting and priority ratio, tagged and port-based VLAN, port-based security
and ACL rule-based packet filtering technology, QoS priority with four queues, management interfaces, enhanced MIB
counters, high-performance memory bandwidth, and a shared memory-based switch fabric with non-blocking support.
The KSZ8775CLX provides support for multiple CPU data interfaces to effectively address both current and emerging
fast Ethernet and Gigabit Ethernet applications where the Port 5 GMAC can be configured to any of the RGMII, MII, and
RMII modes.
The KSZ8775CLX product is built upon industry-leading analog and digital technology, with features designed to offload
host processing and streamline the overall design.
• Three integrated 10/100BASE-T/TX MAC/PHYs
• One integrated 10/100BASE-T/TX MAC with RMII interface
• One integrated 10/100/1000Base-T/TX GMAC with selectable RGMII, MII, and RMII interfaces
• Small 80-pin LQFP package
A robust assortment of power management features including Energy Efficient Ethernet (EEE), power management
event (PME), and Wake-on-LAN (WoL) have been designed in to satisfy energy efficient environments.
All registers in the MAC/PHY units can be managed through the SPI interface. MIIM PHY registers can be accessed
through the MDC/MDIO interface.
FIGURE 1-1:
BLOCK DIAGRAM
KSZ8775CLX
DS00002129C-page 6
2015 Microchip Technology Inc.
2.0
PIN DESCRIPTION AND CONFIGURATION
FIGURE 2-1:
80-QFN PIN ASSIGNMENT (TOP VIEW)
TABLE 2-1:
SIGNALS
Num Pins
Pin Name
Type
Port
Pin Description
1
NC
NC
No connect
2
NC
NC
No connect
3
VDD12A
P
1.2V core power
4
VDDAT
P
3.3V or 2.5V analog power
5
GNDA
GND
Analog ground
XO
XI
GNDA
ISET
VDDA
T33
AT
S
T
VDD12D
RST_N
GNDD
VDDIO
SPIS_N
SDA_MDIO
SCL_MDC
SPIQ
LED1_0
LED1_1
LED2_0
LED2_1
TXEN4
GNDD
GNDA
INTR_N
NC
TXD4_1
LED3_1
TXD4_0
LED3_0
VDD12D
GNDD
TXC4/REFCLKI4
RXC4
TXEN5/TXD5_CTL
TXD5_0
TXD5_1
GNDD
VDDIO
TXD5_2
TXD5_3
TXER5
NC
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PME
REFCLKO
COL5
CRS5
RXER5
RXDV5/CRSDV5/RXD5_CTL
RXD5_3
RXD5_2
VDDIO
GNDD
RXD5_1
RXD5_0
RXC5/GRXC5
TXC5/REFCLKI5/GTXC5
VDD12D
NC
RXDV4/CRSDV4
RXD4_0
RXD4_1
GNDD
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
NC
NC
VDD12A
VDDAT33
GNDA
RXP1
RXM1
TXP1
TXM1
RXP2
RXM2
TXP2
TXM2
VDDAT33
RXP3
RXM3
TXP3
TXM3
NC
NC
KSZ8775
(TOP VIEW)
2015 Microchip Technology Inc.
DS00002129C-page 7
KSZ8775CLX
6
RXP1
I
1
Port 1 physical receive signal + (differential).
7
RXM1
I
1
Port 1 physical receive signal - (differential).
8
TXP1
O
1
Port 1 physical transmit signal + (differential).
9
TXM1
O
1
Port 1 physical transmit signal - (differential).
10
RXP2
I
2
Port 2 physical receive signal + (differential).
11
RXM2
I
2
Port 2 physical receive signal - (differential).
12
TXP2
O
2
Port 2 physical transmit signal + (differential)
13
TXM2
O
2
Port 2 physical transmit signal - (differential).
14
VDDAT
P
3.3V or 2.5V analog power
15
RXP3
I
3
Port 3 physical receive signal + (differential).
16
RXM3
I
3
Port 3 physical receive signal - (differential).
17
TXP3
O
3
Port 3 physical transmit signal + (differential).
18
TXM3
O
3
Port 3 physical transmit signal – (differential).
19
NC
NC
No connect
20
NC
NC
No connect
21
GNDA
GND
Analog ground
22
INTR_N
OPU
Interrupt.
Active low.
This pin is an open-drain output pin.
Note
: an external pull-up resistor is needed on
this pin when it is in use.
23
NC
NC
No connect
24
TXD4_1
IPD
4
RMII:
Port 4 RMII transmit bit [1].
25
LED3_1
IPU/O
3
Port 3 LED Indicator 1.
See global Register 11 bits [5:4] for details.
Strap option: Switch Port 5 GMAC5 interface
mode select by
LED3[1:0]
00 = MII for SW5-MII
01 = RMII for SW5-RMII
10 = Reserved
11 = RGMII for SW5-RGMII (default)
26
TXD4_0
IPD
4
RMII:
Port 4 RMII transmit bit [0]
27
LED3_0
IPU/O
3
Port 3 LED Indicator 0.
See global Register 11 bits [5:4] for details.
Strap option: see LED3_1
28
VDD12D
P
1.2V core power.
29
GNDD
GND
Digital ground.
TABLE 2-1:
SIGNALS (CONTINUED)
Num Pins
Pin Name
Type
Port
Pin Description
KSZ8775CLX
DS00002129C-page 8
2015 Microchip Technology Inc.
30
TXC4/REF-
CLKI4
I/O
4
Port 4 Switch MAC4 SW4-RMII Reference
Clock Input
RMII: Input for receiving 50 MHz clock in normal
mode.
31
RXC4
I/O
4
Port 4 Switch MAC4 SW4-RMII reference clock
out:
RMII: Output 50 MHz reference clock for the
receiving/transmit in the clock mode.
32
TXEN5/
TXD5_CTL
IPD
5
MII/RMII:
Port 5 switch transmit enable.
RGMII:
Transmit data control.
33
TXD5_0
IPD
5
RGMII/MII/RMII:
Port 5 switch transmit bit [0].
34
TXD5_1
IPD
5
RGMII/MII/RMII:
Port 5 switch transmit bit [1].
35
GNDD
GND
Digital ground.
36
VDDIO
P
3.3V, 2.5V, or 1.8V digital V
DD
for digital I/O cir-
cuitry.
37
TXD5_2
IPD
5
RGMII/MII:
Port 5 switch transmit bit [2].
RMII:
No connection.
38
TXD5_3
IPD
5
RGMII/MII:
Port 5 switch transmit bit [3].
RMII:
No connection.
39
TXER5
IPD
5
MII:
Port 5 switch transmit error.
RGMII/RMII:
No connection.
40
NC
NC
No connect
41
GNDD
GND
Digital ground
42
RXD4_1
IPD/O
4
RMII:
Port 4 SW4-RMII receive bit [1]
TABLE 2-1:
SIGNALS (CONTINUED)
Num Pins
Pin Name
Type
Port
Pin Description
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DS00002129C-page 9
KSZ8775CLX
43
RXD4_0
Ipd/O
4
RMII:
Port 4 SW4-RMII receive bit [0].
Strap Option: Clock or Normal Mode Select in
Port 4 RMII
PU = Clock mode in RMII, using 25MHz OSC
clock and provide 50 MHz RMII clock from pin
RXC4 (Default)
PD = Normal mode in RMII, the TXC4/REFCLKI4
pin on the Port 4 RMII will receive an external
50 MHz clock
Note: Port 4 also can use either an internal or
external clock in RMII mode based on this strap
pin or the setting of the Register 70 (0x46) bit [7].
An external pull-up/down resistor is requested for
the strap-in.
44
RXDV4/CRS-
DV4
IPD/O
4
RMII:
CRSDV4 is for Port 4 RMII carrier sense/receive
data valid output.
45
NC
NC
No connect
46
VDD12D
P
5
1.2V core power
47
TXC5/REF-
CLKI5/
GTXC5
I/O
5
Port 5 Switch GMAC5 Clock Pin:
MII:
2.5/25 MHz clock, PHY mode is output, MAC
mode is input.
RMII:
Input for receiving 50 MHz in normal mode.
RGMII:
Input 125 MHz clock with falling and rising
edge to latch data for the data transfer.
48
RXC5/
GRXC5
I/O
5
Port 5 Switch GMAC5 Clock Pin:
MII:
2.5/25 MHz clock, PHY mode is output, MAC
mode is input.
RMII:
Output 50 MHz reference clock for the
receiving/transmit in the clock mode.
RGMII:
Output 125 MHz clock with falling and ris-
ing edge to latch data for the receiving.
49
RXD5_0
IPD/O
5
RGMII/MII/RMII:
Port 5 switch receive bit [0]
50
RXD5_1
IPD/O
5
RGMII/MII/RMII:
Port 5 switch receive bit [1]
51
GNDD
GND
Digital ground
52
VDDIO
P
3.3V, 2.5V, or 1.8V digital VDD for digital I/O cir-
cuitry.
53
RXD5_2
IPD/O
5
RGMII/MII:
Port 5 switch receive bit [2]
RMII:
No connection.
TABLE 2-1:
SIGNALS (CONTINUED)
Num Pins
Pin Name
Type
Port
Pin Description
KSZ8775CLX
DS00002129C-page 10
2015 Microchip Technology Inc.
54
RXD5_3
IPD/O
5
RGMII/MII:
Port 5 switch receive bit [3]
RMII:
No connection.
55
RXDV5/CRS-
DV5
/RXD5_CTL
IPD/O
5
MII:
RXDV5 is for Port 5 switch MII receiving data
valid.
RMII:
CRSDV5 is for Port 5 RMII carrier sense/receive
data valid output.
RGMII:
RXD5_CTL is for Port 5 RGMII receiving data
control.
56
RXER5
IPD/O
5
MII:
Port 5 switch receive error.
RGMII/RMII:
No connection.
57
CRS5
IPD/O
5
MII:
Port 5 switch MII modes carrier sense.
RGMII/RMII:
No connection.
58
COL5
IPD/O
5
MII:
Port 5 Switch MII collision detect.
RGMII/RMII:
No connection.
59
REFCLKO
IPU/O
25 MHz clock output (Option)
Controlled by the strap pin LED2_0.
Default is enabled; it is better to disable it if not
using it.
60
PME_N
I/O
Power Management Event
This output signal indicates that a wake-on-LAN
event has been detected as a result of a wake-up
frame detection. The KSZ8775CLX is requesting
the system to wake up from low power mode. Its
assertion polarity is programmable with the
default polarity set to active low.
61
GNDD
GND
Digital ground
62
TXEN4
IPD
4
RMII:
Port 4 switch SW4-RMII transmit enable.
TABLE 2-1:
SIGNALS (CONTINUED)
Num Pins
Pin Name
Type
Port
Pin Description