2016 Microchip Technology Inc.
DS20005372A-page 1
Features
• 24 Channels of high voltage analog switch
• 3.3 or 5.0V CMOS input logic level
• 24 Channel SPST configuration
• 20 MHz data shift clock frequency
• HVCMOS technology for high performance
• Very low quiescent power dissipation-10µA
• Low parasitic capacitance
• DC to 50 MHz analog signal frequency
• -60dB typical OFF-isolation at 5.0 MHz
• CMOS logic circuitry for low power
• Excellent noise immunity
• Cascadable serial data register with latches
• Flexible operating supply voltages
• Integrated bleed resistors on outputs (HV2762 only)
Applications
• Medical ultrasound imaging
• Piezoelectric transducer drivers
• Inkjet printer heads
• Optical MEMS modules
Description
HV2662/HV2762 are low-charge injection, 24-channel,
high-voltage analog switch integrated circuits (ICs).
These ICs excel in applications requiring high-voltage
switching controlled by low-voltage control signals such
as medical ultrasound imaging, piezoelectric trans-
ducer driver, and printers. HV2762 provides integrated
bleed resistors that eliminate voltage build-up on
capacitive loads such as piezoelectric transducers.
HV2662 does not have integrated bleed resistors.
HV2662/HV2762 shift input data into a 24-bit shift reg-
ister that can then be retained in a 24-bit latch. To
reduce any possible clock feed through noise, the
latch-enable bar should be left high until all bits are
clocked in during the rising edge of the clock. Using
High Voltage CMOS technology, these ICs combine
high-voltage, bilateral DMOS switches and low-power
CMOS logic to provide efficient control of high voltage
analog signals.
The device is suitable for various combinations of high
voltage supplies, e.g., V
PP
/V
NN
: +40V/-160V, +100V/-
100V, and +160V/-40V.
Package Types
64-ball VFBGA
See
Table 2-1
for pin information
1 2 3 4 5 6 7 8 9 10
A
B
C
D
E
F
G
H
J
K
Top View
HV2662 / HV2762
Low Harmonic Distortion, 24-Channel SPST
High Voltage Analog Switch
HV2662 / HV2762
DS20005372A-page 2
2016 Microchip Technology Inc.
Block Diagram
SW0
SW1
SW2
Level
Shifters
Latches
24-Bit
Shift
Register
CLK
DIN
DOUT
VDD GND LE CLR VPP VNN RGND
Output
Switches
D
LE
CLR
D
LE
CLR
D
LE
CLR
D
LE
CLR
D
LE
CLR
SW22
SW23
Bleed
Resistors
Note:
Bleed resistors and RGND only apply to HV2762.
2016 Microchip Technology Inc.
DS20005372A-page 3
HV2662 / HV2762
1.0
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
†
V
DD
logic supply............................................................................................................................................................... -0.50 to +6.5V
V
PP
- V
NN
differential supply .......................................................................................................................................................... 220V
V
PP
positive supply ...................................................................................................................................................-0.5 to V
NN
+ 200V
V
NN
negative supply.......................................................................................................................................................... +0.5 to -200V
Logic input voltage ................................................................................................................................................... -0.5V to V
DD
+0.3V
Analog signal range .............................................................................................................................................................. V
NN
to V
PP
Peak analog signal current/channel................................................................................................................................................ 2.0A
Storage temperature .................................................................................................................................................... -65°C to +150°C
Power dissipation ........................................................................................................................................................................... 1.0W
† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at those or any other conditions above those indicated in the
operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Notes
1
–
3
)
Symbol
Parameter
Value
V
DD
Logic power supply voltage
3.0V to 5.5V (
Note 2
)
V
PP
Positive high voltage supply
+40V to V
NN
+200V (
Note 2
)
V
NN
Negative high voltage supply
-40V to -160V (
Note 2
)
V
IH
High level input voltage
0.9V
DD
to V
DD
V
IL
Low level input voltage
0V to 0.1 V
DD
V
SIG
Analog signal voltage peak-to-peak
V
NN
+10V to V
PP
-10V (
Note 3
)
T
A
Operating free air temperature
0°C to 70°C
Note 1: Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last.
2: Rise and fall times of power supplies V
DD
, V
PP
, and V
NN
should not be less than 1.0msec.
3: V
SIG
must be V
NN
≤ V
SIG
≤ V
PP
or floating during power up/down transition.
DC ELECTRICAL CHARACTERISTICS
Electrical Specifications: Over recommended operating conditions unless otherwise specified.
See test circuits
Figure 3-2
Parameter
Symbol
0°C
25°C
70°C
Units Conditions
Min
Max
Min
Typ
Max
Min
Max
Small signal switch
ON-resistance
R
ONS
-
-
-
26
-
-
-
Ω
I
SIG
= 5.0mA V
PP
= +40V,
V
NN
= -160V
-
-
-
22
-
-
-
I
SIG =
200mA
-
-
-
22
-
-
-
I
SIG =
5.0mA V
PP
= +100V,
V
NN
= -100V
-
-
-
18
-
-
-
I
SIG
= 200mA
-
-
-
20
-
-
-
I
SIG
= 5.0mA V
PP
= +160V,
V
NN
= -40V
-
-
-
16
-
-
-
I
SIG
= 200mA
Small signal switch
ON-resistance matching
∆R
ONS
-
20
-
5.0
20
-
20
%
I
SIG
= 5.0mA,
V
PP
= +100V, V
NN
= -100V
Large signal switch
ON-resistance
R
ONL
-
-
-
30
-
-
-
Ω
V
SIG
= V
PP
-10V, I
SIG
= 1A
(
Note 1
)
Output-switch shunt
resistance (HV2762
only)
R
INT
-
-
20
35
50
-
-
KΩ Output switch to R
GND
,
I
RINT
=0.5 mA
HV2662 / HV2762
DS20005372A-page 4
2016 Microchip Technology Inc.
Note 1: Specification is obtained by characterization and is not 100% tested.
2: Design guidance only
Switch OFF-leakage
per switch
I
SOL
-
5.0
-
1.0
10
-
15
μA
V
SIG
= V
PP
-10V, V
NN
+10V
DC offset switch OFF
V
OS
-
300
-
100
300
-
300
mV No load for HV2762.
R
LOAD
= 100 KΩ for
HV2662
DC offset switch ON
-
500
-
100
500
-
500
Quiescent V
PP
supply
current
I
PPQ
-
-
-
10
50
-
-
μA
All switches OFF
Quiescent V
NN
supply
current
I
NNQ
-
-
-
-10
-50
-
-
Quiescent V
PP
supply
current
I
PPQ
-
-
-
10
50
-
-
μA
All switches ON,
I
SW
= 5.0mA
Quiescent V
NN
supply
current
I
NNQ
-
-
-
-10
-50
-
-
Switch output peak
current
I
SW
-
-
-
2.0
1.3
-
-
A
V
SIG
duty cycle < 0.1%
(
Note 1
)
Output switching fre-
quency
f
SW
-
-
-
-
50
-
-
kHz Duty cycle = 50%
(
Note 1
)
Average VPP supply
current
I
PP
-
4.0
-
-
4.5
-
5.0
mA V
PP
= +40V,
V
NN
= -160V
All output
switches are
turning ON
and OFF at
50 kHz with
no load
-
4.0
-
-
4.5
-
5.0
V
PP
= +100V,
V
NN
= -100V
-
4.0
-
-
4.5
-
5.0
V
PP
= +160V,
V
NN
= -40V
Average V
NN
supply
current
I
NN
-
4.0
-
-
4.5
-
5.0
mA V
PP
= +40V,
V
NN
= -160V
All output
switches are
turning ON
and OFF at
50 kHz with
no load
-
4.0
-
-
4.5
-
5.0
V
PP
= +100V,
V
NN
= -100V
-
4.0
-
-
4.5
-
5.0
V
PP
= +160V,
V
NN
= -40V
Average V
DD
supply
current
I
DD
-
8.0
-
-
8.0
-
8.0
mA f
CLK
= 5.0MHz, V
DD
= 5.0V
Quiescent V
DD
supply
current
I
DDQ
-
10
-
-
10
-
10
μA
All logic inputs are static
Data out source current
I
SOR
0.45
-
0.45
0.70
-
0.40
-
mA V
OUT
= V
DD
-0.7V
Data out sink current
I
SINK
0.45
-
0.45
0.70
-
0.40
-
mA V
OUT
= 0.7V
Logic input capacitance
C
IN
-
10
-
-
10
-
10
pF
(
Note 2
)
DC ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Over recommended operating conditions unless otherwise specified.
See test circuits
Figure 3-2
Parameter
Symbol
0°C
25°C
70°C
Units Conditions
Min
Max
Min
Typ
Max
Min
Max
AC ELECTRICAL CHARACTERISTICS
Electrical Specifications: Over recommended operating conditions unless otherwise specified.
See test circuits
Figure 3-2
Parameter
Symbol
0°C
25°C
70°C
Units Conditions
Min
Max
Min
Typ
Max
Min
Max
Set up time before
LE rises
t
SD
25
-
25
-
-
25
-
ns
(
Note 1
)
Time width of LE
t
WLE
56
-
56
-
-
56
-
ns
V
DD
= 3.0V (
Note 1
)
12
-
12
-
-
12
-
V
DD
= 5.0V (
Note 1
)
Clock delay time to
data out
t
DO
9.0
40
9.0
-
40
9.0
40
ns
V
DD
= 3.0V (
Note 1
)
8.0
30
8.0
-
30
8.0
30
V
DD
= 5.0V (
Note 1
)
Time width of CLR
t
WCLR
55
-
55
-
-
55
-
ns
(
Note 1
)
Set up time data to
clock
t
SU
21
-
21
-
-
21
-
ns
V
DD
= 3.0V (
Note 1
)
7.0
-
7.0
-
-
7.0
-
V
DD
= 5.0V (
Note 1
)
Hold time data from
clock
t
H
5.0
-
5.0
-
-
5.0
-
ns
V
DD
= 3.0V (
Note 1
)
5.0
-
5.0
-
-
5.0
-
V
DD
= 5.0V (
Note 1
)
Clock frequency
f
CLK
-
8
-
-
8
-
8
MHz V
DD
= 3.0V
-
20
-
-
20
-
20
V
DD
= 5.0V (
Note 1
)
Clock rise and fall
times
t
R
, t
F
-
50
-
-
50
-
50
ns
(
Note 1
)
Turn ON time
t
ON
-
5.0
-
-
5.0
-
5.0
μs
V
SIG
= V
PP
-10V,
R
LOAD
= 10kΩ
Turn OFF time
t
OFF
-
5.0
-
-
5.0
-
5.0
Maximum V
SIG
slew rate
dv/dt
-
20
-
-
20
-
20
V/ns V
PP
= +40V, V
NN
= -160V
(
Note 1
)
-
20
-
-
20
-
20
V
PP
= +100V, V
NN
= -100V
(
Note 1
)
-
20
-
-
20
-
20
V
PP
= +160V, V
NN
= -40V
(
Note 1
)
OFF isolation
K
O
-30
-
-30
-33
-
-30
-
dB
f = 5.0 MHz,
1.0 KΩ//15 pF load (
Note 1
)
-58
-
-58
-60
-
-58
-
f = 5.0 MHz, 50Ω load (
Note 1
)
Switch crosstalk
K
CR
-60
-
-60
-70
-
-60
-
dB
f = 5.0 MHz, 50Ω load (
Note 1
)
Output switch isola-
tion diode current
I
ID
-
300
-
-
300
-
300
mA
300 ns pulse width,
2.0% duty cycle (
Note 1
)
OFF capacitance
SW to GND
C
SG(OFF)
-
14
-
9.0
14
-
14
pF
V
SIG
= 0V, f = 1.0 MHz
(
Note 1
)
ON capacitance
SW to GND
C
SG(ON)
-
17
-
12
17
-
17
Output voltage
spike (per switch)
+V
SPK
-
-
-
-
150
-
-
mV
V
PP
= +40V, V
NN
= -160V
R
LOAD
= 50Ω (
Note 1
)
-V
SPK
-
-
-
-
150
-
-
+V
SPK
-
-
-
-
150
-
-
V
PP
= +100V, V
NN
= -100V
R
LOAD
= 50Ω (
Note 1
)
-V
SPK
-
-
-
-
150
-
-
+V
SPK
-
-
-
-
150
-
-
V
PP
= +160V, V
NN
= -40V
R
LOAD
= 50Ω (
Note 1
)
-V
SPK
-
-
-
-
150
-
-
Charge injection
(per switch)
QC
-
-
-
820
-
-
-
pC
V
PP
= +40V, V
NN
= -160V
(
Note 1
)
-
-
-
600
-
-
-
V
PP
= +100V, V
NN
= -100V
(
Note 1
)
-
-
-
350
-
-
-
V
PP
= +160V, V
NN
= -40V
(
Note 1
)
2016 Microchip Technology Inc.
DS20005372A-page 5
HV2662 / HV2762
Note 1: Specification is obtained by characterization and is not 100% tested.
TEMPERATURE SPECIFICATIONS
Electrical Specifications: Unless otherwise specified, for all specifications T
A
=T
J
= +25°C
Parameter
Symbol
Min
Typ
Max
Units Conditions
Temperature Ranges
Storage Temperature
T
A
-65
–
150
°C
Package Thermal Resistances
Thermal Resistance, 64-Ball
VFBGA
θ
ja
–
36
–
°C/W
HV2662 / HV2762
DS20005372A-page 6
2016 Microchip Technology Inc.
2016 Microchip Technology Inc.
DS20005372A-page 7
HV2662 / HV2762
2.0
PIN DESCRIPTION
The locations of the balls are listed in
Package Types
.
TABLE 2-1:
BALL DESCRIPTION 64-BALL VFBGA
Pin #
HV2662
HV2762
Description
A1
SW22B
SW22B
Analog switch 22 terminal B
A2
V
NN
V
NN
Negative supply voltage
A3
SW21B
SW21B
Analog switch 21 terminal B
A4
SW20B
SW20B
Analog switch 20 terminal B
A5
SW19B
SW19B
Analog switch 19 terminal B
A6
SW18B
SW18B
Analog switch 18 terminal B
A7
SW17B
SW17B
Analog switch 17 terminal B
A8
SW16B
SW16B
Analog switch 16 terminal B
A9
SW15B
SW15B
Analog switch 15 terminal B
A10
SW15A
SW15A
Analog switch 15 terminal A
B1
SW23B
SW23B
Analog switch 23 terminal B
B2
SW23A
SW23A
Analog switch 23 terminal A
B3
SW22A
SW22A
Analog switch 22 terminal A
B4
SW21A
SW21A
Analog switch 21 terminal A
B5
SW20A
SW20A
Analog switch 20 terminal A
B6
SW19A
SW19A
Analog switch 19 terminal A
B7
SW18A
SW18A
Analog switch 18 terminal A
B8
SW17A
SW17A
Analog switch 17 terminal A
B9
SW16A
SW16A
Analog switch 16 terminal A
B10
SW14B
SW14B
Analog switch 14 terminal B
C1
NC
NC
No connect
C2
V
PP
V
PP
Positive supply voltage
C9
SW14A
SW14A
Analog switch 14 terminal A
C10
SW13B
SW13B
Analog switch 13 terminal B
D1
CLR
CLR
Latch clear logic input
D2
NC
RGND
No connect/ Ground for bleed resistor
D9
V
NN
V
NN
Negative supply voltage
D10
SW13A
SW13A
Analog switch 13 terminal A
E1
LE
LE
Latch-enable logic input, low active
E2
CLK
CLK
Clock logic input for shift register
E9
SW12B
SW12B
Analog switch 12 terminal B
E10
SW12A
SW12A
Analog switch 12 terminal A
F1
V
DD
V
DD
Logic supply voltage
F2
GND
GND
Ground
F9
SW11B
SW11B
Analog switch 11 terminal B
F10
SW11A
SW11A
Analog switch 11 terminal A
G1
D
IN
D
IN
Data-in logic input
G2
D
OUT
D
OUT
Data-out logic output
G9
SW10B
SW10B
Analog switch 10 terminal B
G10
V
NN
V
NN
Negative supply voltage
H1
NC
RGND
No connect/ Ground for bleed resistor
H2
V
PP
V
PP
Positive supply voltage
HV2662 / HV2762
DS20005372A-page 8
2016 Microchip Technology Inc.
H9
SW10A
SW10A
Analog switch 10 terminal A
H10
SW9B
SW9B
Analog switch 9 terminal B
J1
SW0A
SW0A
Analog switch 0 terminal A
J2
SW0B
SW0B
Analog switch 0 terminal B
J3
SW1B
SW1B
Analog switch 1 terminal B
J4
SW2B
SW2B
Analog switch 2 terminal B
J5
SW3B
SW3B
Analog switch 3 terminal B
J6
SW4B
SW4B
Analog switch 4 terminal B
J7
SW5B
SW5B
Analog switch 5 terminal B
J8
SW6B
SW6B
Analog switch 6 terminal B
J9
SW7B
SW7B
Analog switch 7 terminal B
J10
SW9A
SW9A
Analog switch 9 terminal A
K1
SW1A
SW1A
Analog switch 1 terminal A
K2
V
NN
V
NN
Negative supply voltage
K3
SW2A
SW2A
Analog switch 2 terminal A
K4
SW3A
SW3A
Analog switch 3 terminal A
K5
SW4A
SW4A
Analog switch 4 terminal A
K6
SW5A
SW5A
Analog switch 5 terminal A
K7
SW6A
SW6A
Analog switch 6 terminal A
K8
SW7A
SW7A
Analog switch 7 terminal A
K9
SW8A
SW8A
Analog switch 8 terminal A
K10
SW8B
SW8B
Analog switch 8 terminal B
TABLE 2-1:
BALL DESCRIPTION 64-BALL VFBGA (CONTINUED)
Pin #
HV2662
HV2762
Description
2016 Microchip Technology Inc.
DS20005372A-page 9
HV2662 / HV2762
3.0
FUNCTIONAL DESCRIPTION
FIGURE 3-1:
LOGIC TIMING WAVEFORMS
DATA IN
DIN
LE
CLOCK
DATA OUT
DOUT
OFF
ON
CLR
V
OUT
(typ)
50%
50%
50%
50%
t
WLE
t
SD
50%
50%
t
SU
t
h
t
OFF
50%
t
DO
t
ON
t
WCL
D
N - 1
D
N
D
N + 1
50%
50%
90%
10%
TABLE 3-1:
TRUTH TABLE
D0
1
D1
...
D15
D16
...
D23
2
LE
3
CLR
4
SW0
5
,
6
SW1
...
SW15
SW16
...
SW23
L
-
...
-
-
...
-
L
L
OFF
-
...
-
-
...
-
H
-
-
-
-
L
L
ON
-
-
-
-
-
L
-
-
-
L
L
-
OFF
-
-
-
-
H
-
-
-
L
L
-
ON
-
-
-
-
-
-
-
-
L
L
-
-
-
-
-
-
-
-
-
-
L
L
-
-
-
-
-
-
-
L
-
-
L
L
-
-
OFF
-
-
-
-
H
-
-
L
L
-
-
ON
-
-
-
-
-
L
-
L
L
-
-
-
OFF
-
-
-
-
H
-
L
L
-
-
-
ON
-
-
-
-
-
-
L
L
-
-
-
-
-
-
-
-
-
-
L
L
-
-
-
-
-
-
-
-
-
-
L
L
-
-
-
-
-
-
-
-
-
-
L
L
-
-
-
-
-
-
-
-
-
L
L
L
-
-
-
-
OFF
-
-
-
-
H
L
L
-
-
-
-
ON
X
X
X
X
X
X
X
H
L
HOLD PREVIOUS STATE
X
X
X
X
X
X
X
X
H
ALL SWITCHES OFF
Note 1: Serial data is clocked in on the L to H transition of the CLK
2: DOUT is high when data in the register 23 is high.
3: Shift registers clocking has no effect on the switch states if LE is high.
4: The CLR clear input overrides all other inputs.
5: The 24 switches operate independently.
6: All 24 switches go to a state retaining their latched condition at the rising edge of LE. When LE is low, the
shift registers data flow through the latch.
HV2662 / HV2762
DS20005372A-page 10
2016 Microchip Technology Inc.
3.1
Application Information
FIGURE 3-2:
TEST CIRCUITS
DC Offset Switch
ON/OFF
V
PP
5V
V
NN
VPP
VNN
VDD
GND
V
OUT
T
ON
/T
OFF
Test Circuit
5V
GND
10kΩ
V
OUT
Output Switch
Isolation Diode Current
I
ID
5V
GND
V
NN
V
SIG
Switch Crosstalk
NC
5V
GND
50Ω
Output Voltage Spike
5V
GND
V
OUT
1kΩ
R
LOAD
50Ω
+V
SPK
–V
SPK
OFF Isolation
5V
GND
V
OUT
50Ω
R
LOAD
R
LOAD
V
PP
V
NN
VPP
VNN
VDD
V
PP
V
NN
VPP
VNN
VDD
V
PP
V
NN
VPP
VNN
VDD
V
PP
V
NN
VPP
VNN
VDD
V
PP
V
NN
VPP
VNN
VDD
K
CR
= 20Log
V
OUT
V
IN
V
PP
-10V
Switch Off Leakage
per Switch
RGND
Open
Q = 1000pF x ΔV
OUT
Charge Injection
5V
GND
V
PP
V
NN
VPP
VNN
VDD
V
PP
5V
V
NN
VPP
VNN
VDD
Open
I
SOL
GND
V
OUT
ΔV
OUT
1000pF
RGND
RGND
RGND
RGND
RGND
RGND
RGND
V
PP
-10V
V
IN
=10V
PP
@5.0MHz
K
O
= 20Log
V
OUT
V
IN
V
IN
=10V
PP
@5.0MHz
V
SIG
R
LOAD
100kΩ
HV2662
only
Note:
RGND only applies to HV2762.