2013-2015 Microchip Technology Inc.
DS00001567B-page 1
General Description
The CAP1206 is a multiple channel capacitive touch
sensor controller. It contains six (6) individual capaci-
tive touch sensor inputs with programmable sensitivity
for use in touch sensor applications. Each sensor input
is calibrated to compensate for system parasitic capac-
itance and automatically recalibrated to compensate
for gradual environmental changes.
The CAP1206 includes Multiple Pattern Touch recogni-
tion that allows the user to select a specific set of but-
tons to be touched simultaneously. If this pattern is
detected, a status bit is set and an interrupt is gener-
ated.
The CAP1206 has Active and Standby states, each
with its own sensor input configuration controls. Power
consumption in the Standby state is dependent on the
number of sensor inputs enabled as well as averaging,
sampling time, and cycle time. Deep Sleep is the low-
est power state available, drawing 5µA (typical) of cur-
rent. In this state, no sensor inputs are active, and
communications will wake the device.
Applications
• Desktop and Notebook PCs
• LCD Monitors
• Consumer Electronics
• Appliances
Features
• Six (6) Capacitive Touch Sensor Inputs
- Programmable sensitivity
- Automatic recalibration
- Calibrates for parasitic capacitance
- Individual thresholds for each button
• Multiple Button Pattern Detection
• Power Button Support
• Press and Hold Feature for Volume-like Applica-
tions
• 3.3V or 5V Supply
• Analog Filtering for System Noise Sources
• RF Detection and Avoidance Filters
• Digital EMI Blocker
• 8kV ESD Rating on All Pins (HBM)
• Low Power Operation
- 5µA quiescent current in Deep Sleep
- 50µA quiescent current in Standby (1 sensor
input monitored)
- Samples one or more channels in Standby
• SMBus / I
2
C Compliant Communication Interface
• Available in a 10-pin 3mm x 3mm DFN RoHS
compliant package
CAP1206
6-Channel Capacitive Touch Sensor
CAP1206
DS00001567B-page 2
2013-2015 Microchip Technology Inc.
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The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
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2013-2015 Microchip Technology Inc.
DS00001567B-page 3
CAP1206
Table of Contents
1.0 Introduction ..................................................................................................................................................................................... 4
2.0 Pin Description and Configuration .................................................................................................................................................. 8
3.0 Functional Description .................................................................................................................................................................. 21
4.0 Register Descriptions .................................................................................................................................................................... 58
5.0 Operational Characteristics ........................................................................................................................................................... 69
6.0 Package Outline ............................................................................................................................................................................ 85
Appendix A: Data Sheet Revision History ........................................................................................................................................... 91
The Microchip Web Site ...................................................................................................................................................................... 93
Customer Change Notification Service ............................................................................................................................................... 93
Customer Support ............................................................................................................................................................................... 93
Product Identification System ............................................................................................................................................................. 94
2013-2015 Microchip Technology Inc.
DS00001567B-page 4
CAP1206
1.0
INTRODUCTION
1.1
Block Diagram
1.2
Pin Diagrams
FIGURE 1-1:
CAP1206 BLOCK DIAGRAM
FIGURE 1-2:
CAP1206 14-PIN SOIC
SMBus
Protocol
VDD
GND
Capacitive Touch Sensing Algorithm
CS1
CS2
CS3
CS4
CS5
SMCLK
SMDATA
ALERT#
CS6
CA
P1
206
1
2
3
4
14
13
12
11
5
6
7
10
9
8
N/C
CS1
ALERT#
SMDAT
SMCLK
N/C
N/C
CS2
CS3
CS4
CS5
CS6
GND
VDD
CAP1206
DS00001567B-page 5
2013-2015 Microchip Technology Inc.
FIGURE 1-3:
CAP1206 PIN DIAGRAM (10-PIN 3 X 3 MM DFN)
TABLE 1-1:
PIN DESCRIPTION FOR CAP1206
QFN Pin #
SOIC Pin #
Pin Name
Pin Function
Pin Type
Unused
Connection
1
2
CS1
Capacitive Touch Sensor Input 1
AIO
Connect to
Ground
2
3
ALERT#
ALERT# - Active low alert / interrupt out-
put for SMBus alert - requires pull-up
resistor (default)
OD
Connect to
Ground
3
4
SMDATA
SMDATA - Bi-directional, open-drain
SMBus or I
2
C data - requires pull-up
resistor
DIOD
n/a
4
5
SMCLK
SMCLK - SMBus or I
2
C clock input -
requires pull-up resistor
DI
n/a
5
7
VDD
Positive Power supply
Power
n/a
6
9
CS6
Capacitive Touch Sensor Input 6
AIO
Connect to
Ground
7
10
CS5
Capacitive Touch Sensor Input 5
AIO
Connect to
Ground
8
11
CS4
Capacitive Touch Sensor Input 4
AIO
Connect to
Ground
9
12
CS3
Capacitive Touch Sensor Input 3
AIO
Connect to
Ground
10
13
CS2
Capacitive Touch Sensor Input 2
AIO
Connect to
Ground
Bottom
Pad
8
GND
Ground
Power
n/a
CS3
CS2
1
2
3
4
5
CS4
CS1
ALERT#
SMDATA
VDD
SMCLK
CS5
CS6
GND
10
9
8
7
6
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DS00001567B-page 6
CAP1206
1.3
Pin Description
APPLICATION NOTE: All digital pins are 5V tolerant pins.
The pin types are described in
Table 1-2, "Pin Types"
.
TABLE 1-2:
PIN TYPES
Pin Type
Description
Power
This pin is used to supply power or ground to the device.
DI
Digital Input - This pin is used as a digital input. This pin is 5V tolerant.
AIO
Analog Input / Output - This pin is used as an I/O for analog signals.
DIOD
Digital Input / Open Drain Output - This pin is used as a digital I/O. When it is used as an
output, it is open drain and requires a pull-up resistor. This pin is 5V tolerant.
OD
Open Drain Digital Output - This pin is used as a digital output. It is open drain and requires
a pull-up resistor. This pin is 5V tolerant.
2013-2015 Microchip Technology Inc.
DS00001567B-page 7
CAP1206
2.0
ELECTRICAL SPECIFICATIONS
Note 2-1
Stresses above those listed could cause permanent damage to the device. This is a stress rating
only and functional operation of the device at any other condition above those indicated in the
operation sections of this specification is not implied.
Note 2-2
For the 5V tolerant pins that have a pull-up resistor, the voltage difference between V
5VT_PIN
and V
DD
must never exceed 3.6V.
Note 2-3
The Package Power Dissipation specification assumes a recommended thermal via design consisting
of a 2x3 matrix of 0.3mm (12mil) vias at 0.9mm pitch connected to the ground plane with a 1.6 x
2.3mm thermal landing.
Note 2-4
Junction to Ambient (
JA
) is dependent on the design of the thermal vias. Without thermal vias and
a thermal landing, the
JA
will be higher.
TABLE 2-1:
ABSOLUTE MAXIMUM RATINGS
Voltage on VDD pin
-0.3 to 6.5
V
Voltage on CS pins to GND
-0.3 to 4.0
V
Voltage on 5V tolerant pins (V
5VT_PIN
)
-0.3 to 5.5
V
Voltage on 5V tolerant pins (|V
5VT_PIN
- V
DD
|) (see
Note 2-2
)
0 to 3.6
V
Input current to any pin except VDD
+10
mA
Output short circuit current
Continuous
N/A
Package Power Dissipation up to T
A
= 85°C for 10-pin DFN
(see
Note 2-3
)
0.5
W
Junction to Ambient (
JA
) (see
Note 2-4
)
78
°C/W
Operating Ambient Temperature Range
-40 to 125
°C
Storage Temperature Range
-55 to 150
°C
ESD Rating, All Pins, HBM
8000
V
CAP1206
DS00001567B-page 8
2013-2015 Microchip Technology Inc.
TABLE 2-2:
ELECTRICAL SPECIFICATIONS
V
DD
= 3V to 5.5V, T
A
= 0°C to 85°C, all Typical values at T
A
= 25°C unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Conditions
DC Power
Supply Voltage
V
DD
3.0
5.5
V
Supply Current
I
STBY_DEF
120
170
µA
Standby state active
1 sensor input monitored
Default conditions (8 avg, 70ms
cycle time)
I
STBY_LP
50
µA
Standby state active
1 sensor input monitored
1 avg, 140ms cycle time
I
DSLEEP_3V
5
TBD
µA
Deep Sleep state active
No communications
T
A
< 40°C
3.135 < V
DD
< 3.465V
I
DD
500
750
µA
Capacitive Sensing Active
Capacitive Touch Sensor Inputs
Maximum Base
Capacitance
C
BASE
50
pF
Pad untouched
Minimum Detectable
Capacitive Shift
C
TOUCH
20
fF
Pad touched - default conditions
Recommended Cap
Shift
C
TOUCH
0.1
2
pF
Pad touched - Not tested
Power Supply
Rejection
PSR
±3
±10
counts
/ V
Untouched Current Counts
Base Capacitance 5pF - 50pF
Negative Delta Counts disabled
Maximum sensitivity
All other parameters default
Power-On and Brown-out Reset (see
Section 4.2, "Reset"
)
Power-On Reset
Voltage
V
POR
1
1.3
V
Pin States Defined
Power-On Reset
Release Voltage
V
PORR
2.85
V
Rising V
DD
Ensured by design
Brown-Out Reset
V
BOR
2.8
V
Falling V
DD
VDD Rise Rate
(ensures internal
POR signal)
SV
DD
0.05
V/ms
0 to 3V in 60ms
Power-Up Timer
Period
t
PWRT
10
ms
Brown-Out Reset
Voltage Delay
t
BORDC
1
µs
V
DD
= V
BOR
- 1
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DS00001567B-page 9
CAP1206
Timing
Time to
Communications
Ready
t
COMM_DLY
15
ms
Time to First
Conversion Ready
t
CONV_DLY
170
200
ms
I/O Pins
Output Low Voltage
V
OL
0.4
V
I
SINK_IO
= 8mA
Output High Voltage
V
OH
V
DD
-
0.4
V
I
SOURCE_IO
= 8mA
Input High Voltage
V
IH
2.0
V
Input Low Voltage
V
IL
0.8
V
Leakage Current
I
LEAK
±5
µA
powered or unpowered
T
A
< 85°C
pull-up voltage < 3.6V if
unpowered
SMBus Timing
Input Capacitance
C
IN
5
pF
Clock Frequency
f
SMB
10
400
kHz
Spike Suppression
t
SP
50
ns
Bus Free Time Stop
to Start
t
BUF
1.3
µs
Start Setup Time
t
SU:STA
0.6
µs
Start Hold Time
t
HD:STA
0.6
µs
Stop Setup Time
t
SU:STO
0.6
µs
Data Hold Time
t
HD:DAT
0
µs
When transmitting to the master
Data Hold Time
t
HD:DAT
0.3
µs
When receiving from the master
Data Setup Time
t
SU:DAT
0.6
µs
Clock Low Period
t
LOW
1.3
µs
Clock High Period
t
HIGH
0.6
µs
Clock / Data Fall
Time
t
FALL
300
ns
Min = 20+0.1C
LOAD
ns
Clock / Data Rise
Time
t
RISE
300
ns
Min = 20+0.1C
LOAD
ns
Capacitive Load
C
LOAD
400
pF
per bus line
TABLE 2-2:
ELECTRICAL SPECIFICATIONS (CONTINUED)
V
DD
= 3V to 5.5V, T
A
= 0°C to 85°C, all Typical values at T
A
= 25°C unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Conditions
2013-2015 Microchip Technology Inc.
DS00001567B-page 10
CAP1206
3.0
COMMUNICATIONS
3.1
Communications
The CAP1206 communicates using the SMBus or I
2
C protocol.
3.2
System Management Bus
The CAP1206 communicates with a host controller, such as an MCHP SIO, through the SMBus. The SMBus is a two-
wire serial communication protocol between a computer host and its peripheral devices. A detailed timing diagram is
shown in
Figure 3-1
. Stretching of the SMCLK signal is supported; however, the CAP1206 will not stretch the clock sig-
nal.
3.2.1
SMBUS START BIT
The SMBus Start bit is defined as a transition of the SMBus Data line from a logic ‘1’ state to a logic ‘0’ state while the
SMBus Clock line is in a logic ‘1’ state.
3.2.2
SMBUS ADDRESS AND RD / WR BIT
The SMBus Address Byte consists of the 7-bit client address followed by the RD / WR indicator bit. If this RD / WR bit
is a logic ‘0’, then the SMBus Host is writing data to the client device. If this RD / WR bit is a logic ‘1’, then the SMBus
Host is reading data from the client device.
3.2.3
The CAP1206responds to SMBus address 0101_000(r/w).
SMBUS DATA BYTES
All SMBus Data bytes are sent most significant bit first and composed of 8-bits of information.
3.2.4
SMBUS ACK AND NACK BITS
The SMBus client will acknowledge all data bytes that it receives. This is done by the client device pulling the SMBus
Data line low after the 8th bit of each byte that is transmitted. This applies to both the Write Byte and Block Write proto-
cols.
The Host will NACK (not acknowledge) the last data byte to be received from the client by holding the SMBus data line
high after the 8th data bit has been sent. For the Block Read protocol, the Host will ACK each data byte that it receives
except the last data byte.
3.2.5
SMBUS STOP BIT
The SMBus Stop bit is defined as a transition of the SMBus Data line from a logic ‘0’ state to a logic ‘1’ state while the
SMBus clock line is in a logic ‘1’ state. When the CAP1206 detects an SMBus Stop bit and it has been communicating
with the SMBus protocol, it will reset its client interface and prepare to receive further communications.
FIGURE 3-1:
SMBUS TIMING DIAGRAM
SM D A TA
SM C LK
T
B U F
P
S
S - Start C o ndition
P - Stop C ondition
P
S
T
H IG H
T
LO W
T
H D :STA
T
SU :STO
T
H D :STA
T
H D :D AT
T
S U :D AT
T
SU :STA
T
FALL
T
R ISE