1998-2013 Microchip Technology Inc.
Preliminary
DS39016B-page 1
Devices included:
Microcontroller Core Features:
• High-performance RISC CPU
• Only 35 single word instructions to learn
• All single cycle instructions except for program
branches which are two cycle
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
• 2K x 14 words of Program Memory,
128 x 8 bytes of Data Memory (RAM)
• Interrupt capability
• Eight level deep hardware stack
• Direct, indirect, and relative addressing modes
• Power-on Reset (POR)
• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Programmable code-protection
• Power saving SLEEP mode
• Selectable oscillator options
• Low-power, high-speed CMOS technology
• Fully static design
• Wide operating voltage range:
- 2.5V to 6.0V (PIC16C72)
- 2.5V to 5.5V (PIC16CR72)
• High Sink/Source Current 25/25 mA
• Commercial, Industrial and Extended temperature
ranges
• Low-power consumption:
- < 2 mA @ 5V, 4 MHz
- 15
A typical @ 3V, 32 kHz
- < 1
A typical standby current
Pin Diagrams
Peripheral Features:
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler,
can be incremented during sleep via external
crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Capture, Compare, PWM (CCP) module
- Capture is 16-bit, max. resolution is 12.5 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10-bit
• 8-bit 5-channel analog-to-digital converter
• Synchronous Serial Port (SSP) with
SPI and I
2
C
• Brown-out detection circuitry for
Brown-out Reset (BOR)
• PIC16C72
• PIC16CR72
PIC16C72
MCLR/V
PP
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/V
REF
RA4/T0CKI
RA5/SS/AN4
V
SS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
V
DD
V
SS
RC7
RC6
RC5/SDO
RC4/SDI/SDA
• 1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SDIP, SOIC, SSOP,
PIC16CR72
Windowed Side Brazed Ceramic
PIC16C72 SERIES
8-Bit CMOS Microcontrollers with A/D Converter
PIC16C72 Series
DS39016B-page 2
Preliminary
1998-2013 Microchip Technology Inc.
Table of Contents
1.0
Device Overview .......................................................................................................................................................................... 3
2.0
Memory Organization ................................................................................................................................................................... 5
3.0
I/O Ports ..................................................................................................................................................................................... 19
4.0
Timer0 Module ........................................................................................................................................................................... 25
5.0
Timer1 Module ........................................................................................................................................................................... 27
6.0
Timer2 Module ........................................................................................................................................................................... 31
7.0
Capture/Compare/PWM (CCP) Module ..................................................................................................................................... 33
8.0
Synchronous Serial Port (SSP) Module ..................................................................................................................................... 39
9.0
Analog-to-Digital Converter (A/D) Module .................................................................................................................................. 53
10.0 Special Features of the CPU ...................................................................................................................................................... 59
11.0 Instruction Set Summary ............................................................................................................................................................ 73
12.0 Development Support................................................................................................................................................................. 75
13.0 Electrical Characteristics - PIC16C72 Series ............................................................................................................................. 77
14.0 DC and AC Characteristics Graphs and Tables - PIC16C72 ..................................................................................................... 97
15.0 DC and AC Characteristics Graphs and Tables - PIC16CR72 ................................................................................................ 107
16.0 Packaging Information.............................................................................................................................................................. 109
Appendix A:
What’s New in this Data Sheet .................................................................................................................................. 115
Appendix B:
What’s Changed in this Data Sheet ........................................................................................................................... 115
Appendix C:
Device Differences..................................................................................................................................................... 115
Index .................................................................................................................................................................................................. 117
On-Line Support................................................................................................................................................................................. 121
Reader Response .............................................................................................................................................................................. 122
PIC16C72 Series Product Identification System................................................................................................................................ 125
Sales and Support.............................................................................................................................................................................. 125
To Our Valued Customers
We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional
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Key Reference Manual Features
PIC16C72
PIC16CR72
Operating Frequency
DC - 20MHz
DC - 20MHz
Resets
POR, PWRT, OST, BOR
POR, PWRT, OST, BOR
Program Memory - (14-bit words)
2K (EPROM)
2K (ROM)
Data Memory - RAM (8-bit bytes)
128
128
Interrupts
8
8
I/O Ports
PortA, PortB, PortC
PortA, PortB, PortC
Timers
Timer0, Timer1, Timer2
Timer0, Timer1, Timer2
Capture/Compare/PWM Modules
1
1
Serial Communications
Basic SSP
SSP
8-Bit A/D Converter
5 channels
5 channels
Instruction Set (No. of Instructions)
35
35
PIC16C72 Series
1998-2013 Microchip Technology Inc.
Preliminary
DS39016B-page 3
1.0
DEVICE OVERVIEW
This document contains device-specific information for
the operation of the PIC16C72 device. Additional infor-
mation may be found in the PIC
®
Mid-Range MCU Ref-
erence Manual (DS33023) which may be downloaded
from the Microchip website. The Reference Manual
should be considered a complementary document to
this data sheet, and is highly recommended reading for
a better understanding of the device architecture and
operation of the peripheral modules.
The PIC16C72 belongs to the Mid-Range family of the
PIC devices. A block diagram of the device is shown in
Figure 1-1.
The program memory contains 2K words which trans-
late to 2048 instructions, since each 14-bit program
memory word is the same width as each device instruc-
tion. The data memory (RAM) contains 128 bytes.
There are also 22 I/O pins that are user-configurable on
a pin-to-pin basis. Some pins are multiplexed with other
device functions. These functions include:
• External interrupt
• Change on PORTB interrupt
• Timer0 clock input
• Timer1 clock/oscillator
• Capture/Compare/PWM
• A/D converter
• SPI/I
2
C
Table 1-1 details the pinout of the device with descrip-
tions and details for each pin.
FIGURE 1-1:
PIC16C72/CR72 BLOCK DIAGRAM
EPROM/
Program
Memory
2K x 14
13
Data Bus
8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
RAM
File
Registers
128 x 8
Direct Addr
7
RAM Addr
(1)
9
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
W reg
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
MCLR
V
DD
, V
SS
Timer0
A/D
Synchronous
Serial Port
PORTA
PORTB
PORTC
RB0/INT
RB7:RB1
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6
RC7
8
8
Brown-out
Reset
Note 1:
Higher order bits are from the STATUS register.
CCP1
Timer1
Timer2
RA4/T0CKI
RA5/SS/AN4
RA3/AN3/V
REF
RA2/AN2
RA1/AN1
RA0/AN0
8
3
ROM
PIC16C72 Series
DS39016B-page 4
Preliminary
1998-2013 Microchip Technology Inc.
TABLE 1-1
PIC16C72/CR72 PINOUT DESCRIPTION
Pin Name
Pin#
I/O/P
Type
Buffer
Type
Description
OSC1/CLKIN
9
I
ST/CMOS
(3)
Oscillator crystal input/external clock source input.
OSC2/CLKOUT
10
O
—
Oscillator crystal output. Connects to crystal or resonator in crystal
oscillator mode. In RC mode, the OSC2 pin outputs CLKOUT which
has 1/4 the frequency of OSC1, and denotes the instruction cycle rate.
MCLR/V
PP
1
I/P
ST
Master clear (reset) input or programming voltage input. This pin is an
active low reset to the device.
PORTA is a bi-directional I/O port.
RA0/AN0
2
I/O
TTL
RA0 can also be analog input0.
RA1/AN1
3
I/O
TTL
RA1 can also be analog input1.
RA2/AN2
4
I/O
TTL
RA2 can also be analog input2.
RA3/AN3/V
REF
5
I/O
TTL
RA3 can also be analog input3 or analog reference voltage
RA4/T0CKI
6
I/O
ST
RA4 can also be the clock input to the Timer0 module. Output is
open drain type.
RA5/SS/AN4
7
I/O
TTL
RA5 can also be analog input4 or the slave select for the
synchronous serial port.
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
RB0/INT
21
I/O
TTL/ST
(1)
RB0 can also be the external interrupt pin.
RB1
22
I/O
TTL
RB2
23
I/O
TTL
RB3
24
I/O
TTL
RB4
25
I/O
TTL
Interrupt on change pin.
RB5
26
I/O
TTL
Interrupt on change pin.
RB6
27
I/O
TTL/ST
(2)
Interrupt on change pin. Serial programming clock.
RB7
28
I/O
TTL/ST
(2)
Interrupt on change pin. Serial programming data.
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI
11
I/O
ST
RC0 can also be the Timer1 oscillator output or Timer1 clock
input.
RC1/T1OSI
12
I/O
ST
RC1 can also be the Timer1 oscillator input.
RC2/CCP1
13
I/O
ST
RC2 can also be the Capture1 input/Compare1 output/PWM1
output.
RC3/SCK/SCL
14
I/O
ST
RC3 can also be the synchronous serial clock input/output for both
SPI and I
2
C modes.
RC4/SDI/SDA
15
I/O
ST
RC4 can also be the SPI Data In (SPI mode) or
data I/O (I
2
C mode).
RC5/SDO
16
I/O
ST
RC5 can also be the SPI Data Out (SPI mode).
RC6
17
I/O
ST
RC7
18
I/O
ST
V
SS
8, 19
P
—
Ground reference for logic and I/O pins.
V
DD
20
P
—
Positive supply for logic and I/O pins.
Legend: I = input
O = output
I/O = input/output
P = power
— = Not used
TTL = TTL input
ST = Schmitt Trigger input
Note 1:
This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3:
This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise
.
PIC16C72 Series
1998-2013 Microchip Technology Inc.
Preliminary
DS39016B-page 5
2.0
MEMORY ORGANIZATION
There are two memory blocks in PIC16C72 Series
devices. These are the program memory and the data
memory. Each block has its own bus, so that access to
both blocks can occur during the same oscillator cycle.
The data memory can further be broken down into the
general purpose RAM and the Special Function
Registers (SFRs). The operation of the SFRs that
control the “core” are described here. The SFRs used
to control the peripheral modules are described in the
section discussing each individual peripheral module.
Additional information on device memory may be found
in the PIC
®
Mid-Range Reference Manual, DS33023.
2.1
Program Memory Organization
PIC16C72 Series devices have a 13-bit program coun-
ter capable of addressing a 2K x 14 program memory
space. The address range for this program memory is
0000h - 07FFh. Accessing a location above the physi-
cally implemented address will cause a wraparound.
The reset vector is at 0000h and the interrupt vector is
at 0004h.
FIGURE 2-1:
PROGRAM MEMORY MAP
AND STACK
PC<12:0>
13
0000h
0004h
0005h
07FFh
1FFFh
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
On-chip Program
Memory
CALL, RETURN
RETFIE, RETLW
0800h
U
s
e
r Me
mo
ry
Spa
c
e
PIC16C72 Series
DS39016B-page 6
Preliminary
1998-2013 Microchip Technology Inc.
2.2
Data Memory Organization
The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 and RP0 are the
bank select bits.
= 00
Bank0
= 01
Bank1
= 10
Bank2 (not implemented)
= 11
Bank3 (not implemented)
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers, implemented as
static RAM.
All implemented banks contain special function regis-
ters. Some “high use” special function registers from
one bank may be mirrored in another bank for code
reduction and quicker access (ex; the STATUS register
is in Bank 0 and Bank 1).
2.2.1
GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly or indi-
rectly through the File Select Register FSR
(Section 2.5).
FIGURE 2-2:
REGISTER FILE MAP
RP1*
RP0
(STATUS<6:5>)
*
Maintain this bit clear to ensure upward com-
patibility with future products.
INDF
(1)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
ADRES
ADCON0
INDF
(1)
OPTION
PCL
STATUS
FSR
TRISA
TRISB
TRISC
PCLATH
INTCON
PIE1
PCON
PR2
SSPADD
SSPSTAT
ADCON1
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
20h
A0h
General
Purpose
Register
General
Purpose
Register
7Fh
FFh
Bank 0
Bank 1
File
Address
BFh
C0h
Unimplemented data memory locations, read as '0'.
Note 1:
Not a physical register.
File
Address
PIC16C72 Series
1998-2013 Microchip Technology Inc.
Preliminary
DS39016B-page 7
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM.
The special function registers can be classified into two
sets (core and peripheral). Those registers associated
with the “core” functions are described in this section,
and those related to the operation of the peripheral fea-
tures are described in the section of that peripheral fea-
ture.
TABLE 2-1
SPECIAL FUNCTION REGISTER SUMMARY
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
(3)
Bank 0
00h
(1)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
0000 0000
01h
TMR0
Timer0 module’s register
xxxx xxxx
uuuu uuuu
02h
(1)
PCL
Program Counter's (PC) Least Significant Byte
0000 0000
0000 0000
03h
(1)
STATUS
IRP
(4)
RP1
(4)
RP0
TO
PD
Z
DC
C
0001 1xxx
000q quuu
04h
(1)
FSR
Indirect data memory address pointer
xxxx xxxx
uuuu uuuu
05h
PORTA
—
—
PORTA Data Latch when written: PORTA pins when read
--0x 0000
--0u 0000
06h
PORTB
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx
uuuu uuuu
07h
PORTC
PORTC Data Latch when written: PORTC pins when read
xxxx xxxx
uuuu uuuu
08h
—
Unimplemented
—
—
09h
—
Unimplemented
—
—
0Ah
(1,2)
PCLATH
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
---0 0000
0Bh
(1)
INTCON
GIE PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
0Ch
PIR1
—
ADIF
—
—
SSPIF
CCP1IF
TMR2IF
TMR1IF
-0-- 0000
-0-- 0000
0Dh
—
Unimplemented
—
—
0Eh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
xxxx xxxx
uuuu uuuu
0Fh
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx
uuuu uuuu
10h
T1CON
—
—
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
--00 0000
--uu uuuu
11h
TMR2
Timer2 module’s register
0000 0000
0000 0000
12h
T2CON
—
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
-000 0000
-000 0000
13h
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx
uuuu uuuu
14h
SSPCON
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000
0000 0000
15h
CCPR1L
Capture/Compare/PWM Register (LSB)
xxxx xxxx
uuuu uuuu
16h
CCPR1H
Capture/Compare/PWM Register (MSB)
xxxx xxxx
uuuu uuuu
17h
CCP1CON
—
—
CCP1X
CCP1Y
CCP1M3
CCP1M2
CCP1M1
CCP1M0
--00 0000
--00 0000
18h-1Dh
—
Unimplemented
—
—
1Eh
ADRES
A/D Result Register
xxxx xxxx
uuuu uuuu
1Fh
ADCON0
ADCS1
ADCS0
CHS2
CHS1
CHS0
GO/DONE
—
ADON
0000 00-0
0000 00-0
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1:
These registers can be addressed from either bank.
2:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-
tents are transferred to the upper byte of the program counter.
3:
Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
4:
The IRP and RP1 bits are reserved on the PIC16C72/CR72. Always maintain these bits clear.
5:
SSPSTAT<7:6> are not implemented on the PIC16C72, read as '0'.
PIC16C72 Series
DS39016B-page 8
Preliminary
1998-2013 Microchip Technology Inc.
Bank 1
80h
(1)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
0000 0000
81h
OPTION_REG
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
82h
(1)
PCL
Program Counter's (PC) Least Significant Byte
0000 0000
0000 0000
83h
(1)
STATUS
IRP
(4)
RP1
(4)
RP0
TO
PD
Z
DC
C
0001 1xxx
000q quuu
84h
(1)
FSR
Indirect data memory address pointer
xxxx xxxx
uuuu uuuu
85h
TRISA
—
—
PORTA Data Direction Register
--11 1111
--11 1111
86h
TRISB
PORTB Data Direction Register
1111 1111
1111 1111
87h
TRISC
PORTC Data Direction Register
1111 1111
1111 1111
88h
—
Unimplemented
—
—
89h
—
Unimplemented
—
—
8Ah
(1,2)
PCLATH
—
—
—
Write Buffer for the upper 5 bits of the PC
---0 0000
---0 0000
8Bh
(1)
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
8Ch
PIE1
—
ADIE
—
—
SSPIE
CCP1IE
TMR2IE
TMR1IE
-0-- 0000
-0-- 0000
8Dh
—
Unimplemented
—
—
8Eh
PCON
—
—
—
—
—
—
POR
BOR
---- --uu
8Fh
—
Unimplemented
—
—
90h
—
Unimplemented
—
—
91h
—
Unimplemented
—
—
92h
PR2
Timer2 Period Register
1111 1111
1111 1111
93h
SSPADD
Synchronous Serial Port (I
2
C mode) Address Register
0000 0000
0000 0000
94h
SSPSTAT
SMP
(5)
CKE
(5)
D/A
P
S
R/W
UA
BF
0000 0000
0000 0000
95h
—
Unimplemented
—
—
96h
—
Unimplemented
—
—
97h
—
Unimplemented
—
—
98h
—
Unimplemented
—
—
99h
—
Unimplemented
—
—
9Ah
—
Unimplemented
—
—
9Bh
—
Unimplemented
—
—
9Ch
—
Unimplemented
—
—
9Dh
—
Unimplemented
—
—
9Eh
—
Unimplemented
—
—
9Fh
ADCON1
—
—
—
—
—
PCFG2
PCFG1
PCFG0
---- -000 ---- -000
TABLE 2-1
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
(3)
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1:
These registers can be addressed from either bank.
2:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-
tents are transferred to the upper byte of the program counter.
3:
Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
4:
The IRP and RP1 bits are reserved on the PIC16C72/CR72. Always maintain these bits clear.
5:
SSPSTAT<7:6> are not implemented on the PIC16C72, read as '0'.
PIC16C72 Series
1998-2013 Microchip Technology Inc.
Preliminary
DS39016B-page 9
2.2.2.1
STATUS REGISTER
The STATUS register, shown in Figure 2-3, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF
and MOVWF instructions are used to alter the
STATUS register because these instructions do not
affect the Z, C or DC bits from the STATUS register. For
other instructions, not affecting any status bits, see the
"Instruction Set Summary."
FIGURE 2-3:
STATUS REGISTER (ADDRESS 03h, 83h)
Note 1: These devices do not use bits IRP and
RP1 (STATUS<7:6>). Maintain these bits
clear to ensure upward compatibility with
future products.
Note 2: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in sub-
traction. See the SUBLW and SUBWF
instructions for examples.
R/W-0
R/W-0
R/W-0
R-1
R-1
R/W-x
R/W-x
R/W-x
IRP
RP1
RP0
TO
PD
Z
DC
C
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7
bit0
bit 7:
IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)
11
= Bank 3 (180h - 1FFh)
10
= Bank 2 (100h - 17Fh)
01
= Bank 1 (80h - FFh)
00
= Bank 0 (00h - 7Fh)
Each bank is 128 bytes. For devices with only Bank0 and Bank1, the IRP bit is reserved. Always maintain
this bit clear.
bit 4:
TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3:
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2:
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1:
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0:
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of
the source register.
PIC16C72 Series
DS39016B-page 10
Preliminary
1998-2013 Microchip Technology Inc.
2.2.2.2
OPTION_REG REGISTER
The OPTION_REG register is a readable and writable
register which contains various control bits to configure
the TMR0 prescaler/WDT postscaler (single assign-
able register known also as the prescaler), the External
INT Interrupt, TMR0, and the weak pull-ups on PORTB.
FIGURE 2-4:
OPTION_REG REGISTER
(ADDRESS 81h)
Note:
To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
R
= Readable bit
W = Writable bit
U
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7
bit0
bit 7:
RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6:
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5:
T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4:
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3:
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0: PS2:PS0: Prescaler Rate Select bits
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value
TMR0 Rate
WDT Rate