Features
•
High Performance, Low Power AVR
®
8-Bit Microcontroller
•
Advanced RISC Architecture
– 120 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Throughput at 20 MHz
•
Data and Non-volatile Program and Data Memories
– 2/4K Bytes of In-System Self Programmable Flash
• Endurance 10,000 Write/Erase Cycles
– 128/256 Bytes In-System Programmable EEPROM
• Endurance: 100,000 Write/Erase Cycles
– 128/256 Bytes Internal SRAM
– Programming Lock for Flash Program and EEPROM Data Security
•
Peripheral Features
– One 8-bit Timer/Counter with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare and Capture Modes
– Four PWM Channels
– On-chip Analog Comparator
– Programmable Watchdog Timer with On-chip Oscillator
– USI – Universal Serial Interface
– Full Duplex USART
•
Special Microcontroller Features
– debugWIRE On-chip Debugging
– In-System Programmable via SPI Port
– External and Internal Interrupt Sources
– Low-power Idle, Power-down, and Standby Modes
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit
– Internal Calibrated Oscillator
•
I/O and Packages
– 18 Programmable I/O Lines
– 20-pin PDIP, 20-pin SOIC, 20-pad MLF/VQFN
•
Operating Voltage
– 1.8 – 5.5V
•
Speed Grades
– 0 – 4 MHz @ 1.8 – 5.5V
– 0 – 10 MHz @ 2.7 – 5.5V
– 0 – 20 MHz @ 4.5 – 5.5V
•
Industrial Temperature Range: -40
°
C to +85
°
C
•
Low Power Consumption
– Active Mode
• 190 µA at 1.8V and 1MHz
– Idle Mode
• 24 µA at 1.8V and 1MHz
– Power-down Mode
• 0.1 µA at 1.8V and +25
°
C
8-bit
Microcontroller
with 2/4K Bytes
In-System
Programmable
Flash
ATtiny2313A
ATtiny4313
Summary
Rev. 8246BS–AVR–09/11
2
8246BS–AVR–09/11
ATtiny2313A/4313
1.
Pin Configurations
Figure 1-1.
Pinout ATtiny2313A/4313
(PCINT10/RESET/dW) PA2
(PCINT11/RXD) PD0
(PCINT12/TXD) PD1
(PCINT9/XTAL2) PA1
(PCINT8/CLKI/XTAL1) PA0
(PCINT13/CKOUT/XCK/INT0) PD2
(PCINT14/INT1) PD3
(PCINT15/T0) PD4
(PCINT16/OC0B/T1) PD5
GND
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
VCC
PB7 (USCK/SCL/SCK/PCINT7)
PB6 (MISO/DO/PCINT6)
PB5 (MOSI/DI/SDA/PCINT5)
PB4 (OC1B/PCINT4)
PB3 (OC1A/PCINT3)
PB2 (OC0A/PCINT2)
PB1 (AIN1/PCINT1)
PB0 (AIN0/PCINT0)
PD6 (ICPI/PCINT17)
PDIP/SOIC
1
2
3
4
5
MLF/VQFN
15
14
13
12
11
20
19
18
17
16
6
7
8
9
10
(PCINT12/TXD) PD1
(PCINT9/XTAL2) PA1
(PCINT8/CLKI/XTAL1) PA0
(PCINT13/CKOUT/XCK/INT0) PD2
(PCINT14/INT1) PD3
(PCINT15/T0) PD4
(PCINT16/OC0B/T1) PD5
GND
(PCINT17/ICPI) PD6
(AIN0/PCINT0) PB0
PB5 (MOSI/DI/SDA/PCINT5)
PB4 (OC1B/PCINT4)
PB3 (OC1A/PCINT3)
PB2 (OC0A/PCINT2)
PB1 (AIN1/PCINT1)
PD0 (RXD/PCINT1
1)
P
A2 (RESET/dW/PCINT10)
VCC
PB7 (USCK/SCL/SCK/PCINT7)
PB6 (MISO/DO/PCINT6)
NOTE: Bottom pad should be soldered to ground.
3
8246BS–AVR–09/11
ATtiny2313A/4313
1.1
Pin Descriptions
1.1.1
VCC
Digital supply voltage.
1.1.2
GND
Ground.
1.1.3
Port A (PA2..PA0)
Port A is a 3-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port A output buffers have symmetrical drive characteristics with both high sink and source
capability, except PA2 which has the RESET capability. To use pin PA2 as I/O pin, instead of
RESET pin, program (“0”) RSTDISBL fuse. As inputs, Port A pins that are externally pulled low
will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
Port A also serves the functions of various special features of the ATtiny2313A/4313 as listed on
page 61
.
1.1.4
Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B also serves the functions of various special features of the ATtiny2313A/4313 as listed on
page 62
.
1.1.5
Port D (PD6..PD0)
Port D is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port D also serves the functions of various special features of the ATtiny2313A/4313 as listed on
page 66
.
1.1.6
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running and provided that the reset pin has not been disabled. The
minimum pulse length is given in
Table 22-3 on page 201
. Shorter pulses are not guaranteed to
generate a reset. The Reset Input is an alternate function for PA2 and dW.
The reset pin can also be used as a (weak) I/O pin.
1.1.7
XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. XTAL1
is an alternate function for PA0.
4
8246BS–AVR–09/11
ATtiny2313A/4313
1.1.8
XTAL2
Output from the inverting Oscillator amplifier. XTAL2 is an alternate function for PA1.
5
8246BS–AVR–09/11
ATtiny2313A/4313
2.
Overview
The ATtiny2313A/4313 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced
RISC architecture. By executing powerful instructions in a single clock cycle, the
ATtiny2313A/4313 achieves throughputs approaching 1 MIPS per MHz allowing the system
designer to optimize power consumption versus processing speed.
2.1
Block Diagram
Figure 2-1.
Block Diagram
PROGRAM
COUNTER
PROGRAM
FLASH
INSTRUCTION
REGISTER
GND
VCC
INSTRUCTION
DECODER
CONTROL
LINES
STACK
POINTER
SRAM
GENERAL
PURPOSE
REGISTER
ALU
STATUS
REGISTER
PROGRAMMING
LOGIC
SPI
8-BIT DATA BUS
XTAL1
XTAL2
RESET
INTERNAL
OSCILLATOR
OSCILLATOR
WATCHDOG
TIMER
TIMING AND
CONTROL
MCU CONTROL
REGISTER
MCU STATUS
REGISTER
TIMER/
COUNTERS
INTERRUPT
UNIT
EEPROM
USI
USART
ANALOG
COMP
ARA
T
O
R
DATA REGISTER
PORTB
DATA DIR.
REG. PORTB
DATA REGISTER
PORTA
DATA DIR.
REG. PORTA
PORTB DRIVERS
PB0 - PB7
PORTA DRIVERS
PA0 - PA2
DATA REGISTER
PORTD
DATA DIR.
REG. PORTD
PORTD DRIVERS
PD0 - PD6
ON-CHIP
DEBUGGER
INTERNAL
CALIBRATED
OSCILLATOR
6
8246BS–AVR–09/11
ATtiny2313A/4313
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
The ATtiny2313A/4313 provides the following features: 2/4K bytes of In-System Programmable
Flash, 128/256 bytes EEPROM, 128/256 bytes SRAM, 18 general purpose I/O lines, 32 general
purpose working registers, a single-wire Interface for On-chip Debugging, two flexible
Timer/Counters with compare modes, internal and external interrupts, a serial programmable
USART, Universal Serial Interface with Start Condition Detector, a programmable Watchdog
Timer with internal Oscillator, and three software selectable power saving modes. The Idle mode
stops the CPU while allowing the SRAM, Timer/Counters, and interrupt system to continue func-
tioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling
all other chip functions until the next interrupt or hardware reset. In Standby mode, the crys-
tal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast
start-up combined with low-power consumption.
The device is manufactured using Atmel’s high density non-volatile memory technology. The
On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI
serial interface, or by a conventional non-volatile memory programmer. By combining an 8-bit
RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel
ATtiny2313A/4313 is a powerful microcontroller that provides a highly flexible and cost effective
solution to many embedded control applications.
The ATtiny2313A/4313 AVR is supported with a full suite of program and system development
tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emu-
lators, and Evaluation kits.
2.2
Comparison Between ATtiny2313A and ATtiny4313
The ATtiny2313A and ATtiny4313 differ only in memory sizes.
Table 2-1
summarizes the differ-
ent memory sizes for the two devices.
Table 2-1.
Memory Size Summary
Device
Flash
EEPROM
RAM
ATtiny2313A
2K Bytes
128 Bytes
128 Bytes
ATtiny4313
4K Bytes
256 Bytes
256 Bytes
7
8246BS–AVR–09/11
ATtiny2313A/4313
3.
About
3.1
Resources
A comprehensive set of drivers, application notes, data sheets and descriptions on development
tools are available for download at http://www.atmel.com/avr.
3.2
Code Examples
This documentation contains simple code examples that briefly show how to use various parts of
the device. These code examples assume that the part specific header file is included before
compilation. Be aware that not all C compiler vendors include bit definitions in the header files
and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-
tation for more details.
For I/O Registers located in the extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”
instructions must be replaced with instructions that allow access to extended I/O. Typically, this
means “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. Note that not all
AVR devices include an extended I/O map.
3.3
Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less
than 1 PPM over 20 years at 85°C or 100 years at 25°C.
8
8246BS–AVR–09/11
ATtiny2313A/4313
4.
Register Summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
0x3F (0x5F)
SREG
I
T
H
S
V
N
Z
C
9
0x3E (0x5E)
Reserved
–
–
–
–
–
–
–
–
0x3D (0x5D)
SPL
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
12
0x3C (0x5C)
OCR0B
Timer/Counter0 – Compare Register B
85
0x3B (0x5B)
GIMSK
INT1
INT0
PCIE0
PCIE2
PCIE1
–
–
–
50
0x3A (0x5A)
GIFR
INTF1
INTF0
PCIF0
PCIF2
PCIF1
–
–
–
51
0x39 (0x59)
TIMSK
TOIE1
OCIE1A
OCIE1B
–
ICIE1
OCIE0B
TOIE0
OCIE0A
86, 115
0x38 (0x58)
TIFR
TOV1
OCF1A
OCF1B
–
ICF1
OCF0B
TOV0
OCF0A
86, 115
0x37 (0x57)
SPMCSR
–
–
RSIG
CTPB
RFLB
PGWRT
PGERS
SPMEN
175
0x36 (0x56)
OCR0A
Timer/Counter0 – Compare Register A
85
0x35 (0x55)
MCUCR
PUD
SM1
SE
SM0
ISC11
ISC10
ISC01
ISC00
36, 50, 68
0x34 (0x54)
MCUSR
–
–
–
–
WDRF
BORF
EXTRF
PORF
44
0x33 (0x53)
TCCR0B
FOC0A
FOC0B
–
–
WGM02
CS02
CS01
CS00
84
0x32 (0x52)
TCNT0
Timer/Counter0 (8-bit)
85
0x31 (0x51)
OSCCAL
–
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
31
0x30 (0x50)
TCCR0A
COM0A1
COM0A0
COM0B1
COM0B0
–
–
WGM01
WGM00
81
0x2F (0x4F)
TCCR1A
COM1A1
COM1A0
COM1B1
COM1B0
–
–
WGM11
WGM10
110
0x2E (0x4E)
TCCR1B
ICNC1
ICES1
–
WGM13
WGM12
CS12
CS11
CS10
112
0x2D (0x4D)
TCNT1H
Timer/Counter1 – Counter Register High Byte
114
0x2C (0x4C)
TCNT1L
Timer/Counter1 – Counter Register Low Byte
114
0x2B (0x4B)
OCR1AH
Timer/Counter1 – Compare Register A High Byte
114
0x2A (0x4A)
OCR1AL
Timer/Counter1 – Compare Register A Low Byte
114
0x29 (0x49)
OCR1BH
Timer/Counter1 – Compare Register B High Byte
114
0x28 (0x48)
OCR1BL
Timer/Counter1 – Compare Register B Low Byte
114
0x27 (0x47)
Reserved
–
–
–
–
–
–
–
–
0x26 (0x46)
CLKPR
CLKPCE
–
–
–
CLKPS3
CLKPS2
CLKPS1
CLKPS0
31
0x25 (0x45)
ICR1H
Timer/Counter1 - Input Capture Register High Byte
114
0x24 (0x44)
ICR1L
Timer/Counter1 - Input Capture Register Low Byte
114
0x23 (0x43)
GTCCR
–
–
–
–
–
–
–
PSR10
118
0x22 (ox42)
TCCR1C
FOC1A
FOC1B
–
–
–
–
–
–
113
0x21 (0x41)
WDTCSR
WDIF
WDIE
WDP3
WDCE
WDE
WDP2
WDP1
WDP0
44
0x20 (0x40)
PCMSK0
PCINT7
PCINT6
PCINT5
PCINT4
PCINT3
PCINT2
PCINT1
PCINT0
53
0x1F (0x3F)
Reserved
–
–
–
–
–
–
–
–
0x1E (0x3E)
EEAR
–
EEPROM Address Register
23
0x1D (0x3D)
EEDR
EEPROM Data Register
23
0x1C (0x3C)
EECR
–
–
EEPM1
EEPM0
EERIE
EEMPE
EEPE
EERE
23
0x1B (0x3B)
PORTA
–
–
–
–
–
PORTA2
PORTA1
PORTA0
68
0x1A (0x3A)
DDRA
–
–
–
–
–
DDA2
DDA1
DDA0
68
0x19 (0x39)
PINA
–
–
–
–
–
PINA2
PINA1
PINA0
69
0x18 (0x38)
PORTB
PORTB7
PORTB6
PORTB5
PORTB4
PORTB3
PORTB2
PORTB1
PORTB0
69
0x17 (0x37)
DDRB
DDB7
DDB6
DDB5
DDB4
DDB3
DDB2
DDB1
DDB0
69
0x16 (0x36)
PINB
PINB7
PINB6
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
69
0x15 (0x35)
GPIOR2
General Purpose I/O Register 2
24
0x14 (0x34)
GPIOR1
General Purpose I/O Register 1
24
0x13 (0x33)
GPIOR0
General Purpose I/O Register 0
24
0x12 (0x32)
PORTD
–
PORTD6
PORTD5
PORTD4
PORTD3
PORTD2
PORTD1
PORTD0
69
0x11 (0x31)
DDRD
–
DDD6
DDD5
DDD4
DDD3
DDD2
DDD1
DDD0
69
0x10 (0x30)
PIND
–
PIND6
PIND5
PIND4
PIND3
PIND2
PIND1
PIND0
69
0x0F (0x2F)
USIDR
USI Data Register
165
0x0E (0x2E)
USISR
USISIF
USIOIF
USIPF
USIDC
USICNT3
USICNT2
USICNT1
USICNT0
164
0x0D (0x2D)
USICR
USISIE
USIOIE
USIWM1
USIWM0
USICS1
USICS0
USICLK
USITC
162
0x0C (0x2C)
UDR
UART Data Register (8-bit)
136
0x0B (0x2B)
UCSRA
RXC
TXC
UDRE
FE
DOR
UPE
U2X
MPCM
137
0x0A (0x2A)
UCSRB
RXCIE
TXCIE
UDRIE
RXEN
TXEN
UCSZ2
RXB8
TXB8
138
0x09 (0x29)
UBRRL
UBRRH[7:0]
140
0x08 (0x28)
ACSR
ACD
ACBG
ACO
ACI
ACIE
ACIC
ACIS1
ACIS0
167
0x07 (0x27)
BODCR
–
–
–
–
–
–
BODS
BODSE
37
0x06 (0x26)
PRR
–
–
–
–
PRTIM1
PRTIM0
PRUSI
PRUSART
36
0x05 (0x25)
PCMSK2
–
PCINT17
PCINT16
PCINT15
PCINT14
PCINT13
PCINT12
PCINT11
52
0x04 (0x24)
PCMSK1
–
–
–
–
–
PCINT10
PCINT9
PCINT8
52
0x03 (0x23)
UCSRC
UMSEL1
UMSEL0
UPM1
UPM0
USBS
UCSZ1
UCSZ0
UCPOL
139
0x02 (0x22)
UBRRH
–
–
–
–
UBRRH[11:8]
140
0x01 (0x21)
DIDR
–
–
–
–
–
–
AIN1D
AIN0D
168
0x00 (0x20)
USIBR
USI Buffer Register
166
9
8246BS–AVR–09/11
ATtiny2313A/4313
Notes:
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses.
10
8246BS–AVR–09/11
ATtiny2313A/4313
5.
Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
Rd, Rr
Add two Registers
Rd
←
Rd + Rr
Z,C,N,V,H
1
ADC
Rd, Rr
Add with Carry two Registers
Rd
←
Rd + Rr + C
Z,C,N,V,H
1
ADIW
Rdl,K
Add Immediate to Word
Rdh:Rdl
←
Rdh:Rdl + K
Z,C,N,V,S
2
SUB
Rd, Rr
Subtract two Registers
Rd
←
Rd - Rr
Z,C,N,V,H
1
SUBI
Rd, K
Subtract Constant from Register
Rd
←
Rd - K
Z,C,N,V,H
1
SBC
Rd, Rr
Subtract with Carry two Registers
Rd
←
Rd - Rr - C
Z,C,N,V,H
1
SBCI
Rd, K
Subtract with Carry Constant from Reg.
Rd
←
Rd - K - C
Z,C,N,V,H
1
SBIW
Rdl,K
Subtract Immediate from Word
Rdh:Rdl
←
Rdh:Rdl - K
Z,C,N,V,S
2
AND
Rd, Rr
Logical AND Registers
Rd
←
Rd
•
Rr
Z,N,V
1
ANDI
Rd, K
Logical AND Register and Constant
Rd
←
Rd
•
K
Z,N,V
1
OR
Rd, Rr
Logical OR Registers
Rd
←
Rd v Rr
Z,N,V
1
ORI
Rd, K
Logical OR Register and Constant
Rd
←
Rd v K
Z,N,V
1
EOR
Rd, Rr
Exclusive OR Registers
Rd
←
Rd
⊕
Rr
Z,N,V
1
COM
Rd
One’s Complement
Rd
←
0xFF
−
Rd
Z,C,N,V
1
NEG
Rd
Two’s Complement
Rd
←
0x00
−
Rd
Z,C,N,V,H
1
SBR
Rd,K
Set Bit(s) in Register
Rd
←
Rd v K
Z,N,V
1
CBR
Rd,K
Clear Bit(s) in Register
Rd
←
Rd
•
(0xFF - K)
Z,N,V
1
INC
Rd
Increment
Rd
←
Rd + 1
Z,N,V
1
DEC
Rd
Decrement
Rd
←
Rd
−
1
Z,N,V
1
TST
Rd
Test for Zero or Minus
Rd
←
Rd
•
Rd
Z,N,V
1
CLR
Rd
Clear Register
Rd
←
Rd
⊕
Rd
Z,N,V
1
SER
Rd
Set Register
Rd
←
0xFF
None
1
BRANCH INSTRUCTIONS
RJMP
k
Relative Jump
PC
←
PC + k + 1
None
2
IJMP
Indirect Jump to (Z)
PC
←
Z
None
2
RCALL
k
Relative Subroutine Call
PC
←
PC + k + 1
None
3
ICALL
Indirect Call to (Z)
PC
←
Z
None
3
RET
Subroutine Return
PC
←
STACK
None
4
RETI
Interrupt Return
PC
←
STACK
I
4
CPSE
Rd,Rr
Compare, Skip if Equal
if (Rd = Rr) PC
←
PC + 2 or 3
None
1/2/3
CP
Rd,Rr
Compare
Rd
−
Rr
Z, N,V,C,H
1
CPC
Rd,Rr
Compare with Carry
Rd
−
Rr
−
C
Z, N,V,C,H
1
CPI
Rd,K
Compare Register with Immediate
Rd
−
K
Z, N,V,C,H
1
SBRC
Rr, b
Skip if Bit in Register Cleared
if (Rr(b)=0) PC
←
PC + 2 or 3
None
1/2/3
SBRS
Rr, b
Skip if Bit in Register is Set
if (Rr(b)=1) PC
←
PC + 2 or 3
None
1/2/3
SBIC
P, b
Skip if Bit in I/O Register Cleared
if (P(b)=0) PC
←
PC + 2 or 3
None
1/2/3
SBIS
P, b
Skip if Bit in I/O Register is Set
if (P(b)=1) PC
←
PC + 2 or 3
None
1/2/3
BRBS
s, k
Branch if Status Flag Set
if (SREG(s) = 1) then PC
←
PC+k + 1
None
1/2
BRBC
s, k
Branch if Status Flag Cleared
if (SREG(s) = 0) then PC
←
PC+k + 1
None
1/2
BREQ
k
Branch if Equal
if (Z = 1) then PC
←
PC + k + 1
None
1/2
BRNE
k
Branch if Not Equal
if (Z = 0) then PC
←
PC + k + 1
None
1/2
BRCS
k
Branch if Carry Set
if (C = 1) then PC
←
PC + k + 1
None
1/2
BRCC
k
Branch if Carry Cleared
if (C = 0) then PC
←
PC + k + 1
None
1/2
BRSH
k
Branch if Same or Higher
if (C = 0) then PC
←
PC + k + 1
None
1/2
BRLO
k
Branch if Lower
if (C = 1) then PC
←
PC + k + 1
None
1/2
BRMI
k
Branch if Minus
if (N = 1) then PC
←
PC + k + 1
None
1/2
BRPL
k
Branch if Plus
if (N = 0) then PC
←
PC + k + 1
None
1/2
BRGE
k
Branch if Greater or Equal, Signed
if (N
⊕
V= 0) then PC
←
PC + k + 1
None
1/2
BRLT
k
Branch if Less Than Zero, Signed
if (N
⊕
V= 1) then PC
←
PC + k + 1
None
1/2
BRHS
k
Branch if Half Carry Flag Set
if (H = 1) then PC
←
PC + k + 1
None
1/2
BRHC
k
Branch if Half Carry Flag Cleared
if (H = 0) then PC
←
PC + k + 1
None
1/2
BRTS
k
Branch if T Flag Set
if (T = 1) then PC
←
PC + k + 1
None
1/2
BRTC
k
Branch if T Flag Cleared
if (T = 0) then PC
←
PC + k + 1
None
1/2
BRVS
k
Branch if Overflow Flag is Set
if (V = 1) then PC
←
PC + k + 1
None
1/2
BRVC
k
Branch if Overflow Flag is Cleared
if (V = 0) then PC
←
PC + k + 1
None
1/2
BRIE
k
Branch if Interrupt Enabled
if ( I = 1) then PC
←
PC + k + 1
None
1/2
BRID
k
Branch if Interrupt Disabled
if ( I = 0) then PC
←
PC + k + 1
None
1/2
BIT AND BIT-TEST INSTRUCTIONS
SBI
P,b
Set Bit in I/O Register
I/O(P,b)
←
1
None
2
CBI
P,b
Clear Bit in I/O Register
I/O(P,b)
←
0
None
2
LSL
Rd
Logical Shift Left
Rd(n+1)
←
Rd(n), Rd(0)
←
0
Z,C,N,V
1
LSR
Rd
Logical Shift Right
Rd(n)
←
Rd(n+1), Rd(7)
←
0
Z,C,N,V
1
ROL
Rd
Rotate Left Through Carry
Rd(0)
←
C,Rd(n+1)
←
Rd(n),C
←
Rd(7)
Z,C,N,V
1