Features
•
High-performance, Low-power AVR
®
8-bit Microcontroller
•
Advanced RISC Architecture
– 130 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-chip 2-cycle Multiplier
•
Nonvolatile Program and Data Memories
– 8K Bytes of In-System Self-Programmable Flash
Endurance: 10,000 Write/Erase Cycles
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– 512 Bytes EEPROM
Endurance: 100,000 Write/Erase Cycles
– 512 Bytes Internal SRAM
– Programming Lock for Software Security
•
Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode
– Real Time Counter with Separate Oscillator
– Four PWM Channels
– 8-channel, 10-bit ADC
8 Single-ended Channels
7 Differential Channels for TQFP Package Only
2 Differential Channels with Programmable Gain at 1x, 10x, or 200x for TQFP
Package Only
– Byte-oriented Two-wire Serial Interface
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
•
Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby
and Extended Standby
•
I/O and Packages
– 32 Programmable I/O Lines
– 40-pin PDIP, 44-lead TQFP, 44-lead PLCC, and 44-pad QFN/MLF
•
Operating Voltages
– 2.7 - 5.5V for ATmega8535L
– 4.5 - 5.5V for ATmega8535
•
Speed Grades
– 0 - 8 MHz for ATmega8535L
– 0 - 16 MHz for ATmega8535
8-bit
Microcontroller
with 8K Bytes
In-System
Programmable
Flash
ATmega8535
ATmega8535L
Summary
2502KS–AVR–10/06
Note: This is a summary document. A complete document
is available on our Web site at www.atmel.com.
2
ATmega8535(L)
2502KS–AVR–10/06
Pin Configurations
Figure 1. Pinout ATmega8535
Disclaimer
Typical values contained in this data sheet are based on simulations and characteriza-
tion of other AVR microcontrollers manufactured on the same process technology. Min
and Max values will be available after the device is characterized.
(XCK/T0) PB0
(T1) PB1
(INT2/AIN0) PB2
(OC0/AIN1) PB3
(SS) PB4
(MOSI) PB5
(MISO) PB6
(SCK) PB7
RESET
VCC
GND
XTAL2
XTAL1
(RXD) PD0
(TXD) PD1
(INT0) PD2
(INT1) PD3
(OC1B) PD4
(OC1A) PD5
(ICP1) PD6
PA0 (ADC0)
PA1 (ADC1)
PA2 (ADC2)
PA3 (ADC3)
PA4 (ADC4)
PA5 (ADC5)
PA6 (ADC6)
PA7 (ADC7)
AREF
GND
AVCC
PC7 (TOSC2)
PC6 (TOSC1)
PC5
PC4
PC3
PC2
PC1 (SDA)
PC0 (SCL)
PD7 (OC2)
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
(MOSI) PB5
(MISO) PB6
(SCK) PB7
RESET
VCC
GND
XTAL2
XTAL1
(RXD) PD0
(TXD) PD1
(INT0) PD2
PA4 (ADC4)
PA5 (ADC5)
PA6 (ADC6)
PA7 (ADC7)
AREF
GND
AVCC
PC7 (TOSC2)
PC6 (TOSC1)
PC5
PC4
44
43
42
41
40
39
38
37
36
35
34
12
13
14
15
16
17
18
19
20
21
22
(INT1) PD3
(OC1B) PD4
(OC1A) PD5
(ICP1) PD6
(OC2) PD7
VCC
GND
(SCL) PC0
(SDA) PC1
PC2
PC3
PB4 (SS)
PB3 (AIN1/OC0)
PB2 (AIN0/INT2)
PB1 (T1)
PB0 (XCK/T0)
GND
VCC
P
A0 (ADC0)
P
A1 (ADC1)
P
A2 (ADC2)
P
A3 (ADC3)
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
(MOSI) PB5
(MISO) PB6
(SCK) PB7
RESET
VCC
GND
XTAL2
XTAL1
(RXD) PD0
(TXD) PD1
(INT0) PD2
PA4 (ADC4)
PA5 (ADC5)
PA6 (ADC6)
PA7 (ADC7)
AREF
GND
AVCC
PC7 (TOSC2)
PC6 (TOSC1)
PC5
PC4
6
5
4
3
2
1
44
43
42
41
40
18
19
20
21
22
23
24
25
26
27
28
(INT1) PD3
(OC1B) PD4
(OC1A) PD5
(ICP1) PD6
(OC2) PD7
VCC
GND
(SCL) PC0
(SDA) PC1
PC2
PC3
PB4 (SS)
PB3 (AIN1/OC0)
PB2 (AIN0/INT2)
PB1 (T1)
PB0 (XCK/T0)
GND
VCC
P
A0 (ADC0)
P
A1 (ADC1)
P
A2 (ADC2)
P
A3 (ADC3)
PLCC
NOTE: MLF Bottom pad should be soldered to ground.
3
ATmega8535(L)
2502KS–AVR–10/06
Overview
The ATmega8535 is a low-power CMOS 8-bit microcontroller based on the AVR
enhanced RISC architecture. By executing instructions in a single clock cycle, the
ATmega8535 achieves throughputs approaching 1 MIPS per MHz allowing the system
designer to optimize power consumption versus processing speed.
Block Diagram
Figure 2. Block Diagram
INTERNAL
OSCILLATOR
OSCILLATOR
WATCHDOG
TIMER
MCU CTRL.
& TIMING
OSCILLATOR
TIMERS/
COUNTERS
INTERRUPT
UNIT
STACK
POINTER
EEPROM
SRAM
STATUS
REGISTER
USART
PROGRAM
COUNTER
PROGRAM
FLASH
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
PROGRAMMING
LOGIC
SPI
ADC
INTERFACE
COMP.
INTERFACE
PORTA DRIVERS/BUFFERS
PORTA DIGITAL INTERFACE
GENERAL
PURPOSE
REGISTERS
X
Y
Z
ALU
+
-
PORTC DRIVERS/BUFFERS
PORTC DIGITAL INTERFACE
PORTB DIGITAL INTERFACE
PORTB DRIVERS/BUFFERS
PORTD DIGITAL INTERFACE
PORTD DRIVERS/BUFFERS
XTAL1
XTAL2
RESET
CONTROL
LINES
V
CC
GND
MUX &
ADC
AREF
PA0 - PA7
PC0 - PC7
PD0 - PD7
PB0 - PB7
AVR CPU
TWI
AVCC
INTERNAL
CALIBRATED
OSCILLATOR
4
ATmega8535(L)
2502KS–AVR–10/06
The AVR core combines a rich instruction set with 32 general purpose working registers.
All 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two
independent registers to be accessed in one single instruction executed in one clock
cycle. The resulting architecture is more code efficient while achieving throughputs up to
ten times faster than conventional CISC microcontrollers.
The ATmega8535 provides the following features: 8K bytes of In-System Programmable
Flash with Read-While-Write capabilities, 512 bytes EEPROM, 512 bytes SRAM, 32
general purpose I/O lines, 32 general purpose working registers, three flexible
Timer/Counters with compare modes, internal and external interrupts, a serial program-
mable USART, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with
optional differential input stage with programmable gain in TQFP package, a program-
mable Watchdog Timer with Internal Oscillator, an SPI serial port, and six software
selectable power saving modes. The Idle mode stops the CPU while allowing the
SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The
Power-down mode saves the register contents but freezes the Oscillator, disabling all
other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the
asynchronous timer continues to run, allowing the user to maintain a timer base while
the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and
all I/O modules except asynchronous timer and ADC, to minimize switching noise during
ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the
rest of the device is sleeping. This allows very fast start-up combined with low-power
consumption. In Extended Standby mode, both the main Oscillator and the asynchro-
nous timer continue to run.
The device is manufactured using Atmel’s high density nonvolatile memory technology.
The On-chip ISP Flash allows the program memory to be reprogrammed In-System
through an SPI serial interface, by a conventional nonvolatile memory programmer, or
by an On-chip Boot program running on the AVR core. The boot program can use any
interface to download the application program in the Application Flash memory. Soft-
ware in the Boot Flash section will continue to run while the Application Flash section is
updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU
with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega8535
is a powerful microcontroller that provides a highly flexible and cost effective solution to
many embedded control applications.
The ATmega8535 AVR is supported with a full suite of program and system develop-
ment tools including: C compilers, macro assemblers, program debugger/simulators, In-
Circuit Emulators, and evaluation kits.
AT90S8535 Compatibility
The ATmega8535 provides all the features of the AT90S8535. In addition, several new
features are added. The ATmega8535 is backward compatible with AT90S8535 in most
cases. However, some incompatibilities between the two microcontrollers exist. To
solve this problem, an AT90S8535 compatibility mode can be selected by programming
the S8535C fuse. ATmega8535 is pin compatible with AT90S8535, and can replace the
AT90S8535 on current Printed Circuit Boards. However, the location of fuse bits and the
electrical characteristics differs between the two devices.
AT90S8535 Compatibility
Mode
Programming the S8535C fuse will change the following functionality:
•
The timed sequence for changing the Watchdog Time-out period is disabled. See
“Timed Sequences for Changing the Configuration of the Watchdog Timer” on page
45 for details.
•
The double buffering of the USART Receive Register is disabled. See “AVR USART
vs. AVR UART – Compatibility” on page 146 for details.
5
ATmega8535(L)
2502KS–AVR–10/06
Pin Descriptions
V
CC
Digital supply voltage.
GND
Ground.
Port A (PA7..PA0)
Port A serves as the analog inputs to the A/D Converter.
Port A also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used.
Port pins can provide internal pull-up resistors (selected for each bit). The Port A output
buffers have symmetrical drive characteristics with both high sink and source capability.
When pins PA0 to PA7 are used as inputs and are externally pulled low, they will source
current if the internal pull-up resistors are activated. The Port A pins are tri-stated when
a reset condition becomes active, even if the clock is not running.
Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port B output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port B pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port B also serves the functions of various special features of the ATmega8535 as listed
on page 60.
Port C (PC7..PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port C output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port C pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port D output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port D pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port D also serves the functions of various special features of the ATmega8535 as listed
on page 64.
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will gener-
ate a reset, even if the clock is not running. The minimum pulse length is given in Table
15 on page 37. Shorter pulses are not guaranteed to generate a reset.
XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting Oscillator amplifier.
AVCC
AVCC is the supply voltage pin for Port A and the A/D Converter. It should be externally
connected to V
CC
, even if the ADC is not used. If the ADC is used, it should be con-
nected to V
CC
through a low-pass filter.
AREF
AREF is the analog reference pin for the A/D Converter.
6
ATmega8535(L)
2502KS–AVR–10/06
Resources
A comprehensive set of development tools, application notes and datasheets are avail-
able for download on http://www.atmel.com/avr.
7
ATmega8535(L)
2502KS–AVR–10/06
About Code
Examples
This documentation contains simple code examples that briefly show how to use various
parts of the device. These code examples assume that the part specific header file is
included before compilation. Be aware that not all C compiler vendors include bit defini-
tions in the header files and interrupt handling in C is compiler dependent. Please
confirm with the C Compiler documentation for more details.
8
ATmega8535(L)
2502KS–AVR–10/06
.
Register Summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
0x3F (0x5F)
SREG
I
T
H
S
V
N
Z
C
10
0x3E (0x5E)
SPH
–
–
–
–
–
–
SP9
SP8
12
0x3D (0x5D)
SPL
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
12
0x3C (0x5C)
OCR0
Timer/Counter0 Output Compare Register
85
0x3B (0x5B)
GICR
INT1
INT0
INT2
–
–
–
IVSEL
IVCE
49, 69
0x3A (0x5A)
GIFR
INTF1
INTF0
INTF2
–
–
–
–
–
70
0x39 (0x59)
TIMSK
OCIE2
TOIE2
TICIE1
OCIE1A
OCIE1B
TOIE1
OCIE0
TOIE0
85, 115, 133
0x38 (0x58)
TIFR
OCF2
TOV2
ICF1
OCF1A
OCF1B
TOV1
OCF0
TOV0
86, 116, 134
0x37 (0x57)
SPMCR
SPMIE
RWWSB
–
RWWSRE
BLBSET
PGWRT
PGERS
SPMEN
228
0x36 (0x56)
TWCR
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
–
TWIE
181
0x35 (0x55)
MCUCR
SM2
SE
SM1
SM0
ISC11
ISC10
ISC01
ISC00
32, 68
0x34 (0x54)
MCUCSR
–
ISC2
–
–
WDRF
BORF
EXTRF
PORF
40, 69
0x33 (0x53)
TCCR0
FOC0
WGM00
COM01
COM00
WGM01
CS02
CS01
CS00
83
0x32 (0x52)
TCNT0
Timer/Counter0 (8 Bits)
85
0x31 (0x51)
OSCCAL
Oscillator Calibration Register
30
0x30 (0x50)
SFIOR
ADTS2
ADTS1
ADTS0
–
ACME
PUD
PSR2
PSR10
59,88,135,203,223
0x2F (0x4F)
TCCR1A
COM1A1
COM1A0
COM1B1
COM1B0
FOC1A
FOC1B
WGM11
WGM10
110
0x2E (0x4E)
TCCR1B
ICNC1
ICES1
–
WGM13
WGM12
CS12
CS11
CS10
113
0x2D (0x4D)
TCNT1H
Timer/Counter1 – Counter Register High Byte
114
0x2C (0x4C)
TCNT1L
Timer/Counter1 – Counter Register Low Byte
114
0x2B (0x4B)
OCR1AH
Timer/Counter1 – Output Compare Register A High Byte
114
0x2A (0x4A)
OCR1AL
Timer/Counter1 – Output Compare Register A Low Byte
114
0x29 (0x49)
OCR1BH
Timer/Counter1 – Output Compare Register B High Byte
114
0x28 (0x48)
OCR1BL
Timer/Counter1 – Output Compare Register B Low Byte
114
0x27 (0x47)
ICR1H
Timer/Counter1 – Input Capture Register High Byte
114
0x26 (0x46)
ICR1L
Timer/Counter1 – Input Capture Register Low Byte
114
0x25 (0x45)
TCCR2
FOC2
WGM20
COM21
COM20
WGM21
CS22
CS21
CS20
128
0x24 (0x44)
TCNT2
Timer/Counter2 (8 Bits)
130
0x23 (0x43)
OCR2
Timer/Counter2 Output Compare Register
131
0x22 (0x42)
ASSR
–
–
–
–
AS2
TCN2UB
OCR2UB
TCR2UB
131
0x21 (0x41)
WDTCR
–
–
–
WDCE
WDE
WDP2
WDP1
WDP0
42
0x20
(1)
(0x40)
(1)
UBRRH
URSEL
–
–
–
UBRR[11:8]
169
UCSRC
URSEL
UMSEL
UPM1
UPM0
USBS
UCSZ1
UCSZ0
UCPOL
167
0x1F (0x3F)
EEARH
–
–
–
–
–
–
–
EEAR8
19
0x1E (0x3E)
EEARL
EEPROM Address Register Low Byte
19
0x1D (0x3D)
EEDR
EEPROM Data Register
19
0x1C (0x3C)
EECR
–
–
–
–
EERIE
EEMWE
EEWE
EERE
19
0x1B (0x3B)
PORTA
PORTA7
PORTA6
PORTA5
PORTA4
PORTA3
PORTA2
PORTA1
PORTA0
66
0x1A (0x3A)
DDRA
DDA7
DDA6
DDA5
DDA4
DDA3
DDA2
DDA1
DDA0
66
0x19 (0x39)
PINA
PINA7
PINA6
PINA5
PINA4
PINA3
PINA2
PINA1
PINA0
66
0x18 (0x38)
PORTB
PORTB7
PORTB6
PORTB5
PORTB4
PORTB3
PORTB2
PORTB1
PORTB0
66
0x17 (0x37)
DDRB
DDB7
DDB6
DDB5
DDB4
DDB3
DDB2
DDB1
DDB0
66
0x16 (0x36)
PINB
PINB7
PINB6
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
67
0x15 (0x35)
PORTC
PORTC7
PORTC6
PORTC5
PORTC4
PORTC3
PORTC2
PORTC1
PORTC0
67
0x14 (0x34)
DDRC
DDC7
DDC6
DDC5
DDC4
DDC3
DDC2
DDC1
DDC0
67
0x13 (0x33)
PINC
PINC7
PINC6
PINC5
PINC4
PINC3
PINC2
PINC1
PINC0
67
0x12 (0x32)
PORTD
PORTD7
PORTD6
PORTD5
PORTD4
PORTD3
PORTD2
PORTD1
PORTD0
67
0x11 (0x31)
DDRD
DDD7
DDD6
DDD5
DDD4
DDD3
DDD2
DDD1
DDD0
67
0x10 (0x30)
PIND
PIND7
PIND6
PIND5
PIND4
PIND3
PIND2
PIND1
PIND0
67
0x0F (0x2F)
SPDR
SPI Data Register
143
0x0E (0x2E)
SPSR
SPIF
WCOL
–
–
–
–
–
SPI2X
143
0x0D (0x2D)
SPCR
SPIE
SPE
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
141
0x0C (0x2C)
UDR
USART I/O Data Register
164
0x0B (0x2B)
UCSRA
RXC
TXC
UDRE
FE
DOR
PE
U2X
MPCM
165
0x0A (0x2A)
UCSRB
RXCIE
TXCIE
UDRIE
RXEN
TXEN
UCSZ2
RXB8
TXB8
166
0x09 (0x29)
UBRRL
USART Baud Rate Register Low Byte
169
0x08 (0x28)
ACSR
ACD
ACBG
ACO
ACI
ACIE
ACIC
ACIS1
ACIS0
203
0x07 (0x27)
ADMUX
REFS1
REFS0
ADLAR
MUX4
MUX3
MUX2
MUX1
MUX0
219
0x06 (0x26)
ADCSRA
ADEN
ADSC
ADATE
ADIF
ADIE
ADPS2
ADPS1
ADPS0
221
0x05 (0x25)
ADCH
ADC Data Register High Byte
222
0x04 (0x24)
ADCL
ADC Data Register Low Byte
222
0x03 (0x23)
TWDR
Two-wire Serial Interface Data Register
183
0x02 (0x22)
TWAR
TWA6
TWA5
TWA4
TWA3
TWA2
TWA1
TWA0
TWGCE
183
0x01 (0x21)
TWSR
TWS7
TWS6
TWS5
TWS4
TWS3
–
TWPS1
TWPS0
183
9
ATmega8535(L)
2502KS–AVR–10/06
Notes:
1. Refer to the USART description for details on how to access UBRRH and UCSRC.
2. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
3. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on
all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions
work with registers 0x00 to 0x1F only.
0x00 (0x20)
TWBR
Two-wire Serial Interface Bit Rate Register
181
Register Summary (Continued)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
10
ATmega8535(L)
2502KS–AVR–10/06
Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
Rd, Rr
Add two Registers
Rd
← Rd + Rr
Z,C,N,V,H
1
ADC
Rd, Rr
Add with Carry two Registers
Rd
← Rd + Rr + C
Z,C,N,V,H
1
ADIW
Rdl,K
Add Immediate to Word
Rdh:Rdl
← Rdh:Rdl + K
Z,C,N,V,S
2
SUB
Rd, Rr
Subtract two Registers
Rd
← Rd - Rr
Z,C,N,V,H
1
SUBI
Rd, K
Subtract Constant from Register
Rd
← Rd - K
Z,C,N,V,H
1
SBC
Rd, Rr
Subtract with Carry two Registers
Rd
← Rd - Rr - C
Z,C,N,V,H
1
SBCI
Rd, K
Subtract with Carry Constant from Reg.
Rd
← Rd - K - C
Z,C,N,V,H
1
SBIW
Rdl,K
Subtract Immediate from Word
Rdh:Rdl
← Rdh:Rdl - K
Z,C,N,V,S
2
AND
Rd, Rr
Logical AND Registers
Rd
← Rd • Rr
Z,N,V
1
ANDI
Rd, K
Logical AND Register and Constant
Rd
← Rd • K
Z,N,V
1
OR
Rd, Rr
Logical OR Registers
Rd
← Rd v Rr
Z,N,V
1
ORI
Rd, K
Logical OR Register and Constant
Rd
← Rd v K
Z,N,V
1
EOR
Rd, Rr
Exclusive OR Registers
Rd
← Rd ⊕ Rr
Z,N,V
1
COM
Rd
One’s Complement
Rd
← 0xFF − Rd
Z,C,N,V
1
NEG
Rd
Two’s Complement
Rd
← 0x00 − Rd
Z,C,N,V,H
1
SBR
Rd,K
Set Bit(s) in Register
Rd
← Rd v K
Z,N,V
1
CBR
Rd,K
Clear Bit(s) in Register
Rd
← Rd • (0xFF - K)
Z,N,V
1
INC
Rd
Increment
Rd
← Rd + 1
Z,N,V
1
DEC
Rd
Decrement
Rd
← Rd − 1
Z,N,V
1
TST
Rd
Test for Zero or Minus
Rd
← Rd • Rd
Z,N,V
1
CLR
Rd
Clear Register
Rd
← Rd ⊕ Rd
Z,N,V
1
SER
Rd
Set Register
Rd
← 0xFF
None
1
MUL
Rd, Rr
Multiply Unsigned
R1:R0
← Rd x Rr
Z,C
2
MULS
Rd, Rr
Multiply Signed
R1:R0
← Rd x Rr
Z,C
2
MULSU
Rd, Rr
Multiply Signed with Unsigned
R1:R0
← Rd x Rr
Z,C
2
FMUL
Rd, Rr
Fractional Multiply Unsigned
R1:R0
← (Rd x Rr)
<< 1
Z,C
2
FMULS
Rd, Rr
Fractional Multiply Signed
R1:R0
← (Rd x Rr)
<< 1
Z,C
2
FMULSU
Rd, Rr
Fractional Multiply Signed with Unsigned
R1:R0
← (Rd x Rr)
<< 1
Z,C
2
BRANCH INSTRUCTIONS
RJMP
k
Relative Jump
PC
← PC + k + 1
None
2
IJMP
Indirect Jump to (Z)
PC
← Z
None
2
RCALL
k
Relative Subroutine Call
PC
← PC + k + 1
None
3
ICALL
Indirect Call to (Z)
PC
← Z
None
3
RET
Subroutine Return
PC
← STACK
None
4
RETI
Interrupt Return
PC
← STACK
I
4
CPSE
Rd,Rr
Compare, Skip if Equal
if (Rd = Rr) PC
← PC + 2 or 3
None
1 / 2 / 3
CP
Rd,Rr
Compare
Rd
− Rr
Z, N,V,C,H
1
CPC
Rd,Rr
Compare with Carry
Rd
− Rr − C
Z, N,V,C,H
1
CPI
Rd,K
Compare Register with Immediate
Rd
− K
Z, N,V,C,H
1
SBRC
Rr, b
Skip if Bit in Register Cleared
if (Rr(b)=0) PC
← PC + 2 or 3
None
1 / 2 / 3
SBRS
Rr, b
Skip if Bit in Register is Set
if (Rr(b)=1) PC
← PC + 2 or 3
None
1 / 2 / 3
SBIC
P, b
Skip if Bit in I/O Register Cleared
if (P(b)=0) PC
← PC + 2 or 3
None
1 / 2 / 3
SBIS
P, b
Skip if Bit in I/O Register is Set
if (P(b)=1) PC
← PC + 2 or 3
None
1 / 2 / 3
BRBS
s, k
Branch if Status Flag Set
if (SREG(s) = 1) then PC
←PC+k + 1
None
1 / 2
BRBC
s, k
Branch if Status Flag Cleared
if (SREG(s) = 0) then PC
←PC+k + 1
None
1 / 2
BREQ
k
Branch if Equal
if (Z = 1) then PC
← PC + k + 1
None
1 / 2
BRNE
k
Branch if Not Equal
if (Z = 0) then PC
← PC + k + 1
None
1 / 2
BRCS
k
Branch if Carry Set
if (C = 1) then PC
← PC + k + 1
None
1 / 2
BRCC
k
Branch if Carry Cleared
if (C = 0) then PC
← PC + k + 1
None
1 / 2
BRSH
k
Branch if Same or Higher
if (C = 0) then PC
← PC + k + 1
None
1 / 2
BRLO
k
Branch if Lower
if (C = 1) then PC
← PC + k + 1
None
1 / 2
BRMI
k
Branch if Minus
if (N = 1) then PC
← PC + k + 1
None
1 / 2
BRPL
k
Branch if Plus
if (N = 0) then PC
← PC + k + 1
None
1 / 2
BRGE
k
Branch if Greater or Equal, Signed
if (N
⊕ V= 0) then PC ← PC + k + 1
None
1 / 2
BRLT
k
Branch if Less Than Zero, Signed
if (N
⊕ V= 1) then PC ← PC + k + 1
None
1 / 2
BRHS
k
Branch if Half Carry Flag Set
if (H = 1) then PC
← PC + k + 1
None
1 / 2
BRHC
k
Branch if Half Carry Flag Cleared
if (H = 0) then PC
← PC + k + 1
None
1 / 2
BRTS
k
Branch if T Flag Set
if (T = 1) then PC
← PC + k + 1
None
1 / 2
BRTC
k
Branch if T Flag Cleared
if (T = 0) then PC
← PC + k + 1
None
1 / 2
BRVS
k
Branch if Overflow Flag is Set
if (V = 1) then PC
← PC + k + 1
None
1 / 2
BRVC
k
Branch if Overflow Flag is Cleared
if (V = 0) then PC
← PC + k + 1
None
1 / 2
BRIE
k
Branch if Interrupt Enabled
if ( I = 1) then PC
← PC + k + 1
None
1 / 2
BRID
k
Branch if Interrupt Disabled
if ( I = 0) then PC
← PC + k + 1
None
1 / 2
DATA TRANSFER INSTRUCTIONS