Features
•
High Performance, Low Power Atmel
®
AVR
®
8-Bit Microcontroller
•
Advanced RISC Architecture
– 130 Powerful Instructions – Most Single Clock Cycle Execution
– 32 × 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-Chip 2-cycle Multiplier
•
High Endurance Non-volatile Memory segments
– 16 Kbytes of In-System Self-programmable Flash program memory
– 512 Bytes EEPROM
– 1 Kbytes Internal SRAM
– Write/Erase cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C
(1)
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– Programming Lock for Software Security
•
JTAG (IEEE std. 1149.1 compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
•
Peripheral Features
– 4 × 25 Segment LCD Driver
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode
– Real Time Counter with Separate Oscillator
– Four PWM Channels
– 8-channel, 10-bit ADC
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Universal Serial Interface with Start Condition Detector
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
•
Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and
Standby
•
I/O and Packages
– 54 Programmable I/O Lines
– 64-lead TQFP, 64-pad QFN/MLF and 64-pad DRQFN
•
Speed Grade:
– ATmega169PV: 0 - 4 MHz @ 1.8V - 5.5V, 0 - 8 MHz @ 2.7V - 5.5V
– ATmega169P: 0 - 8 MHz @ 2.7V - 5.5V, 0 - 16 MHz @ 4.5V - 5.5V
•
Temperature range:
– -40
°
C to 85
°
C Industrial
•
Ultra-Low Power Consumption
– Active Mode:
1 MHz, 1.8V: 330 µA
32 kHz, 1.8V: 10 µA (including Oscillator)
32 kHz, 1.8V: 25 µA (including Oscillator and LCD)
– Power-down Mode:
0.1 µA at 1.8V
– Power-save Mode:
0.6 µA at 1.8V (Including 32 kHz RTC)
8-bit
Microcontroller
with 16K Bytes
In-System
Programmable
Flash
ATmega169P
ATmega169PV
Preliminary
Summary
Rev. 8018PS–AVR–08/10
2
8018PS–AVR–08/10
ATmega169P
1.
Pin Configurations
1.1
Pinout - TQFP/QFN/MLF
Figure 1-1.
64A (TQFP)and 64M1 (QFN/MLF) Pinout ATmega169P
Note:
The large center pad underneath the QFN/MLF packages is made of metal and internally connected to GND. It should be sol-
dered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen
from the board.
64
63
62
47
46
48
45
44
43
42
41
40
39
38
37
36
35
33
34
2
3
1
4
5
6
7
8
9
10
11
12
13
14
16
15
17
61
60
18
59
20
58
19
21
57
22
56
23
55
24
54
25
53
26
52
27
51
29
28
50
49
32
31
30
PC0 (SEG12)
VCC
GND
PF0 (ADC0)
PF7 (ADC7/TDI)
PF1 (ADC1)
PF2 (ADC2)
PF3 (ADC3)
PF4 (ADC4/TCK)
PF5 (ADC5/TMS)
PF6 (ADC6/TDO)
AREF
GND
AVCC
(RXD/PCINT0) PE0
(TXD/PCINT1) PE1
LCDCAP
(XCK/AIN0/PCINT2) PE2
(AIN1/PCINT3) PE3
(USCK/SCL/PCINT4) PE4
(DI/SDA/PCINT5) PE5
(DO/PCINT6) PE6
(CLKO/PCINT7) PE7
(SS/PCINT8) PB0
(SCK/PCINT9) PB1
(MOSI/PCINT10) PB2
(MISO/PCINT11) PB3
(OC0A/PCINT12) PB4
(OC2A/PCINT15) PB7
(T1/SEG24) PG3
(OC1B/PCINT14) PB6
(T0/SEG23) PG4
(OC1A/PCINT13) PB5
PC1 (SEG11)
PG0 (SEG14)
(SEG15) PD7
PC2 (SEG10)
PC3 (SEG9)
PC4 (SEG8)
PC5 (SEG7)
PC6 (SEG6)
PC7 (SEG5)
PA7 (SEG3)
PG2 (SEG4)
PA6 (SEG2)
PA5 (SEG1)
PA4 (SEG0)
PA3 (COM3)
PA0 (COM0)
PA1 (COM1)
PA2 (COM2)
PG1 (SEG13)
(SEG16) PD6
(SEG17) PD5
(SEG18) PD4
(SEG19) PD3
(SEG20) PD2
(INT0/SEG21) PD1
(ICP1/SEG22) PD0
(TOSC1) XTAL1
(TOSC2) XTAL2
RESET/PG5
GND
VCC
INDEX CORNER
3
8018PS–AVR–08/10
ATmega169P
1.2
Pinout - DRQFN
Figure 1-2.
64MC (DRQFN) Pinout ATmega169P
Top view
Bottom view
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
A8
A9
B8
A10
B9
A11
B10
A12
B11
A13
B12
A14
B13
A15
B14
A16
B15
A17
A25
B22
A24
B21
A23
B20
A22
B19
A21
B18
A20
B17
A19
B16
A18
A34
B30
A33
B29
A32
B28
A31
B27
A30
B26
A29
B25
A28
B24
A27
B23
A26
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
A8
A25
B22
A24
B21
A23
B20
A22
B19
A21
B18
A20
B17
A19
B16
A18
A17
B15
A16
B14
A15
B13
A14
B12
A13
B11
A12
B10
A11
B9
A10
B8
A9
A26
B23
A27
B24
A28
B25
A29
B26
A30
B27
A31
B28
A32
B29
A33
B30
A34
Table 1-1.
DRQFN-64 Pinout ATmega169P.
A1
PE0
A9
PB7
A18
PG1 (SEG13)
A26
PA2 (COM2)
B1
VLCDCAP
B8
PB6
B16
PG0 (SEG14)
B23
PA3 (COM3)
A2
PE1
A10
PG3
A19
PC0 (SEG12)
A27
PA1 (COM1)
B2
PE2
B9
PG4
B17
PC1 (SEG11)
B24
PA0 (COM0)
A3
PE3
A11
RESET
A20
PC2 (SEG10)
A28
VCC
B3
PE4
B10
VCC
B18
PC3 (SEG9)
B25
GND
A4
PE5
A12
GND
A21
PC4 (SEG8)
A29
PF7
B4
PE6
B11
XTAL2 (TOSC2)
B19
PC5 (SEG7)
B26
PF6
A5
PE7
A13
XTAL1 (TOSC1)
A22
PC6 (SEG6)
A30
PF5
B5
PB0
B12
PD0 (SEG22)
B20
PC7 (SEG5)
B27
PF4
A6
PB1
A14
PD1 (SEG21)
A23
PG2 (SEG4)
A31
PF3
B6
PB2
B13
PD2 (SEG20)
B21
PA7 (SEG3)
B28
PF2
A7
PB3
A15
PD3 (SEG19)
A24
PA6 (SEG2)
A32
PF1
B7
PB5
B14
PD4 (SEG18)
B22
PA4 (SEG0)
B29
PF0
A8
PB4
A16
PD5 (SEG17)
A25
PA5 (SEG1)
A33
AREF
B15
PD7 (SEG15)
B30
AVCC
A17
PD6 (SEG16)
A34
GND
4
8018PS–AVR–08/10
ATmega169P
2.
Overview
The ATmega169P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By execut-
ing powerful instructions in a single clock cycle, the ATmega169P achieves throughputs approaching 1 MIPS per MHz
allowing the system designer to optimize power consumption versus processing speed.
2.1
Block Diagram
Figure 2-1.
Block Diagram
PROGRAM
COUNTER
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
STACK
POINTER
PROGRAM
FLASH
MCU CONTROL
REGISTER
SRAM
GENERAL
PURPOSE
REGISTERS
INSTRUCTION
REGISTER
TIMER/
COUNTERS
INSTRUCTION
DECODER
DATA DIR.
REG. PORTB
DATA DIR.
REG. PORTE
DATA DIR.
REG. PORTA
DATA DIR.
REG. PORTD
DATA REGISTER
PORTB
DATA REGISTER
PORTE
DATA REGISTER
PORTA
DATA REGISTER
PORTD
TIMING AND
CONTROL
OSCILLATOR
INTERRUPT
UNIT
EEPROM
SPI
USART
STATUS
REGISTER
Z
Y
X
ALU
PORTB DRIVERS
PORTE DRIVERS
PORTA DRIVERS
PORTF DRIVERS
PORTD DRIVERS
PORTC DRIVERS
PB0 - PB7
PE0 - PE7
PA0 - PA7
PF0 - PF7
VCC
GND
AREF
XT
AL1
XT
AL2
CONTROL
LINES
+
-
ANALOG
COMP
ARA
T
O
R
PC0 - PC7
8-BIT DATA BUS
RESET
AVCC
CALIB. OSC
DATA DIR.
REG. PORTC
DATA REGISTER
PORTC
ON-CHIP DEBUG
JTAG TAP
PROGRAMMING
LOGIC
BOUNDARY-
SCAN
DATA DIR.
REG. PORTF
DATA REGISTER
PORTF
ADC
PD0 - PD7
DATA DIR.
REG. PORTG
DATA REG.
PORTG
PORTG DRIVERS
PG0 - PG4
UNIVERSAL
SERIAL INTERFACE
AVR CPU
LCD
CONTROLLER/
DRIVER
5
8018PS–AVR–08/10
ATmega169P
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
The ATmega169P provides the following features: 16 Kbytes of In-System Programmable Flash
with Read-While-Write capabilities, 512 bytes EEPROM, 1 Kbyte SRAM, 53 general purpose I/O
lines, 32 general purpose working registers, a JTAG interface for Boundary-scan, On-chip
Debugging support and programming, a complete On-chip LCD controller with internal step-up
voltage, three flexible Timer/Counters with compare modes, internal and external interrupts, a
serial programmable USART, Universal Serial Interface with Start Condition Detector, an 8-
channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, an SPI serial
port, and five software selectable power saving modes. The Idle mode stops the CPU while
allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The
Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip
functions until the next interrupt or hardware reset. In Power-save mode, the asynchronous
timer and the LCD controller continues to run, allowing the user to maintain a timer base and
operate the LCD display while the rest of the device is sleeping. The ADC Noise Reduction
mode stops the CPU and all I/O modules except asynchronous timer, LCD controller and ADC,
to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator
Oscillator is running while the rest of the device is sleeping. This allows very fast start-up com-
bined with low-power consumption.
The device is manufactured using Atmel’s high density non-volatile memory technology. The
On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI
serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot pro-
gram running on the AVR core. The Boot program can use any interface to download the
application program in the Application Flash memory. Software in the Boot Flash section will
continue to run while the Application Flash section is updated, providing true Read-While-Write
operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a
monolithic chip, the Atmel ATmega169P is a powerful microcontroller that provides a highly flex-
ible and cost effective solution to many embedded control applications.
The ATmega169P AVR is supported with a full suite of program and system development tools
including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators,
and Evaluation kits.
6
8018PS–AVR–08/10
ATmega169P
2.2
Pin Descriptions
2.2.1
VCC
Digital supply voltage.
2.2.2
GND
Ground.
2.2.3
Port A (PA7:PA0)
Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port A output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port A also serves the functions of various special features of the ATmega169P as listed on
”Alternate Functions of Port A” on page 73
.
2.2.4
Port B (PB7:PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B has better driving capabilities than the other ports.
Port B also serves the functions of various special features of the ATmega169P as listed on
”Alternate Functions of Port B” on page 74
.
2.2.5
Port C (PC7:PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port C also serves the functions of special features of the ATmega169P as listed on
”Alternate
Functions of Port C” on page 77
.
2.2.6
Port D (PD7:PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port D also serves the functions of various special features of the ATmega169P as listed on
”Alternate Functions of Port D” on page 79
.
7
8018PS–AVR–08/10
ATmega169P
2.2.7
Port E (PE7:PE0)
Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port E output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port E also serves the functions of various special features of the ATmega169P as listed on
”Alternate Functions of Port E” on page 81
.
2.2.8
Port F (PF7:PF0)
Port F serves as the analog inputs to the A/D Converter.
Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins
can provide internal pull-up resistors (selected for each bit). The Port F output buffers have sym-
metrical drive characteristics with both high sink and source capability. As inputs, Port F pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port F
pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the
JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will
be activated even if a reset occurs.
Port F also serves the functions of the JTAG interface, see
”Alternate Functions of Port F” on
page 83
.
2.2.9
Port G (PG5:PG0)
Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port G output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port G pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port G also serves the functions of various special features of the ATmega169P as listed on
page 85
.
2.2.10
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in
Table 28-4 on page
333
. Shorter pulses are not guaranteed to generate a reset.
2.2.11
XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
2.2.12
XTAL2
Output from the inverting Oscillator amplifier.
2.2.13
AVCC
AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally con-
nected to V
CC
, even if the ADC is not used. If the ADC is used, it should be connected to V
CC
through a low-pass filter.
8
8018PS–AVR–08/10
ATmega169P
2.2.14
AREF
This is the analog reference pin for the A/D Converter.
2.2.15
LCDCAP
An external capacitor (typical > 470 nF) must be connected to the LCDCAP pin as shown in
Fig-
ure 23-2 on page 236
. This capacitor acts as a reservoir for LCD power (V
LCD
). A large
capacitance reduces ripple on V
LCD
but increases the time until V
LCD
reaches its target value.
9
8018PS–AVR–08/10
ATmega169P
3.
Resources
A comprehensive set of development tools, application notes and datasheets are available for
download on http://www.atmel.com/avr.
Note:
1.
4.
Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less
than 1 PPM over 20 years at 85°C or 100 years at 25°C.
10
8018PS–AVR–08/10
ATmega169P
5.
Register Summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
(0xFF)
Reserved
–
–
–
–
–
–
–
–
(0xFE)
LCDDR18
–
–
–
–
–
–
–
SEG324
250
(0xFD)
LCDDR17
SEG323
SEG322
SEG321
SEG320
SEG319
SEG318
SEG317
SEG316
250
(0xFC)
LCDDR16
SEG315
SEG314
SEG313
SEG312
SEG311
SEG310
SEG309
SEG308
250
(0xFB)
LCDDR15
SEG307
SEG306
SEG305
SEG304
SEG303
SEG302
SEG301
SEG300
250
(0xFA)
Reserved
–
–
–
–
–
–
–
–
(0xF9)
LCDDR13
–
–
–
–
–
–
–
SEG224
250
(0xF8)
LCDDR12
SEG223
SEG222
SEG221
SEG220
SEG219
SEG218
SEG217
SEG216
250
(0xF7)
LCDDR11
SEG215
SEG214
SEG213
SEG212
SEG211
SEG210
SEG209
SEG208
250
(0xF6)
LCDDR10
SEG207
SEG206
SEG205
SEG204
SEG203
SEG202
SEG201
SEG200
250
(0xF5)
Reserved
–
–
–
–
–
–
–
–
(0xF4)
LCDDR8
–
–
–
–
–
–
–
SEG124
250
(0xF3)
LCDDR7
SEG123
SEG122
SEG121
SEG120
SEG119
SEG118
SEG117
SEG116
250
(0xF2)
LCDDR6
SEG115
SEG114
SEG113
SEG112
SEG111
SEG110
SEG109
SEG108
250
(0xF1)
LCDDR5
SEG107
SEG106
SEG105
SEG104
SEG103
SEG102
SEG101
SEG100
250
(0xF0)
Reserved
–
–
–
–
–
–
–
–
(0xEF)
LCDDR3
–
–
–
–
–
–
–
SEG024
250
(0xEE)
LCDDR2
SEG023
SEG022
SEG021
SEG020
SEG019
SEG018
SEG017
SEG016
250
(0xED)
LCDDR1
SEG015
SEG014
SEG013
SEG012
SEG011
SEG010
SEG09
SEG008
250
(0xEC)
LCDDR0
SEG007
SEG006
SEG005
SEG004
SEG003
SEG002
SEG001
SEG000
250
(0xEB)
Reserved
–
–
–
–
–
–
–
–
(0xEA)
Reserved
–
–
–
–
–
–
–
–
(0xE9)
Reserved
–
–
–
–
–
–
–
–
(0xE8)
Reserved
–
–
–
–
–
–
–
–
(0xE7)
LCDCCR
LCDDC2
LCDDC1
LCDDC0
LCDMDT
LCDCC3
LCDCC2
LCDCC1
LCDCC0
249
(0xE6)
LCDFRR
–
LCDPS2
LCDPS1
LCDPS0
–
LCDCD2
LCDCD1
LCDCD0
247
(0xE5)
LCDCRB
LCDCS
LCD2B
LCDMUX1
LCDMUX0
–
LCDPM2
LCDPM1
LCDPM0
246
(0xE4)
LCDCRA
LCDEN
LCDAB
–
LCDIF
LCDIE
LCDBD
LCDCCD
LCDBL
245
(0xE3)
Reserved
–
–
–
–
–
–
–
–
(0xE2)
Reserved
–
–
–
–
–
–
–
–
(0xE1)
Reserved
–
–
–
–
–
–
–
–
(0xE0)
Reserved
–
–
–
–
–
–
–
–
(0xDF)
Reserved
–
–
–
–
–
–
–
–
(0xDE)
Reserved
–
–
–
–
–
–
–
–
(0xDD)
Reserved
–
–
–
–
–
–
–
–
(0xDC)
Reserved
–
–
–
–
–
–
–
–
(0xDB)
Reserved
–
–
–
–
–
–
–
–
(0xDA)
Reserved
–
–
–
–
–
–
–
–
(0xD9)
Reserved
–
–
–
–
–
–
–
–
(0xD8)
Reserved
–
–
–
–
–
–
–
–
(0xD7)
Reserved
–
–
–
–
–
–
–
–
(0xD6)
Reserved
–
–
–
–
–
–
–
–
(0xD5)
Reserved
–
–
–
–
–
–
–
–
(0xD4)
Reserved
–
–
–
–
–
–
–
–
(0xD3)
Reserved
–
–
–
–
–
–
–
–
(0xD2)
Reserved
–
–
–
–
–
–
–
–
(0xD1)
Reserved
–
–
–
–
–
–
–
–
(0xD0)
Reserved
–
–
–
–
–
–
–
–
(0xCF)
Reserved
–
–
–
–
–
–
–
–
(0xCE)
Reserved
–
–
–
–
–
–
–
–
(0xCD)
Reserved
–
–
–
–
–
–
–
–
(0xCC)
Reserved
–
–
–
–
–
–
–
–
(0xCB)
Reserved
–
–
–
–
–
–
–
–
(0xCA)
Reserved
–
–
–
–
–
–
–
–
(0xC9)
Reserved
–
–
–
–
–
–
–
–
(0xC8)
Reserved
–
–
–
–
–
–
–
–
(0xC7)
Reserved
–
–
–
–
–
–
–
–
(0xC6)
UDR0
USART0 I/O Data Register
190
(0xC5)
UBRRH0
USART0 Baud Rate Register High
194
(0xC4)
UBRRL0
USART0 Baud Rate Register Low
194
(0xC3)
Reserved
–
–
–
–
–
–
–
–
(0xC2)
UCSR0C
–
UMSEL0
UPM01
UPM00
USBS0
UCSZ01
UCSZ00
UCPOL0
190
(0xC1)
UCSR0B
RXCIE0
TXCIE0
UDRIE0
RXEN0
TXEN0
UCSZ02
RXB80
TXB80
190
(0xC0)
UCSR0A
RXC0
TXC0
UDRE0
FE0
DOR0
UPE0
U2X0
MPCM0
190