2013-2018 Microchip Technology Inc.
DS20005229D-page 1
93AA46AE48
Device Selection Table
Features
• Preprogrammed Globally Unique 48-Bit Node
Address
• Compatible with EUI-48
™
and EUI-64
™
• Compatible with LAN9210, LAN9211, LAN9215,
LAN9217, LAN9218, LAN9220, LAN9221
• Low-Power CMOS Technology
• 128 x 8-Bit Organization
• Self-Timed Erase/Write Cycles
(including Auto-Erase)
• Automatic Erase All (ERAL) before Write All
(WRAL)
• Power-On/Off Data Protection Circuitry
• Industry Standard 3-Wire Serial I/O
• Device Status Signal (Ready/Busy)
• Sequential Read Function
• 1,000,000 Erase/Write Cycles
• Data Retention: >200 Years
• RoHS Compliant
• Temperature Ranges Supported:
Description
The Microchip Technology Inc. 93AA46AE48 device is
a 1 Kbit low-voltage Serial Electrically Erasable PROM
(EEPROM) featuring an 8-bit word size. Advanced
CMOS technology makes this device ideal for
low-power, nonvolatile memory applications. The
93AA46AE48 is available in standard 8-lead SOIC and
6-lead SOT-23 packages.
Package Types (not to scale)
Pin Function Table
Part Number
V
CC
Range
Word Size
Temp. Ranges
Packages
Node Address
93AA46AE48
1.8V-5.5V
8-bit
I
SN, OT
EUI-48
™
- Industrial (I): -40°C to +85°C
Name
Function
CS
Chip Select
CLK
Serial Data Clock
DI
Serial Data Input
DO
Serial Data Output
V
SS
Ground
NC
No Internal Connection
V
CC
Power Supply
DO
V
SS
DI
1
2
3
6
5
4
V
CC
CS
CLK
CS
CLK
DO
V
CC
NC
NC
V
SS
1
2
3
4
8
7
6
5
SOIC
(SN)
DI
6-Lead SOT-23
(OT)
1K Microwire Serial EEPROM with EUI-48
™
Node Identity
2013-2018 Microchip Technology Inc.
DS20005229D-page 2
93AA46AE48
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
V
CC
.............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. V
SS
..........................................................................................................-0.6V to V
CC
+1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied..................................................................................................-40°C to +85°C
ESD protection on all pins........................................................................................................................................ ≥4 kV
TABLE 1-1:
DC CHARACTERISTICS
† NOTICE:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
DC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
T
A
= -40°C to +85°C, V
CC
= +1.8V to +5.5V
Param.
No.
Symbol
Characteristic
Min.
Typ.
Max.
Units
Conditions
D1
V
IH
1
High-Level Input Voltage
2.0
—
V
CC
+1
V
V
CC
≥ 2.7V
V
IH
2
0.7 V
CC
—
V
CC
+1
V
V
CC
2.7V
D2
V
IL
1
Low-Level Input Voltage
-0.3
—
0.8
V
V
CC
≥ 2.7V
V
IL
2
-0.3
—
0.2 V
CC
V
V
CC
2.7V
D3
V
OL
1
Low-Level Output Voltage
—
—
0.4
V
I
OL
= 2.1 mA, V
CC
= 4.5V
V
OL
2
—
—
0.2
V
I
OL
= 100 µA, V
CC
= 2.5V
D4
V
OH
1
High-Level Output Voltage
2.4
—
—
V
I
OH
= -400 µA, V
CC
= 4.5V
V
OH
2
V
CC
- 0.2
—
—
V
I
OH
= -100 µA, V
CC
= 2.5V
D5
I
LI
Input Leakage Current
—
—
±1
µA
V
IN
= V
SS
or V
CC
D6
I
LO
Output Leakage Current
—
—
±1
µA
V
OUT
= V
SS
or V
CC
D7
C
IN
,
C
OUT
Pin Capacitance
(all inputs/outputs)
—
—
7
pF
V
IN
/V
OUT
= 0V (
Note 1
)
T
A
= 25°C, F
CLK
= 1 MHz
D8
I
CCWRITE
Write Current
—
—
2
mA
V
CC
= 5.5V
—
500
—
µA
V
CC
= 2.5V
D9
I
CCREAD
Read Current
—
—
1
mA
F
CLK
= 2 MHz, V
CC
= 5.5V
—
—
500
µA
F
CLK
= 2 MHz, V
CC
= 3.0V
—
100
—
µA
F
CLK
= 2 MHz, V
CC
= 2.5V
D10
I
CCS
Standby Current
—
—
1
µA
CLK = CS = 0V
DI = V
SS
or V
CC
(
Note 2
)
D11
V
POR
V
CC
Voltage Detect
—
1.5
—
V
Note 1
Note 1:
This parameter is periodically sampled and not 100% tested.
2:
Ready/Busy status must be cleared from DO; see
Section 4.4 “Data Out (DO)”
.
2013-2018 Microchip Technology Inc.
DS20005229D-page 3
93AA46AE48
TABLE 1-2:
AC CHARACTERISTICS
AC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
T
A
= -40°C to +85°C, V
CC
= +1.8V to +5.5V
Param.
No.
Symbol
Characteristic
Min.
Max.
Units
Conditions
A1
F
CLK
Clock Frequency
—
2
MHz 2.5V ≤ V
CC
5.5V
—
1
MHz 1.8V ≤ V
CC
2.5V
A2
T
CKH
Clock High Time
250
—
ns
2.5V ≤ V
CC
5.5V
450
—
ns
1.8V ≤ V
CC
2.5V
A3
T
CKL
Clock Low Time
200
—
ns
2.5V ≤ V
CC
5.5V
450
—
ns
1.8V ≤ V
CC
2.5V
A4
T
CSS
Chip Select Setup Time
50
—
ns
4.5V ≤ V
CC
5.5V
100
—
ns
2.5V ≤ V
CC
4.5V
250
—
ns
1.8V ≤ V
CC
2.5V
A5
T
CSH
Chip Select Hold Time
0
—
ns
1.8V ≤ V
CC
5.5V
A6
T
CSL
Chip Select Low Time
250
—
ns
1.8V ≤
V
CC
5.5V
A7
T
DIS
Data Input Setup Time
100
—
ns
2.5V ≤ V
CC
5.5V
250
—
ns
1.8V ≤ V
CC
2.5V
A8
T
DIH
Data Input Hold Time
100
—
ns
2.5V ≤ V
CC
5.5V
250
—
ns
1.8V ≤ V
CC
2.5V
A9
T
PD
Data Output Delay Time
—
200
ns
4.5V ≤ V
CC
5.5V, C
L
= 100 pF
—
250
ns
2.5V ≤ V
CC
4.5V, C
L
= 100 pF
—
400
ns
1.8V ≤ V
CC
2.5V, C
L
= 100 pF
A10
T
CZ
Data Output Disable Time
—
100
ns
4.5V ≤ V
CC
5.5V (
Note 1
)
—
200
ns
1.8V ≤ V
CC
4.5V (
Note 1
)
A11
T
SV
Status Valid Time
—
200
ns
4.5V ≤ V
CC
5.5V, C
L
= 100 pF
—
300
ns
2.5V ≤ V
CC
4.5V, C
L
= 100 pF
—
500
ns
1.8V ≤
V
CC
2.5V, C
L
= 100 pF
A12
T
WC
Program Cycle Time
—
6
ms
Erase/Write mode
A13
T
EC
—
6
ms
ERAL mode, 4.5V ≤ V
CC
≤ 5.5V
A14
T
WL
—
15
ms
WRAL mode, 4.5V ≤ V
CC
≤ 5.5V
A15
Endurance
1M
—
cycles 25°C, V
CC
= 5.0V (
Note 2
)
Note 1:
This parameter is periodically sampled and not 100% tested.
2:
This application is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance
™
Model, which may be obtained from Microchip’s website
at www.microchip.com.
2013-2018 Microchip Technology Inc.
DS20005229D-page 4
93AA46AE48
FIGURE 1-1:
SYNCHRONOUS DATA TIMING
TABLE 1-3:
INSTRUCTION SET
Instruction
SB
Opcode
Address
Data In
Data Out
Req. CLK Cycles
ERASE
1
11
A6 A5 A4 A3 A2 A1 A0
—
(RDY/
BSY
)
10
ERAL
1
00
1
0
X
X
X
X
X
—
(RDY/
BSY
)
10
EWDS
1
00
0
0
X
X
X
X
X
—
High Z
10
EWEN
1
00
1
1
X
X
X
X
X
—
High Z
10
READ
1
10
A6 A5 A4 A3 A2 A1 A0
—
D7-D0
18
WRITE
1
01
A6 A5 A4 A3 A2 A1 A0
D7-D0
(RDY/
BSY
)
18
WRAL
1
00
0
1
X
X
X
X
X
D7-D0
(RDY/
BSY
)
18
CS
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
V
OL
CLK
DI
DO
(Read)
DO
(Program)
T
CSS
T
DIS
T
CKH
T
CKL
T
DIH
T
PD
T
CSH
T
PD
T
CZ
Status Valid
T
SV
T
CZ
Note:
T
SV
is relative to CS.
2013-2018 Microchip Technology Inc.
DS20005229D-page 5
93AA46AE48
2.0
FUNCTIONAL DESCRIPTION
Instructions, addresses and write data are clocked into
the DI pin on the rising edge of the clock (CLK). The DO
pin is normally held in a High Z state except when
reading data from the device, or when checking the
Ready/Busy status during a programming operation.
The Ready/Busy status can be verified during an
erase/write operation by polling the DO pin; DO low
indicates that programming is still in progress, while
DO high indicates the device is ready. DO will enter the
High Z state on the falling edge of CS.
2.1
Start Condition
The Start bit is detected by the device if CS and DI are
both high with respect to the positive edge of CLK for
the first time.
Before a Start condition is detected, CS, CLK and DI
may change in any combination (except to that of a
Start condition), without resulting in any device
operation (Read, Write, Erase, EWEN, EWDS, ERAL
or WRAL). As soon as CS is high, the device is no
longer in Standby mode.
An instruction following a Start condition will only be
executed if the required opcode, address and data bits
for any particular instruction are clocked in.
2.2
Data In/Data Out (DI/DO)
It is possible to connect the Data In and Data Out pins
together. However, with this configuration, it is possible
for a “bus conflict” to occur during the “dummy zero”
that precedes the read operation if A0 is a logic high
level. Under such a condition, the voltage level seen at
Data Out is undefined and depends upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of A0,
the higher the voltage at the Data Out pin. In order to
limit this current, a resistor should be connected
between DI and DO.
2.3
Data Protection
All modes of operation are inhibited when V
CC
is below
a typical voltage of 1.5V.
The EWEN and EWDS commands give additional
protection against accidentally programming during
normal operation.
After power-up, the device is automatically in the EWDS
mode. Therefore, an EWEN instruction must be
performed before the initial ERASE or WRITE instruction
can be executed.
Block Diagram
Note:
When preparing to transmit an instruction,
either the CLK or DI signal levels must be
at a logic low as CS is toggled active-high.
Note:
For added protection, an EWDS command
should be performed after every write
operation and an external 10 k
pull-down protection resistor should be
added to the CS pin.
Memory
Array
Data Register
Mode
Decode
Logic
Clock
Register
Address
Decoder
Address
Counter
Output
Buffer
DO
DI
CS
CLK
V
CC
V
SS
2013-2018 Microchip Technology Inc.
DS20005229D-page 6
93AA46AE48
2.4
Erase
The ERASE instruction forces all data bits of the
specified address to the logical ‘1’ state. CS is brought
low following the loading of the last address bit. This
falling edge of the CS pin initiates the self-timed
programming cycle.
The DO pin indicates the Ready/Busy status of the
device if CS is brought high after a minimum of 250 ns
low (T
CSL
). DO at logical ‘0’ indicates that programming
is still in progress. DO at logical ‘1’ indicates that the
register at the specified address has been erased and
the device is ready for another instruction.
FIGURE 2-1:
ERASE TIMING
Note:
After the Erase cycle is complete, issuing
a Start bit and then taking CS low will clear
the Ready/Busy status from DO.
CS
CLK
DI
DO
T
CSL
Check Status
1
1
1
A
N
A
N
-1 A
N
-2
•••
A0
T
SV
T
CZ
Busy
Ready
High Z
T
WC
High-Z
2013-2018 Microchip Technology Inc.
DS20005229D-page 7
93AA46AE48
2.5
Erase All (ERAL)
The Erase All (ERAL) instruction will erase the entire
memory array to the logical ‘1’ state. The ERAL cycle is
identical to the erase cycle, except for the different
opcode. The ERAL cycle is completely self-timed and
commences at the falling edge of the CS. Clocking of
the CLK pin is not necessary after the device has
entered the ERAL cycle.
The DO pin indicates the Ready/Busy status of the
device if CS is brought high after a minimum of 250 ns
low (T
CSL
).
V
CC
must be ≥4.5V for proper operation of ERAL.
FIGURE 2-2:
ERAL TIMING
Note:
After the ERAL command is complete,
issuing a Start bit and then taking CS low
will clear the Ready/Busy status from DO.
CS
CLK
DI
DO
T
CSL
Check Status
1
0
0
1
0
x
•••
x
T
SV
T
CZ
Busy
Ready
High Z
T
EC
High-Z
Note:
V
CC
must be ≥4.5V for proper operation of ERAL.
2013-2018 Microchip Technology Inc.
DS20005229D-page 8
93AA46AE48
2.6
Erase/Write Disable and Enable
(EWDS/EWEN)
The 93AA46AE48 powers up in the Erase/Write
Disable (EWDS) state. All programming modes must
be preceded by an Erase/Write Enable (EWEN)
instruction. Once the EWEN instruction is executed,
programming remains enabled until an EWDS
instruction is executed or Vcc is removed from the
device.
To protect against accidental data disturbance, the
EWDS
instruction can be used to disable all erase/write
functions and should follow all programming
operations. Execution of a READ instruction is
independent of both the EWEN and EWDS instructions.
FIGURE 2-3:
EWDS TIMING
FIGURE 2-4:
EWEN TIMING
2.7
Read
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 8-bit output string.
The output data bits will toggle on the rising edge of the
CLK and are stable after the specified time delay (T
PD
).
Sequential read is possible when CS is held high. The
memory data will automatically cycle to the next register
and output sequentially.
CS
CLK
DI
1
0
0
0
0
x
•••
x
T
CSL
1
x
CS
CLK
DI
0
0
1
1
x
T
CSL
•••
2013-2018 Microchip Technology Inc.
DS20005229D-page 9
93AA46AE48
FIGURE 2-5:
READ TIMING
2.8
Write
The WRITE instruction is followed by eight bits of data,
which are written into the specified address. For
93AA46AE48, after the last data bit is clocked into DI,
the falling edge of CS initiates the self-timed auto-erase
and programming cycle.
The DO pin indicates the Ready/Busy status of the
device if CS is brought high after a minimum of 250 ns
low (T
CSL
). DO at logical ‘0’ indicates that programming
is still in progress. DO at logical ‘1’ indicates that the
register at the specified address has been written with
the data specified and the device is ready for another
instruction.
FIGURE 2-6:
WRITE TIMING
CS
CLK
DI
DO
1
1
0
A
N
•••
A0
High Z
0
Dx
•••
D0
Dx
•••
D0
•••
Dx
D0
Note:
After the Write cycle is complete, issuing a
Start bit and then taking CS low will clear
the Ready/Busy status from DO.
CS
CLK
DI
DO
1
0
1
A
N
•••
A0
Dx
•••
D0
Busy
Ready
High Z
High Z
T
WC
T
CSL
T
CZ
T
SV
2013-2018 Microchip Technology Inc.
DS20005229D-page 10
93AA46AE48
2.9
Write All (WRAL)
The Write All (WRAL) instruction will write the entire
memory array with the data specified in the command.
For 93AA46AE48, after the last data bit is clocked into
DI, the falling edge of CS initiates the self-timed
auto-erase and programming cycle. Clocking of the
CLK pin is not necessary after the device has entered
the WRAL cycle. The WRAL command does include an
automatic ERAL cycle for the device. Therefore, the
WRAL
instruction does not require an ERAL instruction,
but the chip must be in the EWEN status.
The DO pin indicates the Ready/Busy status of the
device if CS is brought high after a minimum of 250 ns
low (T
CSL
).
V
CC
must be
4.5V for proper operation of WRAL.
FIGURE 2-7:
WRAL TIMING
Note:
After the Write All cycle is complete,
issuing a Start bit and then taking CS low
will clear the Ready/Busy status from DO.
CS
CLK
DI
DO
H
IGH
-Z
1
0
0
0
1
x
•••
x
Dx
•••
D0
High-Z
Busy
Ready
T
WL
T
CSL
T
SV
T
CZ
Note:
V
CC
must be ≥4.5V for proper operation of WRAL.