2002-2013 Microchip Technology Inc.
DS20001749K-page 1
93AA46A/B/C, 93LC46A/B/C,
93C46A/B/C
Device Selection Table
Features:
• Low-Power CMOS Technology
• ORG Pin to Select Word Size for ‘46C’ Version
• 128 x 8-bit Organization ‘A’ Devices (no ORG)
• 64 x 16-bit Organization ‘B’ Devices (no ORG)
• Self-Timed Erase/Write Cycles (including
Auto-Erase)
• Automatic Erase All (ERAL) Before Write All
(WRAL)
• Power-On/Off Data Protection Circuitry
• Industry Standard 3-Wire Serial I/O
• Device Status Signal (Ready/
Busy
)
• Sequential Read Function
• 1,000,000 Erase/Write Cycles
• Data Retention > 200 Years
• RoHS Compliant
• Temperature Ranges Supported:
Pin Function Table
Description:
The Microchip Technology Inc. 93XX46A/B/C devices
are 1Kbit low-voltage serial Electrically Erasable
PROMs (EEPROM). Word-selectable devices such as
the 93AA46C, 93LC46C or 93C46C are dependent
upon external logic levels driving the ORG pin to set
word size. For dedicated 8-bit communication, the
93AA46A, 93LC46A or 93C46A devices are available,
while the 93AA46B, 93LC46B and 93C46B devices
provide dedicated 16-bit communication. Advanced
CMOS technology makes these devices ideal for low-
power, nonvolatile memory applications. The entire
93XX Series is available in standard packages includ-
ing 8-lead PDIP and SOIC, and advanced packaging
including 8-lead MSOP, 6-lead SOT-23, 8-lead
2x3 DFN/TDFN and 8-lead TSSOP. All packages are
Pb-free (Matte Tin) finish.
Part Number
V
CC
Range
ORG Pin
Word Size
Temp Ranges
Packages
93AA46A
1.8-5.5
No
8-bit
I
P, SN, ST, MS, OT, MC, MN
93AA46B
1.8-5-5
No
16-bit
I
P, SN, ST, MS, OT, MC, MN
93LC46A
2.5-5.5
No
8-bit
I, E
P, SN, ST, MS, OT, MC, MN
93LC46B
2.5-5.5
No
16-bit
I, E
P, SN, ST, MS, OT, MC, MN
93C46A
4.5-5.5
No
8-bit
I, E
P, SN, ST, MS, OT, MC, MN
93C46B
4.5-5.5
No
16-bit
I, E
P, SN, ST, MS, OT, MC, MN
93AA46C
1.8-5.5
Yes
8- or 16-bit
I
P, SN, ST, MS, MC, MN
93LC46C
2.5-5.5
Yes
8- or 16-bit
I, E
P, SN, ST, MS, MC, MN
93C46C
4.5-5.5
Yes
8- or 16-bit
I, E
P, SN, ST, MS, MC, MN
- Industrial (I)
-40°C to +85°C
- Automotive (E) -40°C to +125°C
Name
Function
CS
Chip Select
CLK
Serial Data Clock
DI
Serial Data Input
DO
Serial Data Output
V
SS
Ground
NC
No internal connection
ORG
Memory Configuration
V
CC
Power Supply
1K Microwire Compatible Serial EEPROM
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
DS20001749K-page 2
2002-2013 Microchip Technology Inc.
Package Types (not to scale)
CS
CLK
DI
DO
1
2
3
4
8
7
6
5
V
CC
NC
ORG
*
V
SS
PDIP/SOIC
(P, SN)
CS
CLK
DI
DO
1
2
3
4
8
7
6
5
V
CC
NC
ORG*
V
SS
ROTATED SOIC
(ex: 93LC46BX)
TSSOP/MSOP
CS
CLK
DI
DO
1
2
3
4
8
7
6
5
V
CC
NC
ORG*
V
SS
(ST, MS)
SOT-23
DO
V
SS
DI
1
2
3
6
5
4
V
CC
CS
CLK
(OT)
*ORG pin is NC on A/B devices
DFN/TDFN
CS
CLK
DI
DO
NC
ORG*
V
SS
V
CC
8
7
6
5
1
2
3
4
(MC, MN)
2002-2013 Microchip Technology Inc.
DS20001749K-page 3
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
V
CC
.............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. V
SS
..........................................................................................................-0.6V to V
CC
+1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-40°C to +125°C
ESD protection on all pins
4 kV
TABLE 1-1:
DC CHARACTERISTICS
† NOTICE:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
All parameters apply over the specified
ranges unless otherwise noted.
Industrial (I):
T
A
= -40°C to +85°C, V
CC
= +1.8V
TO
+5.5V
Automotive (E): T
A
= -40°C to +125°C, V
CC
= +2.5V
TO
+5.5V
Param.
No.
Symbol
Parameter
Min.
Typ
Max.
Units
Conditions
D1
V
IH
1
V
IH
2
High-level input voltage
2.0
0.7 V
CC
—
—
V
CC
+1
V
CC
+1
V
V
V
CC
2.7V
V
CC
2.7V
D2
V
IL
1
V
IL
2
Low-level input voltage
-0.3
-0.3
—
—
0.8
0.2 V
CC
V
V
V
CC
2.7V
V
CC
2.7V
D3
V
OL
1
V
OL
2
Low-level output voltage
—
—
—
—
0.4
0.2
V
V
I
OL
= 2.1 mA, V
CC
= 4.5V
I
OL
= 100
A, V
CC
= 2.5V
D4
V
OH
1
V
OH
2
High-level output voltage
2.4
V
CC
- 0.2
—
—
—
—
V
V
I
OH
= -400
A, V
CC
= 4.5V
I
OH
= -100
A, V
CC
= 2.5V
D5
I
LI
Input leakage current
—
—
±1
A
V
IN
= V
SS
or V
CC
D6
I
LO
Output leakage current
—
—
±1
A
V
OUT
= V
SS
or V
CC
D7
C
IN
,
C
OUT
Pin capacitance
(all inputs/outputs)
—
—
7
pF
V
IN
/V
OUT
= 0V (Note 1)
T
A
= 25°C, F
CLK
= 1 MHz
D8
I
CC
write
Write current
—
—
—
500
2
—
mA
A
F
CLK
= 3 MHz, V
CC
= 5.5V
F
CLK
= 2 MHz, V
CC
= 2.5V
D9
I
CC
read Read current
—
—
—
—
—
100
1
500
—
mA
A
A
F
CLK
= 3 MHz, V
CC
= 5.5V
F
CLK
= 2 MHz, V
CC
= 3.0V
F
CLK
= 2 MHz, V
CC
= 2.5V
D10
I
CCS
Standby current
—
—
—
—
1
5
A
A
I-Temp
E-Temp
CLK = CS = 0V
ORG = DI = V
SS
or V
CC
(Note 2) (Note 3)
D11
V
POR
V
CC
voltage detect
—
—
1.5
3.8
—
—
V
V
(Note 1)
93AA46A/B/C, 93LC46A/B/C
93C46A/B/C
Note 1: This parameter is periodically sampled and not 100% tested.
2: ORG pin not available on ‘A’ or ‘B’ versions.
3: Ready/
Busy
status must be cleared from DO; see
Section 3.4 “Data Out (DO)”
.
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
DS20001749K-page 4
2002-2013 Microchip Technology Inc.
TABLE 1-2:
AC CHARACTERISTICS
All parameters apply over the specified
ranges unless otherwise noted.
Industrial (I):
T
A
= -40°C to +85°C, V
CC
= +1.8V
TO
+5.5V
Automotive (E): T
A
= -40°C to +125°C, V
CC
= +2.5V
TO
+5.5V
Param.
No.
Symbol
Parameter
Min.
Max.
Units
Conditions
A1
F
CLK
Clock frequency
—
3
2
1
MHz
MHz
MHz
4.5V
V
CC
5.5V, 93XX46C only
2.5V
V
CC
5.5V
1.8V
V
CC
2.5V
A2
T
CKH
Clock high time
200
250
450
—
ns
ns
ns
4.5V
V
CC
5.5V, 93XX46C only
2.5V
V
CC
5.5V
1.8V
V
CC
2.5V
A3
T
CKL
Clock low time
100
200
450
—
ns
ns
ns
4.5V
V
CC
5.5V, 93XX46C only
2.5V
V
CC
5.5V
1.8V
V
CC
2.5V
A4
T
CSS
Chip Select setup time
50
100
250
—
ns
ns
ns
4.5V
V
CC
5.5V
2.5V
V
CC
4.5V
1.8V
V
CC
2.5V
A5
T
CSH
Chip Select hold time
0
—
ns
1.8V
V
CC
5.5V
A6
T
CSL
Chip Select low time
250
—
ns
1.8V
V
CC
5.5V
A7
T
DIS
Data input setup time
50
100
250
—
ns
4.5V
V
CC
5.5V, 93XX46C only
2.5V
V
CC
5.5V
1.8V
V
CC
2.5V
A8
T
DIH
Data input hold time
50
100
250
—
ns
4.5V
V
CC
5.5V, 93XX46C only
2.5V
V
CC
5.5V
1.8V
V
CC
2.5V
A9
T
PD
Data output delay time
—
—
—
200
250
400
ns
4.5V
V
CC
5.5V, C
L
= 100 pF
2.5V
V
CC
4.5V, C
L
= 100 pF
1.8V
V
CC
2.5V, C
L
= 100 pF
A10
T
CZ
Data output disable time
—
—
100
200
ns
4.5V
V
CC
5.5V, (Note 1)
1.8V
V
CC
4.5V, (Note 1)
A11
T
SV
Status valid time
—
200
300
500
ns
4.5V
V
CC
5.5V, C
L
= 100 pF
2.5V
V
CC
4.5V, C
L
= 100 pF
1.8V
V
CC
2.5V, C
L
= 100 pF
A12
T
WC
Program cycle time
—
6
ms
Erase/Write mode (AA and LC
versions)
A13
T
WC
—
2
ms
Erase/Write mode (93C versions)
A14
T
EC
—
6
ms
ERAL mode, 4.5V
V
CC
5.5V
A15
T
WL
—
15
ms
WRAL mode, 4.5V
V
CC
5.5V
A16
—
Endurance
1M
—
cycles 25°C, V
CC
= 5.0V, (Note 2)
Note 1: This parameter is periodically sampled and not 100% tested.
2: This application is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model, which may be obtained from Microchip’s web
site at www.microchip.com.
2002-2013 Microchip Technology Inc.
DS20001749K-page 5
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
FIGURE 1-1:
SYNCHRONOUS DATA TIMING
TABLE 1-3: INSTRUCTION SET FOR X16 ORGANIZATION (93XX46B OR 93XX46C WITH ORG = 1)
TABLE 1-4: INSTRUCTION SET FOR X8 ORGANIZATION (93XX46A OR 93XX46C WITH ORG = 0)
Instruction
SB
Opcode
Address
Data In
Data Out
Req. CLK Cycles
ERASE
1
11
A5
A4
A3
A2
A1
A0
—
(RDY/
BSY
)
9
ERAL
1
00
1
0
X
X
X
X
—
(RDY/
BSY
)
9
EWDS
1
00
0
0
X
X
X
X
—
High-Z
9
EWEN
1
00
1
1
X
X
X
X
—
High-Z
9
READ
1
10
A5
A4
A3
A2
A1
A0
—
D15 - D0
25
WRITE
1
01
A5
A4
A3
A2
A1
A0
D15 - D0
(RDY/
BSY
)
25
WRAL
1
00
0
1
X
X
X
X
D15 - D0
(RDY/
BSY
)
25
Instruction
SB
Opcode
Address
Data In
Data Out
Req. CLK Cycles
ERASE
1
11
A6 A5 A4 A3 A2 A1 A0
—
(RDY/
BSY
)
10
ERAL
1
00
1
0
X
X
X
X
X
—
(RDY/
BSY
)
10
EWDS
1
00
0
0
X
X
X
X
X
—
High-Z
10
EWEN
1
00
1
1
X
X
X
X
X
—
High-Z
10
READ
1
10
A6 A5 A4 A3 A2 A1 A0
—
D7 - D0
18
WRITE
1
01
A6 A5 A4 A3 A2 A1 A0
D7 - D0
(RDY/
BSY
)
18
WRAL
1
00
0
1
X
X
X
X
X
D7 - D0
(RDY/
BSY
)
18
CS
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
V
OL
CLK
DI
DO
(Read)
DO
(Program)
T
CSS
T
DIS
T
CKH
T
CKL
T
DIH
T
PD
T
CSH
T
PD
T
CZ
Status Valid
T
SV
T
CZ
Note: T
SV
is relative to CS.
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
DS20001749K-page 6
2002-2013 Microchip Technology Inc.
2.0
FUNCTIONAL DESCRIPTION
When the ORG pin (93XX46C) is connected to V
CC
,
the (x16) organization is selected. When it is connected
to ground, the (x8) organization is selected. Instruc-
tions, addresses and write data are clocked into the DI
pin on the rising edge of the clock (CLK). The DO pin is
normally held in a High-Z state except when reading
data from the device, or when checking the Ready/
Busy
status during a programming operation. The
Ready/
Busy
status can be verified during an erase/
write operation by polling the DO pin; DO low indicates
that programming is still in progress, while DO high
indicates the device is ready. DO will enter the High-Z
state on the falling edge of CS.
2.1
Start Condition
The Start bit is detected by the device if CS and DI are
both high with respect to the positive edge of CLK for
the first time.
Before a Start condition is detected, CS, CLK and DI
may change in any combination (except to that of a
Start condition), without resulting in any device
operation (Read, Write, Erase, EWEN, EWDS, ERAL
or WRAL). As soon as CS is high, the device is no
longer in Standby mode.
An instruction following a Start condition will only be
executed if the required opcode, address and data bits
for any particular instruction are clocked in.
2.2
Data In/Data Out (DI/DO)
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero”
that precedes the read operation if A0 is a logic high
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of A0,
the higher the voltage at the Data Out pin. In order to
limit this current, a resistor should be connected
between DI and DO.
2.3
Data Protection
All modes of operation are inhibited when V
CC
is below
a typical voltage of 1.5V for ‘93AA’ and ‘93LC’ devices
or 3.8V for ‘93C’ devices.
The EWEN and EWDS commands give additional
protection against accidentally programming during
normal operation.
After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before the initial ERASE or WRITE instruc-
tion can be executed.
Block Diagram
Note:
When preparing to transmit an instruction,
either the CLK or DI signal levels must be
at a logic low as CS is toggled active-high.
Note:
For added protection, an EWDS command
should be performed after every write
operation and an external 10 k
pull-
down protection resistor should be added
to the CS pin.
Memory
Array
Data Register
Mode
Decode
Logic
Clock
Register
Address
Decoder
Address
Counter
Output
Buffer
DO
DI
ORG*
CS
CLK
V
CC
V
SS
*ORG input is not available on A/B devices
2002-2013 Microchip Technology Inc.
DS20001749K-page 7
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
2.4
Erase
The ERASE instruction forces all data bits of the
specified address to the logical ‘1’ state. CS is brought
low following the loading of the last address bit. This
falling edge of the CS pin initiates the self-timed
programming cycle, except on ‘93C’ devices where the
rising edge of CLK before the last address bit initiates
the write cycle.
The DO pin indicates the Ready/
Busy
status of the
device if CS is brought high after a minimum of 250 ns
low (T
CSL
). DO at logical ‘0’ indicates that programming
is still in progress. DO at logical ‘1’ indicates that the
register at the specified address has been erased and
the device is ready for another instruction.
FIGURE 2-1:
ERASE TIMING FOR 93AA AND 93LC DEVICES
FIGURE 2-2:
ERASE TIMING FOR 93C DEVICES
Note:
After the Erase cycle is complete, issuing
a Start bit and then taking CS low will clear
the Ready/
Busy
status from DO.
CS
CLK
DI
DO
T
CSL
Check Status
1
1
1
A
N
A
N
-1 A
N
-2
•••
A0
T
SV
T
CZ
Busy
Ready
High-Z
T
WC
High-Z
CS
CLK
DI
DO
T
CSL
Check Status
1
1
1
A
N
A
N
-1 A
N
-2
•••
A0
T
SV
T
CZ
Busy
Ready
High-Z
T
WC
High-Z
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
DS20001749K-page 8
2002-2013 Microchip Technology Inc.
2.5
Erase All (ERAL)
The Erase All (ERAL) instruction will erase the entire
memory array to the logical ‘1’ state. The ERAL cycle is
identical to the erase cycle, except for the different
opcode. The ERAL cycle is completely self-timed and
commences at the falling edge of the CS, except on
‘93C’ devices where the rising edge of CLK before the
last data bit initiates the write cycle. Clocking of the
CLK pin is not necessary after the device has entered
the ERAL cycle.
The DO pin indicates the Ready/
Busy
status of the
device if CS is brought high after a minimum of 250 ns
low (T
CSL
).
V
CC
must be
4.5V for proper operation of ERAL.
FIGURE 2-3:
ERAL TIMING FOR 93AA AND 93LC DEVICES
FIGURE 2-4:
ERAL TIMING FOR 93C DEVICES
Note:
After the ERAL command is complete,
issuing a Start bit and then taking CS low
will clear the Ready/
Busy
status from DO.
CS
CLK
DI
DO
T
CSL
Check Status
1
0
0
1
0
x
•••
x
T
SV
T
CZ
Busy
Ready
High-Z
T
EC
High-Z
V
CC
must be
4.5V for proper operation of ERAL.
CS
CLK
DI
DO
T
CSL
Check Status
1
0
0
1
0
x
•••
x
T
SV
T
CZ
Busy
Ready
High-Z
T
EC
High-Z
2002-2013 Microchip Technology Inc.
DS20001749K-page 9
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
2.6
Erase/Write Disable and Enable
(EWDS/EWEN)
The 93XX46A/B/C powers up in the Erase/Write Disable
(EWDS) state. All programming modes must be preceded
by an Erase/Write Enable (EWEN) instruction. Once the
EWEN instruction is executed, programming remains
enabled until an EWDS instruction is executed or Vcc is
removed from the device.
To protect against accidental data disturbance, the EWDS
instruction can be used to disable all erase/write functions
and should follow all programming operations. Execution
of a READ instruction is independent of both the EWEN
and EWDS instructions.
FIGURE 2-5:
EWDS TIMING
FIGURE 2-6:
EWEN TIMING
2.7
Read
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 8-bit (if ORG pin is low or A-version
devices) or 16-bit (if ORG pin is high or B-version
devices) output string.
The output data bits will toggle on the rising edge of the
CLK and are stable after the specified time delay (T
PD
).
Sequential read is possible when CS is held high. The
memory data will automatically cycle to the next register
and output sequentially.
FIGURE 2-7:
READ TIMING
CS
CLK
DI
1
0
0
0
0
x
•••
x
T
CSL
1
x
CS
CLK
DI
0
0
1
1
x
T
CSL
•••
CS
CLK
DI
DO
1
1
0
A
N
•••
A0
High-Z
0
Dx
•••
D0
Dx
•••
D0
•••
Dx
D0
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
DS20001749K-page 10
2002-2013 Microchip Technology Inc.
2.8
Write
The WRITE instruction is followed by 8 bits (if ORG is
low or A-version devices) or 16 bits (if ORG pin is high
or B-version devices) of data, which are written into the
specified address. For 93AA46A/B/C and 93LC46A/B/C
devices, after the last data bit is clocked into DI, the
falling edge of CS initiates the self-timed auto-erase and
programming cycle. For 93C46A/B/C devices, the self-
timed auto-erase and programming cycle is initiated by
the rising edge of CLK on the last data bit.
The DO pin indicates the Ready/
Busy
status of the
device if CS is brought high after a minimum of 250 ns
low (T
CSL
). DO at logical ‘0’ indicates that programming
is still in progress. DO at logical ‘1’ indicates that the
register at the specified address has been written with
the data specified and the device is ready for another
instruction.
FIGURE 2-8:
WRITE TIMING FOR 93AA AND 93LC DEVICES
FIGURE 2-9:
WRITE TIMING FOR 93C DEVICES
Note:
After the Write cycle is complete, issuing a
Start bit and then taking CS low will clear
the Ready/
Busy
status from DO.
CS
CLK
DI
DO
1
0
1
A
N
•••
A0
Dx
•••
D0
Busy
Ready
High-Z
High-Z
T
WC
T
CSL
T
CZ
T
SV
CS
CLK
DI
DO
1
0
1
A
N
•••
A0
Dx
•••
D0
Busy
Ready
High-Z
High-Z
T
WC
T
CSL
T
CZ
T
SV