2011 Microchip Technology Inc.
DS22029F-page 1
34AA02/34LC02
Features:
• Permanent and Resettable Software Write-Protect
for Lower Half of the Array (00h-7Fh)
• Single Supply with Operation Down to 1.7V
• Low-Power CMOS Technology:
- Read current 1 mA, typical
- Standby current, 100 nA, typical
• 2-Wire Serial Interface Bus, I
2
C™ Compatible
• Cascadable up to Eight Devices
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Compatibility
• 1 MHz Clock for LC Versions
• Page Write Time 3 ms, typical
• Self-Timed Erase/Write Cycle
• 16-Byte Page Write Buffer
• ESD Protection > 4,000V
• Software Write Protection for Lower 128 Bytes
• Hardware Write Protection for Entire Array
• More than 1 Million Erase/Write Cycles
• Data Retention > 200 Years
• 8-Lead PDIP, SOIC, TSSOP, MSOP and TDFN
Packages
• 6-Lead SOT-23 Package
• Pb-free and RoHS Compliant
• Available for Extended Temperature Ranges:
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
Device Selection Table
Package Types
Description:
The Microchip Technology Inc. 34AA02/34LC02
(34XX02*) is a 2 Kbit Electrically Erasable PROM
capable of operation across a broad voltage range
(1.7V to 5.5V). This device has two software write-
protect features for the lower half of the array, as well
as an external pin that can be used to write-protect the
entire array. This allows the system designer to protect
none, half, or all of the array, depending on the
application. The device is organized as one block of
256 x 8-bit memory with a 2-wire serial interface. Low-
voltage design permits operation down to 1.7V, with
standby and active currents of only 100 nA and 1 mA,
respectively. The 34XX02 also has a page write
capability for up to 16 bytes of data. The 34XX02 is
available in the standard 8-pin PDIP, surface mount
SOIC, TSSOP, MSOP and TDFN packages. The
34XX02 is also available in the 6-lead, SOT-23
package.
Part
Number
V
CC
Range
Max. Clock
Frequency
Temp
Ranges
34AA02
1.7-5.5
400 kHz
(1)
I,E
34LC02
2.2-5.5
1 MHz
I,E
Note 1:
100 kHz for V
CC
<1.8V.
A0
A1
A2
V
SS
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
PDIP/SOIC/TSSOP/MSOP/TDFN
A0
A1
A2
V
SS
WP
SCL
SDA
V
CC
8
7
6
5
1
2
3
4
SOT-23
6
2
4
SDA
V
CC
V
SS
A0
A1
5
3
1
SCL
2K I
2
C
™
Serial EEPROM Software Write-Protect
*34XX02 is used in this document as a generic part number
for the 34AA02/34LC02 devices.
34AA02/34LC02
DS22029F-page 2
2011 Microchip Technology Inc.
Block Diagram
I/O
Control
Logic
Memory
Control
Logic
XDEC
HV Generator
Standard
Array
Software write-
Write-Protect
Circuitry
YDEC
V
CC
V
SS
Sense Amp.
R/W Control
SDA SCL
A0 A1 A2
WP
protected area
(00h-7Fh)
2011 Microchip Technology Inc.
DS22029F-page 3
34AA02/34LC02
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
V
CC
............................................................................................................................................................................. 6.5V
All inputs and outputs w.r.t. V
SS
..........................................................................................................-0.3V to V
CC
+1.0V
Storage temperature ............................................................................................................................... -65°C to +150°C
Ambient temperature with power applied................................................................................................-40°C to +125°C
ESD protection on all pins
4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
TABLE 1-1:
DC SPECIFICATIONS
DC CHARACTERISTICS
V
CC
= +1.7V to +5.5V
Industrial (I): T
A
= -40°C to +85°C
Automotive (E):T
A
= -40°C to +125°C
Param.
No.
Symbol
Characteristic
Min.
Typ.
Max.
Units
Conditions
—
A0, A1, A2, SCL, SDA
and WP pins
—
—
—
—
—
D1
V
IH
High-level input voltage
0.7 V
CC
—
—
V
—
D2
V
IL
Low-level input voltage
—
—
0.3 V
CC
V
0.2 V
CC
for V
CC
< 2.5V
D3
V
HYS
Hysteresis of Schmitt
Trigger inputs
0.05 V
CC
—
—
V
(
Note
)
D4
V
OL
Low-level output voltage
—
—
0.40
V
I
OL
= 3.0 mA, V
CC
= 2.5V
D5
V
HV
High-Voltage Detect
7
—
10
V
A0 Pin only, V
CC
< 2.2V
V
CC
+ 4.8
—
10
V
A0 Pin only, V
CC
2.2V
10
—
V
CC
+ 4.8
V
A0 Pin only, V
CC
5.2V
D6
I
LI
Input leakage current
—
—
±1
A
V
IN
= V
SS
or V
CC
D7
I
LO
Output leakage current
—
—
±1
A
V
OUT
= V
SS
or V
CC
D8
C
IN
,
C
OUT
Pin capacitance
(all inputs/outputs)
—
—
10
pF
V
CC
= 5.5V (
Note
)
T
A
= 25°C, F
CLK
= 1 MHz
D9
I
CC
write
Operating current
—
0.1
3
mA
V
CC
= 5.5V, SCL = 1 MHz
D10
I
CC
read
—
0.05
1
mA
—
D11
I
CCS
Standby current
—
—
0.01
—
1
5
A
A
Industrial
Automotive
SDA = SCL = V
CC
A0, A1, A2, WP = V
SS
Note:
This parameter is periodically sampled and not 100% tested.
34AA02/34LC02
DS22029F-page 4
2011 Microchip Technology Inc.
TABLE 1-2:
AC SPECIFICATIONS
AC CHARACTERISTICS
V
CC
= +1.7V to +5.5V
Industrial (I): T
A
= -40°C to +85°C
Automotive (E):T
A
= -40°C to +125°C
Param.
No.
Symbol
Characteristic
Min.
Max.
Units
Conditions
1
F
CLK
Clock frequency
—
—
—
100
400
1000
kHz
1.7V
V
CC
< 1.8V
1.8V
V
CC
5.5V
2.5V
V
CC
5.5V (34LC02)
2
T
HIGH
Clock high time
4000
600
500
—
—
—
ns
1.7V
V
CC
< 1.8V
1.8V
V
CC
5.5V
2.5V
V
CC
5.5V (34LC02)
3
T
LOW
Clock low time
4700
1300
500
—
—
—
ns
1.7V
V
CC
< 1.8V
1.8V
V
CC
5.5V
2.5V
V
CC
5.5V (34LC02)
4
T
R
SDA and SCL rise time (
Note 1
)
—
—
—
1000
300
300
ns
1.7V
V
CC
< 1.8V
1.8V
V
CC
5.5V
2.5V
V
CC
5.5V (34LC02)
5
T
F
SDA and SCL fall time (
Note 1
)
—
—
—
1000
300
300
ns
1.7V
V
CC
< 1.8V
1.8V
V
CC
5.5V
2.5V
V
CC
5.5V (34LC02)
6
T
HD
:
STA
Start condition hold time
4000
600
250
—
—
—
ns
1.7V
V
CC
< 1.8V
1.8V
V
CC
5.5V
2.5V
V
CC
5.5V (34LC02)
7
T
SU
:
STA
Start condition setup time
4700
600
250
—
—
—
ns
1.7V
V
CC
< 1.8V
1.8V
V
CC
5.5V
2.5V
V
CC
5.5V (34LC02)
8
T
HD
:
DAT
Data input hold time
0
—
ns
(
Note 2
)
9
T
SU
:
DAT
Data input setup time
250
100
100
—
—
—
ns
1.7V
V
CC
< 1.8V
1.8V
V
CC
5.5V
2.5V
V
CC
5.5V (34LC02)
10
T
SU
:
STO
Stop condition setup time
4000
600
250
—
—
—
ns
1.7V
V
CC
< 1.8V
1.8V
V
CC
5.5V
2.5V
V
CC
5.5V (34LC02)
11
T
SU
:
WP
WP setup time
4000
600
600
—
—
—
ns
1.7V
V
CC
< 1.8V
1.8V
V
CC
5.5V
2.5V
V
CC
5.5V (34LC02)
12
T
HD
:
WP
WP hold time
4700
600
600
—
—
—
ns
1.7V
V
CC
< 1.8V
1.8V
V
CC
5.5V
2.5V
V
CC
5.5V (34LC02)
13
T
AA
Output valid from clock (
Note 2
)
—
—
—
3500
900
400
ns
1.7V
V
CC
< 1.8V
1.8V
V
CC
5.5V
2.5V
V
CC
5.5V (34LC02)
14
T
BUF
Bus free time: Time the bus must be
free before a new transmission can
start
1300
4700
—
—
—
ns
1.7V
V
CC
< 1.8V
1.8V
V
CC
5.5V
2.5V
V
CC
5.5V (34LC02)
16
T
SP
Input filter spike suppression
(SDA and SCL pins)
—
50
ns
All except 34LC02
(
Note 1
and
Note 3
)
17
T
WC
Write cycle time (byte or page)
—
5
ms
—
18
—
Endurance
1M
—
cycles
25°C, V
CC
= 5.5V, Block mode
(
Note 4
)
Note
1:
Not 100% tested. C
B
= total capacitance of one bus line in pF.
2:
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the
falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3:
The combined T
SP
and V
HYS
specifications are due to new Schmitt Trigger inputs, which provide improved noise spike suppres-
sion. This eliminates the need for a T
I
specification for standard operation.
4:
This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult
the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com.
2011 Microchip Technology Inc.
DS22029F-page 5
34AA02/34LC02
FIGURE 1-1:
BUS TIMING DATA
(unprotected)
(protected)
SCL
SDA
In
SDA
Out
WP
5
7
6
16
3
2
8
9
13
D4
4
10
11
12
14
34AA02/34LC02
DS22029F-page 6
2011 Microchip Technology Inc.
2.0
FUNCTIONAL DESCRIPTION
The 34XX02 has two Software Write-Protect features
that allow you to protect half of the array from being
written (Addresses 00h-7Fh). One command, Software
Write-Protect (SWP) will prevent writes to half of the
array and is resettable by using the Clear Software
Write-Protect (CSWP) command. The other command
is Permanent Software Write-Protect (PSWP), which is
not resettable and will permanently lock half the array
from being written to. The device still has an external
pin (WP) that allows you to protect the entire array if so
desired.
The 34XX02 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, and a device
receiving data, as a receiver. The bus has to be
controlled by a master device, which generates the
Serial Clock (SCL), controls the bus access and gener-
ates the Start and Stop conditions, while the 34XX02
works as slave. Both master and slave can operate as
transmitter or receiver, but the master device
determines which mode is activated.
3.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (
Figure 3-1
).
3.1
Bus Not Busy (A)
Both data and clock lines remain high.
3.2
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
3.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
3.4
Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of data
bytes transferred between the Start and Stop
conditions is determined by the master device and is,
theoretically, unlimited; although only the last sixteen
will be stored when doing a write operation. When an
overwrite does occur, it will replace data in a first-in,
first-out (FIFO) fashion.
3.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an Acknowledge after the reception of each
byte. Exceptions to this rule relating to software write
protection are described in
Section 7.0 “Write Protec-
tion”
. The master device must generate an extra clock
pulse, which is associated with this Acknowledge bit.
The device that acknowledges has to pull down the
SDA line during the Acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end-of-
data to the slave by not generating an Acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (34XX02) will leave the data line
high to enable the master to generate the Stop
condition.
Note:
The 34XX02 does not generate any
Acknowledge bits if an internal
programming cycle is in progress.
2011 Microchip Technology Inc.
DS22029F-page 7
34AA02/34LC02
FIGURE 3-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
3.6
Device Addressing
A control byte is the first byte received following the
Start condition from the master device. The first part of
the control byte consists of a 4-bit control code which is
set to ‘1010’ for normal read and write operations and
‘0110’ for writing to the write-protect register. The
control byte is followed by three Chip Select bits (A2,
A1, A0). The Chip Select bits allow the use of up to
eight 34XX02 devices on the same bus and are used to
determine which device is accessed. The Chip Select
bits in the control byte must correspond to the logic lev-
els on the corresponding A2, A1 and A0 pins for the
device to respond.
For the SOT-23 package, the A2 pin is not connected.
During device addressing, the A2 Chip Select bit
(
Figure 3-2
) should be set to ‘0’. Only four 34XX02
SOT-23 packages can be connected to the same bus.
The eighth bit of slave address determines if the master
device wants to read or write to the 34XX02
(
Figure 3-2
). When set to a one, a read operation is
selected. When set to a zero, a write operation is
selected.
FIGURE 3-2:
CONTROL BYTE
ALLOCATION
4.0
WRITE OPERATIONS
4.1
Byte Write
Following the Start signal from the master, the device
code(4 bits), the Chip Select bits (3 bits) and the R/W
bit, which is a logic low, are placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow,
once it has generated an Acknowledge bit during the
ninth clock cycle. Therefore, the next byte transmitted
by the master is the word address and will be written
into the Address Pointer of the 34XX02.
After receiving another Acknowledge signal from the
34XX02, the master device will transmit the data word
to be written into the addressed memory location. The
34XX02 acknowledges again and the master generates
a Stop condition. This initiates the internal write cycle,
which means that during this time, the 34XX02 will not
generate Acknowledge signals (
Figure 4-1
). If an
attempt is made to write to the array when the software
or hardware write protection has been enabled, the
device will acknowledge the command, but no data will
be written. The write cycle time must be observed even
if the write protection is enabled.
SCL
SDA
(A)
(B)
(D)
(D)
(A)
(C)
Start
Condition
Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
Operation
Control
Code
Chip
Select
R/W
Read
1010
A2 A1 A0
1
Write
1010
A2 A1 A0
0
Write-Protect Register
0110
A2 A1 A0
0
OR
Start
Read/Write
Slave Address
R/W A
1
0
1
0
A2
A1
A0
0
1
1
0
A2
A1
A0
34AA02/34LC02
DS22029F-page 8
2011 Microchip Technology Inc.
4.2
Page Write
The write control byte, word address and the first data
byte are transmitted to the 34XX02 in the same way as
in a byte write. Instead of generating a Stop condition,
the master transmits up to 15 additional data bytes to
the 34XX02, which are temporarily stored in the on-
chip page buffer and will be written into the memory
after the master has transmitted a Stop condition. Upon
receipt of each word, the four lower order Address
Pointer bits are internally incremented by one. The
higher order four bits of the word address remain
constant. If the master should transmit more than 16
bytes prior to generating the Stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the Stop condition is received, an
internal write cycle will begin (
Figure 4-2
). If an attempt
is made to write to the array when the hardware write
protection has been enabled, the device will acknowl-
edge the command, but no data will be written. The
write cycle time must be observed even if the write
protection is enabled.
FIGURE 4-1:
BYTE WRITE
FIGURE 4-2:
PAGE WRITE
Note:
Page write operations are limited to
writing bytes within a single physical page,
regardless of the number of bytes actually
being written. Physical page boundaries
start at addresses that are integer multi-
ples of the page buffer size (or ‘page size’)
and end at addresses that are integer mul-
tiples of [page size – 1]. If a Page Write
command attempts to write across a phys-
ical page boundary, the result is that the
data wraps around to the beginning of the
current page (overwriting data previously
stored there), instead of being written to
the next page, as might be expected. It is
therefore necessary for the application
software to prevent page write operations
that would attempt to cross a page
boundary.
S
P
Bus Activity
Master
SDA Line
Bus Activity
S
T
A
R
T
S
T
O
P
Control
Byte
Word
Address
Data
A
C
K
A
C
K
A
C
K
S
P
Bus Activity
Master
SDA Line
Bus Activity
S
T
A
R
T
Control
Byte
Word
Address
(n)
Data (n)
Data (n + 15)
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Data (n + 1)
2011 Microchip Technology Inc.
DS22029F-page 9
34AA02/34LC02
5.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition followed by the control byte
for a Write command (R/W =
0
). If the device is still
busy with the write cycle, then no ACK will be returned.
If the cycle is complete, then the device will return the
ACK and the master can then proceed with the next
Read or Write command. See
Figure 5-1
for flow
diagram.
FIGURE 5-1:
ACKNOWLEDGE
POLLING FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
Next
Operation
No
Yes
34AA02/34LC02
DS22029F-page 10
2011 Microchip Technology Inc.
6.0
READ OPERATION
Read operations are initiated in the same way as write
operations, with the exception that the R/W bit of the
slave address is set to ‘
1
’. There are three basic types
of read operations: current address read, random read
and sequential read.
6.1
Current Address Read
The 34XX02 contains an address counter that
maintains the address of the last word accessed, inter-
nally incremented by ‘
1
’. Therefore, if the previous
access (either a read or write operation) was to
address
n
, the next current address read operation
would access data from address
n+1
. Upon receipt of
the slave address with R/W bit set to ‘
1
’, the 34XX02
issues an acknowledge and transmits the 8-bit data
word. The master will not acknowledge the transfer, but
does generate a Stop condition and the 34XX02
discontinues transmission (
Figure 6-1
).
6.2
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is done by sending the word address to the
34XX02 as part of a write operation. Once the word
address is sent, the master generates a Start condition
following the acknowledge. This terminates the write
operation, but not before the internal Address Pointer is
set. The master then issues the control byte again, but
with the R/W bit set to a ‘
1
’. The 34XX02 then issues
an acknowledge and transmits the 8-bit data word. The
master will not acknowledge the transfer, but does
generate a Stop condition and the 34XX02
discontinues transmission (
Figure 6-2
).
6.3
Sequential Read
Sequential reads are initiated in the same way as a
random read, with the exception that after the 34XX02
transmits the first data byte, the master issues acknowl-
edge, as opposed to a Stop condition in a random read.
This directs the 34XX02 to transmit the next sequen-
tially addressed 8-bit word (
Figure 6-3
).
To provide sequential reads, the 34XX02 contains an
internal Address Pointer, which is incremented by one
at the completion of each operation. This Address
Pointer allows the entire memory contents to be serially
read during one operation.
6.4
Contiguous Addressing Across
Multiple Devices
The Chip Select bits (A2, A1, A0) can be used to
expand the contiguous address space for up to 16K bits
by adding up to eight 34XX02 devices on the same
bus. In this case, software can use A0 of the control
byte as address bit A8; A1 as address bit A9, and A2
as address bit A10. It is not possible to sequentially
read across device boundaries.
6.5
Noise Protection and Brown-Out
The 34XX02 employs a V
CC
threshold detector circuit
which disables the internal erase/write logic if the V
CC
is below 1.35V at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation, even on a noisy bus.
FIGURE 6-1:
CURRENT ADDRESS READ
S
P
Bus Activity
Master
SDA Line
Bus Activity
S
T
O
P
Control
Byte
Data (n)
A
C
K
N
O
A
C
K
S
T
A
R
T