2009-2018 Microchip Technology Inc.
DS20002131D-page 1
25LC080C/25LC080D/25LC160C/
25LC160D/25LC320A/25LC640A/
25LC128/25LC256
Features
• Maximum Clock: 5 MHz
• Low-Power CMOS Technology:
- Write current: 5 mA at 5.5V (maximum)
- Read current: 5 mA at 5.5V, 5 MHz
- Standby current: 10 μA at 5.5V
• 1,024 x 8 through 32,768 x 8-bit Organization
• Byte and Page-Level Write Operations
• Self-Timed Erase and Write Cycles
(6 ms maximum)
• Block Write Protection:
- Protect none, 1/4, 1/2 or all of array
• Built-in Write Protection:
- Power-on/off data protection circuitry
- Write enable latch
- Write-protect pin
• Sequential Read
• High Reliability:
- Endurance: >1,000,000 erase/write cycles
- Data retention: >200 years
- ESD protection: >4000V
• Temperature Range Supported:
• RoHS Compliant
• Automotive AECQ-100 Qualified
Description
Microchip Technology Inc. 25LCXXX
(
1
)
devices are
Mid-density 8- through 256-Kbit Serial Electrically
Erasable PROMs (EEPROM). The devices are
organized in blocks of x8-bit memory and support the
Serial Peripheral Interface (SPI) compatible serial bus
architecture. Byte-level and page-level functions are
supported. The bus signals required are a clock input
(SCK) plus separate data in (SI) and data out (SO)
lines. Access to the device is controlled through a Chip
Select (CS) input.
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused,
transitions on its inputs will be ignored, with the
exception of Chip Select, allowing the host to service
higher priority interrupts.
Packages
• 8-Lead SOIC
Package Types (not to scale)
Pin Function Table
- Extended (H):
-40°C to +150°C
Note 1:
25LCXXX is used in this document as a
generic part number for the 25LC080C/
25LC080D/25LC160C/25LC160D/
25LC320A/25LC640A/25LC128/
25LC256 devices.
Name
Function
CS
Chip Select Input
SO
Serial Data Output
WP
Write-Protect
V
SS
Ground
SI
Serial Data Input
SCK
Serial Clock Input
HOLD
Hold Input
V
CC
Supply Voltage
8-Lead SOIC
CS
SO
WP
V
SS
1
2
3
4
8
7
6
5
V
CC
HOLD
SCK
SI
(Top View)
8K-256K SPI Serial EEPROM High Temp Family Data Sheet
2009-2018 Microchip Technology Inc.
DS20002131D-page 2
25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/
25LC128/25LC256
DEVICE SELECTION TABLE
Part Number
Density
(bits)
Organization
V
CC
Range
Max. Speed
(MHz)
Page Size
(Bytes)
Temp.
Range
Package
25LC080C
8K
1,024 x 8
2.5V-5.5V
5
16
H
SN
25LC080D
8K
1,024 x 8
2.5V-5.5V
5
32
H
SN
25LC160C
16K
2,048 x 8
2.5V-5.5V
5
16
H
SN
25LC160D
16K
2,048 x 8
2.5V-5.5V
5
32
H
SN
25LC320A
32K
4,096 x 8
2.5V-5.5V
5
32
H
SN
25LC640A
64K
8,192 x 8
2.5V-5.5V
5
32
H
SN
25LC128
128K
16,384 x 8
2.5V-5.5V
5
64
H
SN
25LC256
256K
32,768 x 8
2.5V-5.5V
5
64
H
SN
2009-2018 Microchip Technology Inc.
DS20002131D-page 3
25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/
25LC128/25LC256
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
V
CC
.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. V
SS
......................................................................................................... -0.6V to V
CC
+1.0V
Storage temperature ...............................................................................................................................-65°C to +155°C
Ambient temperature under bias ......................................................................................................... -40°C to +150°C
(
1
)
ESD protection on all pins..........................................................................................................................................4 kV
Note 1:
AEC-Q100 reliability testing for devices intended to operate at +150°C is 1,000 hours. Any design in which
the total operating time between +125°C and +150°C will be greater than 1,000 hours is not warranted
without prior written approval from Microchip Technology Inc.
†
NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
DC CHARACTERISTICS
Electrical Characteristics:
Extended (H):
T
A
= -40°C to +150°C
V
CC
= 2.5V to 5.5V
Param.
No.
Symbol
Characteristic
Min.
Max.
Units
Test Conditions
D001
V
IH1
High-Level Input
Voltage
0.7 V
CC
V
CC
+ 1
V
D002
V
IL1
Low-Level Input
Voltage
-0.3
0.3V
CC
V
V
CC
≥2.7V
D003
V
IL2
-0.3
0.2V
CC
V
V
CC
< 2.7V
D004
V
OL1
Low-Level Output
Voltage
—
0.4
V
I
OL
= 2.1 mA
D005
V
OL2
—
0.2
V
I
OL
= 1.0 mA
D006
V
OH
High-Level Output
Voltage
V
CC
– 0.5
—
V
I
OH
= -400 μA
D007
I
LI
Input Leakage Current
—
±2
μA
CS = V
CC
, V
IN
= V
SS OR
V
CC
D008
I
LO
Output Leakage Current
—
±2
μA
CS = V
CC
, V
OUT
= V
SS OR
V
CC
D009
C
INT
Internal Capacitance
(all inputs and outputs)
—
7
pF
T
A
= 25°C, CLK = 1.0 MHz,
V
CC
= 5.0V (
Note 1
)
D010
I
CC
Read
Operating Current
—
5
mA
V
CC
= 5.5V; F
CLK
= 5.0 MHz;
SO = Open
—
2.5
mA
V
CC
= 2.5V; F
CLK
= 3.0 MHz;
SO = Open
D011
I
CC
Write
Operating Current
—
5
mA
V
CC
= 5.5V
—
3
mA
V
CC
= 2.5V
D012
I
CCS
Standby Current
—
10
μA
CS = V
CC
= 5.5V,
Inputs tied to V
CC
or V
SS
, +150°C
Note 1:
This parameter is periodically sampled and not 100% tested.
2009-2018 Microchip Technology Inc.
DS20002131D-page 4
25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/
25LC128/25LC256
TABLE 1-2:
AC CHARACTERISTICS
AC CHARACTERISTICS
Electrical Characteristics:
Extended (H):
T
A
= -40°C to +150°C
V
CC
= 2.5V to 5.5V
Param.
No.
Symbol
Characteristic
Min.
Max.
Units
Test Conditions
1
F
CLK
Clock Frequency
—
5
MHz
4.5V ≤ Vcc ≤ 5.5V
—
3
MHz
2.5V ≤ Vcc < 4.5V
2
T
CSS
CS Setup Time
100
—
ns
4.5V ≤
Vcc ≤ 5.5V
150
—
ns
2.5V ≤
Vcc < 4.5V
3
T
CSH
CS Hold Time
200
—
ns
4.5V ≤ Vcc ≤ 5.5V
250
—
ns
2.5V ≤ Vcc < 4.5V
4
T
CSD
CS Disable Time
50
—
ns
—
5
Tsu
Data Setup Time
20
—
ns
4.5V ≤ Vcc ≤ 5.5V
30
—
ns
2.5V ≤ Vcc < 4.5V
6
T
HD
Data Hold Time
40
—
ns
4.5V ≤ Vcc ≤ 5.5V
50
—
ns
2.5V ≤ Vcc < 4.5V
7
T
R
CLK Rise Time
—
2
μs
Note 1
8
T
F
CLK Fall Time
—
2
μs
Note 1
9
T
HI
Clock High Time
100
—
ns
4.5V ≤ Vcc ≤ 5.5V
150
—
ns
2.5V ≤ Vcc < 4.5V
10
T
LO
Clock Low Time
100
—
ns
4.5V ≤ Vcc ≤ 5.5V
150
—
ns
2.5V ≤ Vcc < 4.5V
11
T
CLD
Clock Delay Time
50
—
ns
12
T
CLE
Clock Enable Time
50
—
ns
13
T
V
Output Valid from Clock
Low
—
100
ns
4.5V ≤ Vcc ≤ 5.5V
—
160
ns
2.5V ≤ Vcc < 4.5V
14
T
HO
Output Hold Time
0
—
ns
Note 1
15
T
DIS
Output Disable Time
—
80
ns
4.5V ≤ Vcc ≤ 5.5V (
Note 1
)
—
160
ns
2.5V ≤ Vcc < 4.5V (
Note 1
)
16
T
HS
HOLD Setup Time
40
—
ns
4.5V ≤ Vcc ≤ 5.5V
80
—
ns
2.5V ≤ Vcc < 4.5V
17
T
HH
HOLD Hold Time
40
—
ns
4.5V ≤ Vcc ≤ 5.5V
80
—
ns
2.5V ≤ Vcc < 4.5V
18
T
HZ
HOLD Low to Output
High Z
—
60
ns
4.5V ≤ Vcc ≤ 5.5V (
Note 1
)
—
160
ns
2.5V ≤ Vcc < 4.5V (
Note 1
)
19
T
HV
HOLD High to Output
Valid
—
60
ns
4.5V ≤ Vcc ≤ 5.5V
—
160
ns
2.5V ≤ Vcc < 4.5V
20
T
WC
Internal Write Cycle Time
—
6
ms
Note 2
21
Endurance
1,000,000
—
E/W
Cycles
Page mode, 25°C, V
CC
= 5.5V (
Note 3
)
Note 1:
This parameter is periodically sampled and not 100% tested.
2:
T
WC
begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle
is complete.
3:
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from our website:
www.microchip.com.
2009-2018 Microchip Technology Inc.
DS20002131D-page 5
25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/
25LC128/25LC256
FIGURE 1-1:
HOLD TIMING
FIGURE 1-2:
SERIAL INPUT TIMING
TABLE 1-3:
AC Waveform
V
LO
= 0.2V
V
H I
= V
CC
– 0.2V
Note 1
V
H I
= 4.0V
Note 2
C
L
= 50 pF
Timing Measurement Reference Level
Input
0.5 V
CC
Output
0.5 V
CC
Note 1:
For V
CC
≤ 4.0V
2:
For V
CC
> 4.0V
CS
SCK
SO
SI
HOLD
17
16
16
17
19
18
Don’t Care
5
High-Impedance
n + 2
n + 1
n
n - 1
n
n + 2
n + 1
n
n
n - 1
CS
SCK
SI
SO
6
5
8
7
11
3
LSB in
MSB in
High-Impedance
12
Mode 1,1
Mode 0,0
2
4
2009-2018 Microchip Technology Inc.
DS20002131D-page 6
25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/
25LC128/25LC256
FIGURE 1-3:
SERIAL OUTPUT TIMING
CS
SCK
SO
10
9
13
MSB out
LSB out
3
15
Don’t Care
SI
Mode 1,1
Mode 0,0
14
2009-2018 Microchip Technology Inc.
DS20002131D-page 7
25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/
25LC128/25LC256
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in
Table 2-1
.
2.1
Chip Select (CS)
A low level on this pin selects the device. A high level
deselects the device and forces it into Standby mode.
However, a programming cycle which is already
initiated or in progress will be completed, regardless of
the CS input signal. If CS is brought high during a
program cycle, the device will go into Standby mode as
soon as the programming cycle is complete. When the
device is deselected, SO goes to the high-impedance
state, allowing multiple parts to share the same SPI
bus. A low-to-high transition on CS after a valid write
sequence initiates an internal write cycle. After power-
up, a low level on CS is required prior to any sequence
being initiated.
2.2
Serial Output (SO)
The SO pin is used to transfer data out of the
25LCXXX. During a read cycle, data is shifted out on
this pin after the falling edge of the serial clock.
2.3
Write-Protect (WP)
This pin is used in conjunction with the WPEN bit in the
STATUS register to prohibit writes to the nonvolatile
bits in the STATUS register. When WP is low and
WPEN is high, writing to the nonvolatile bits in the
STATUS register is disabled. All other operations
function normally. When WP is high, all functions,
including writes to the nonvolatile bits in the STATUS
register operate normally. If the WPEN bit is set, WP
low during a STATUS register write sequence will dis-
able writing to the STATUS register. If an internal write
cycle has already begun, WP going low will have no
effect on the write.
The WP pin function is blocked when the WPEN bit in
the STATUS register is low. This allows the user to
install the 25LCXXX in a system with WP pin grounded
and still be able to write to the STATUS register. The
WP pin functions will be enabled when the WPEN bit is
set high.
2.4
Serial Input (SI)
The SI pin is used to transfer data into the device. It
receives instructions, addresses and data. Data is
latched on the rising edge of the serial clock.
2.5
Serial Clock (SCK)
The SCK is used to synchronize the communication
between a master and the 25LCXXX. Instructions,
addresses or data present on the SI pin are latched on
the rising edge of the clock input, while data on the SO
pin is updated after the falling edge of the clock input.
2.6
Hold (HOLD)
The HOLD pin is used to suspend transmission to the
25LCXXX while in the middle of a serial sequence
without having to retransmit the entire sequence
again. It must be held high any time this function is not
being used. Once the device is selected and a serial
sequence is underway, the HOLD pin may be pulled
low to pause further serial communication without
resetting the serial sequence. The HOLD pin must be
brought low while SCK is low, otherwise the HOLD
function will not be invoked until the next SCK high-to-
low transition. The 25LCXXX must remain selected
during this sequence. The SI, SCK and SO pins are in
a high-impedance state during the time the device is
paused and transitions on these pins will be ignored.
To resume serial communication, HOLD must be
brought high while the SCK pin is low, otherwise serial
communication will not resume. Lowering the HOLD
line at any time will tri-state the SO line.
TABLE 2-1:
PIN FUNCTION TABLE
Name
Pin Number
Function
CS
1
Chip Select Input
SO
2
Serial Data Output
WP
3
Write-Protect Pin
V
SS
4
Ground
SI
5
Serial Data Input
SCK
6
Serial Clock Input
HOLD
7
Hold Input
V
CC
8
Supply Voltage
2009-2018 Microchip Technology Inc.
DS20002131D-page 8
25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/
25LC128/25LC256
3.0
FUNCTIONAL DESCRIPTION
3.1
Principles of Operation
The 25LCXXX are Mid-Density Serial EEPROMs
designed to interface directly with the Serial Peripheral
Interface (SPI) port of many of today’s popular
microcontroller families, including Microchip’s PIC
®
microcontrollers. It may also interface with
microcontrollers that do not have a built-in SPI port by
using discrete I/O lines programmed properly in
firmware to match the SPI protocol.
The 25LCXXX contains an 8-bit instruction register.
The device is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. The CS pin must
be low and the HOLD pin must be high for the entire
operation.
Table 3-1
contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses, and data are transferred Most Significant
bit (MSb) first, Least Significant bit (LSb) last.
Data (SI) is sampled on the first rising edge of SCK
after CS goes low. If the clock line is shared with other
peripheral devices on the SPI bus, the user can assert
the HOLD input and place the 25LCXXX in ‘HOLD’
mode. After releasing the HOLD pin, operation will
resume from the point when the HOLD was asserted.
Block Diagram
SI
SO
SCK
CS
HOLD
WP
STATUS
Register
I/O Control
Memory
Control
Logic
X
Dec
HV Generator
EEPROM
Array
Page Latches
Y Decoder
Sense Amp.
R/W Control
Logic
V
CC
V
SS
TABLE 3-1:
INSTRUCTION SET
Instruction Name
Instruction Format
Description
READ
0000 0011
Read data from memory array beginning at selected address
WRITE
0000 0010
Write data to memory array beginning at selected address
WRDI
0000 0100
Reset the write enable latch (disable write operations)
WREN
0000 0110
Set the write enable latch (enable write operations)
RDSR
0000 0101
Read STATUS register
WRSR
0000 0001
Write STATUS register
2009-2018 Microchip Technology Inc.
DS20002131D-page 9
25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/
25LC128/25LC256
3.2
Read Sequence
The device is selected by pulling CS low. The 8-bit
READ
instruction is transmitted to the 25LCXXX
followed by the 16-bit address. After the correct READ
instruction and address are sent, the data stored in the
memory at the selected address is shifted out on the
SO pin. The data stored in the memory at the next
address can be read sequentially by continuing to
provide clock pulses. The internal Address Pointer is
automatically incremented to the next higher address
after each byte of data is shifted out. When the highest
address is reached, the address counter rolls over to
address 0000h allowing the read cycle to be continued
indefinitely. The read operation is terminated by raising
the CS pin (
Figure 3-1
).
3.3
Write Sequence
Prior to any attempt to write data to the 25LCXXX, the
write enable latch must be set by issuing the WREN
instruction (
Figure 3-4
). This is done by setting CS low
and then clocking out the proper instruction into the
25LCXXX. After all eight bits of the instruction are
transmitted, the CS must be brought high to set the
write enable latch. If the write operation is initiated
immediately after the WREN instruction without CS
being brought high, the data will not be written to the
array because the write enable latch will not have been
properly set.
Once the write enable latch is set, the user may
proceed by setting the CS low, issuing a WRITE instruc-
tion, followed by the 16-bit address, and then the data
to be written. Depending upon the density, a page of
data that ranges from 16 bytes to 64 bytes can be sent
to the device before a write cycle is necessary. The only
restriction is that all of the bytes must reside in the
same page.
For the data to be actually written to the array, the CS
must be brought high after the Least Significant bit (D0)
of the n
th
data byte has been clocked in. If CS is
brought high at any other time, the write operation will
not be completed. Refer to
Figure 3-2
and
Figure 3-3
for more detailed illustrations on the byte write
sequence and the page write sequence, respectively.
While the write is in progress, the STATUS register may
be read to check the status of the WPEN, WIP, WEL,
BP1 and BP0 bits (
Figure 3-6
). A read attempt of a
memory array location will not be possible during a
write cycle. When the write cycle is completed, the
write enable latch is reset.
FIGURE 3-1:
READ SEQUENCE
Note:
Page write operations are limited to
writing bytes within a single physical page,
regardless
of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size
(or ‘page size’) and, end at addresses that
are integer multiples of page size – 1. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
SO
SI
SCK
CS
0
2
3
4
5
6
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
1
0
1
0
0
0
0
0
1
15 14 13 12
2
1
0
7
6
5
4
3
2
1
0
Instruction
16-bit Address
Data Out
High-Impedance
2009-2018 Microchip Technology Inc.
DS20002131D-page 10
25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/
25LC128/25LC256
FIGURE 3-2:
BYTE WRITE SEQUENCE
FIGURE 3-3:
PAGE WRITE SEQUENCE
SO
SI
CS
9 10 11
21 22 23 24 25 26 27 28 29 30 31
0
0
0
0
0
0
0
1
15 14 13 12
2
1
0 7
6
5
4
3
2
1
0
Instruction
16-bit Address
Data Byte
High-Impedance
SCK
0
2
3
4
5
6
7
1
8
Twc
SI
CS
9 10 11
21 22 23 24 25 26 27 28 29 30 31
0
0
0
0
0
0
0
1
15 14 13 12
2
1
0
7
6
5
4
3
2
1
0
Instruction
16-bit Address
Data Byte 1
SCK
0
2
3
4
5
6
7
1
8
SI
CS
41 42 43
46 47
7
6
5
4
3
2
1
0
Data Byte n (16/32/64 max)
SCK
32
34 35 36 37 38 39
33
40
7
6
5
4
3
2
1
0
Data Byte 3
7
6
5
4
3
2
1
0
Data Byte 2
44 45