2007-2015 Microchip Technology Inc.
DS20001836J-page 1
25AA1024
Device Selection Table
Features
• 20 MHz Maximum Clock Speed
• Byte and Page-level Write Operations:
- 256 byte page
- 6 ms maximum write cycle time
- No page or sector erase required
• Low-Power CMOS Technology:
- Maximum Write current: 7 mA at 5.5V
- Maximum Read current: 10 mA at 5.5V,
20 MHz
- Standby current: 1 µA at 2.5V, 85°C
(Deep Power-down)
• Electronic Signature for Device ID
• Self-Timed Erase and Write Cycles:
- Page Erase (6 ms maximum)
- Sector Erase (10 ms maximum)
- Chip Erase (10 ms maximum)
• Sector Write Protection (32K byte/sector):
- Protect none, 1/4, 1/2 or all of array
• Built-in Write Protection:
- Power-on/off data protection circuitry
- Write enable latch
- Write-protect pin
• High Reliability:
- Endurance: 1M erase/write cycles
- Data Retention: >200 years
- ESD Protection: 4000V
• Temperature Ranges Supported:
- Industrial (I):-40°C to +85°C
• RoHS Compliant
Pin Function Table
Description
The Microchip Technology Inc. 25AA1024 is a
1024 Kbit serial EEPROM memory with byte-level and
page-level serial EEPROM functions. It also features
Page, Sector and Chip erase functions typically
associated with Flash-based products. These functions
are not required for byte or page write operations. The
memory is accessed via a simple Serial Peripheral
Interface (SPI) compatible serial bus. The bus signals
required are a clock input (SCK) plus separate data in
(SI) and data out (SO) lines. Access to the device is
controlled by a Chip Select (CS) input.
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused,
transitions on its inputs will be ignored, with the
exception of Chip Select, allowing the host to service
higher priority interrupts.
The 25AA1024 is available in standard packages
including 8-lead PDIP and SOIJ, and advanced 8-lead
DFN package. All devices are RoHS compliant.
Package Types (not to scale)
Part Number
V
CC
Range
Page Size
Temp. Ranges
Packages
25AA1024
1.8-5.5V
256 Byte
I
P, SM, MF
Name
Function
CS
Chip Select Input
SO
Serial Data Output
WP
Write-Protect
V
SS
Ground
SI
Serial Data Input
SCK
Serial Clock Input
HOLD
Hold Input
V
CC
Supply Voltage
25AA1024
CS
SO
WP
V
SS
1
2
3
4
8
7
6
5
V
CC
HOLD
SCK
SI
PDIP/SOIJ
(P, SM)
DFN
CS
SO
WP
V
SS
HOLD
SCK
SI
25AA
1024
5
6
7
8
4
3
2
1
V
CC
(MF)
1 Mbit SPI Bus Serial EEPROM
25AA1024
DS20001836J-page 2
2007-2015 Microchip Technology Inc.
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
V
CC
.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. V
SS
......................................................................................................... -0.6V to V
CC
+1.0V
Storage temperature .................................................................................................................................-65°C to 150°C
Ambient temperature under bias ...............................................................................................................-40°C to 125°C
ESD protection on all pins ..........................................................................................................................................4 kV
TABLE 1-1:
DC CHARACTERISTICS
†
NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability.
DC CHARACTERISTICS
Industrial (I)*:
T
A
= 0°C to +85°C
V
CC
= 1.8V to 5.5V
Industrial (I):
T
A
= -40°C to +85°C
V
CC
= 2.0V to 5.5V
* Limited industrial temperature range.
Param.
No.
Sym.
Characteristic
Min.
Max.
Units
Test Conditions
D001
V
IH
1
High-level Input
Voltage
0.7 V
CC
V
CC
+1
V
D002
V
IL
1
Low-level Input
Voltage
-0.3
0.3 V
CC
V
V
CC
≥ 2.7V
D003
V
IL
2
-0.3
0.2 V
CC
V
V
CC
< 2.7V
D004
V
OL
Low-level Output
Voltage
—
0.4
V
I
OL
= 2.1 mA
D005
V
OL
—
0.2
V
I
OL
= 1.0 mA, V
CC
< 2.5V
D006
V
OH
High-level Output
Voltage
V
CC
-0.2
—
V
I
OH
= -400 µA
D007
I
LI
Input Leakage
Current
—
±1
µA
CS = V
CC
, V
IN
= V
SS
or V
CC
D008
I
LO
Output Leakage
Current
—
±1
µA
CS = V
CC
, V
OUT
= V
SS
or V
CC
D009
C
INT
Internal Capacitance
(all inputs and
outputs)
—
7
pF
T
A
= 25°C, CLK = 1.0 MHz,
V
CC
= 5.0V (
Note
)
D010
I
CCREAD
Operating Current
—
10
mA
V
CC
= 5.5V; F
CLK
= 20.0 MHz;
SO = Open
—
5
mA
V
CC
= 2.5V; F
CLK
= 10.0 MHz;
SO = Open
D011
I
CCWRITE
—
7
mA
V
CC
= 5.5V
—
5
mA
V
CC
= 2.5V
D012
I
CCS
Standby Current
—
12
A
CS = V
CC
= 5.5V, Inputs tied to V
CC
or
V
SS
, 85°C
D013
I
CCSPD
Deep Power-down
Current
—
1
µA
CS = V
CC
= 2.5V, Inputs tied to V
CC
or
V
SS
, 85°C
Note:
This parameter is periodically sampled and not 100% tested.
2007-2015 Microchip Technology Inc.
DS20001836J-page 3
25AA1024
TABLE 1-2:
AC CHARACTERISTICS
AC CHARACTERISTICS
Industrial (I)*:
T
A
= 0°C to +85°C
V
CC
= 1.8V to 5.5V
Industrial (I):
T
A
= -40°C to +85°C
V
CC
= 2.0V to 5.5V
*Limited industrial temperature range.
Param.
No.
Sym.
Characteristic
Min.
Max.
Units
Conditions
1
F
CLK
Clock Frequency
—
20
MHz
4.5 ≤ V
CC
≤ 5.5
—
10
MHz
2.5 ≤ V
CC
< 4.5
—
2
MHz
2.0 ≤ V
CC
< 2.5
1.8 ≤ V
CC
< 2.0, 0°C to +85°C
2
T
CSS
CS Setup Time
25
—
ns
4.5 ≤ V
CC
≤ 5.5
50
—
ns
2.5 ≤ V
CC
< 4.5
250
—
ns
2.0 ≤ V
CC
< 2.5
1.8 ≤ V
CC
< 2.0, 0°C to +85°C
3
T
CSH
CS Hold Time
50
—
ns
4.5 ≤ V
CC
≤ 5.5
100
—
ns
2.5 ≤ V
CC
< 4.5
500
—
ns
2.0 ≤ V
CC
< 2.5
1.8 ≤ V
CC
< 2.0, 0°C to +85°C
(
Note 3
)
4
T
CSD
CS Disable Time
50
—
ns
5
T
SU
Data Setup Time
5
—
ns
4.5 ≤ V
CC
≤ 5.5
10
—
ns
2.5 ≤ V
CC
< 4.5
50
—
ns
2.0 ≤ V
CC
< 2.5
1.8 ≤ V
CC
< 2.0, 0°C to +85°C
6
T
HD
Data Hold Time
10
—
ns
4.5 ≤ V
CC
≤ 5.5
20
—
ns
2.5 ≤ V
CC
< 4.5
100
—
ns
2.0 ≤ V
CC
< 2.5
1.8 ≤ V
CC
< 2.0, 0°C to +85°C
7
T
R
CLK Rise Time
—
20
ns
(
Note 1
)
8
T
F
CLK Fall Time
—
20
ns
(
Note 1
)
9
T
HI
Clock High Time
25
—
4.5 ≤ V
CC
≤ 5.5
50
—
ns
2.5 ≤ V
CC
< 4.5
250
—
ns
2.0 ≤ V
CC
< 2.5
1.8 ≤ V
CC
< 2.0, 0°C to +85°C
10
T
LO
Clock Low Time
25
—
ns
4.5 ≤ V
CC
≤ 5.5
50
—
ns
2.5 ≤ V
CC
< 4.5
250
—
ns
2.0 ≤ V
CC
< 2.5
1.8 ≤ V
CC
< 2.0, 0°C to +85°C
11
T
CLD
Clock Delay Time
50
—
ns
12
T
CLE
Clock Enable Time
50
—
ns
13
T
V
Output Valid from Clock
Low
—
25
ns
4.5 ≤ V
CC
≤ 5.5
—
50
ns
2.5 ≤ V
CC
< 4.5
—
250
ns
2.0 ≤ V
CC
< 2.5
1.8 ≤ V
CC
< 2.0, 0°C to +85°C
Note 1:
This parameter is periodically sampled and not 100% tested.
2:
This parameter is not tested but established by characterization and qualification. For endurance
estimates in a specific application, please consult the Total Endurance™ Model which can be obtained
from Microchip’s web site at www.microchip.com.
3:
Includes T
HI
time.
25AA1024
DS20001836J-page 4
2007-2015 Microchip Technology Inc.
14
T
HO
Output Hold Time
0
—
ns
(
Note 1
)
15
T
DIS
Output Disable Time
—
25
ns
4.5 ≤ V
CC
≤ 5.5
—
50
ns
2.5 ≤ V
CC
< 4.5
—
250
ns
2.0 ≤ V
CC
< 2.5
1.8 ≤ V
CC
< 2.0, 0°C to +85°C
(
Note 1
)
16
T
HS
HOLD Setup Time
10
—
ns
4.5 ≤ V
CC
≤ 5.5
20
—
ns
2.5 ≤ V
CC
< 4.5
100
—
ns
2.0 ≤ V
CC
< 2.5
1.8 ≤ V
CC
< 2.0, 0°C to +85°C
17
T
HH
HOLD Hold Time
10
—
ns
4.5 ≤ V
CC
≤ 5.5
20
—
ns
2.5 ≤ V
CC
< 4.5
100
—
ns
2.0 ≤ V
CC
< 2.5
1.8 ≤ V
CC
< 2.0, 0°C to +85°C
18
T
HZ
HOLD Low to Output
High Z
15
—
ns
4.5 ≤ V
CC
≤ 5.5
30
—
ns
2.5 ≤ V
CC
< 4.5
150
—
ns
2.0 ≤ V
CC
< 2.5
1.8 ≤ V
CC
< 2.0, 0°C to +85°C
(
Note 1
)
19
T
HV
HOLD High to Output
Valid
15
—
ns
4.5 ≤ V
CC
≤ 5.5
30
—
ns
2.5 ≤ V
CC
< 4.5
150
—
ns
2.0 ≤ V
CC
< 2.5
1.8 ≤ V
CC
< 2.0, 0°C to +85°C
20
T
REL
CS High to Standby mode
—
100
µs
V
CC
= 1.8V to 5.5V
21
T
PD
CS High to Deep
Power-down
—
100
µs
V
CC
= 1.8V to 5.5V
22
T
CE
Chip Erase Cycle Time
—
10
ms
V
CC
= 1.8V to 5.5V
23
T
SE
Sector Erase Cycle Time
—
10
ms
V
CC
= 1.8V to 5.5V
24
T
WC
Internal Write Cycle Time
—
6
ms
Byte or Page mode and Page
Erase
25
—
Endurance
1M
—
E/W
cycles
Page mode, 25°C, 5.5V (
Note 2
)
TABLE 1-2:
AC CHARACTERISTICS (CONTINUED)
AC CHARACTERISTICS
Industrial (I)*:
T
A
= 0°C to +85°C
V
CC
= 1.8V to 5.5V
Industrial (I):
T
A
= -40°C to +85°C
V
CC
= 2.0V to 5.5V
*Limited industrial temperature range.
Param.
No.
Sym.
Characteristic
Min.
Max.
Units
Conditions
Note 1:
This parameter is periodically sampled and not 100% tested.
2:
This parameter is not tested but established by characterization and qualification. For endurance
estimates in a specific application, please consult the Total Endurance™ Model which can be obtained
from Microchip’s web site at www.microchip.com.
3:
Includes T
HI
time.
2007-2015 Microchip Technology Inc.
DS20001836J-page 5
25AA1024
TABLE 1-3:
AC TEST CONDITIONS
FIGURE 1-1:
HOLD TIMING
FIGURE 1-2:
SERIAL INPUT TIMING
AC Waveform
V
LO
= 0.2V
—
V
HI
= V
CC
- 0.2V
(
Note 1
)
V
HI
= 4.0V
(
Note 2
)
C
L
= 30 pF
—
Timing Measurement Reference Level
Input
0.5 V
CC
Output
0.5 V
CC
Note 1:
For V
CC
4.0V
2:
For V
CC
> 4.0V
CS
SCK
SO
SI
HOLD
17
16
16
17
19
18
Don’t Care
5
High-Impedance
n + 2
n + 1
n
n - 1
n
n + 2
n + 1
n
n
n - 1
CS
SCK
SI
SO
6
5
8
7
11
3
LSB in
MSB in
High-Impedance
12
Mode 1,1
Mode 0,0
2
4
25AA1024
DS20001836J-page 6
2007-2015 Microchip Technology Inc.
FIGURE 1-3:
SERIAL OUTPUT TIMING
CS
SCK
SO
10
9
13
MSB out
LSB out
3
15
Don’t Care
SI
Mode 1,1
Mode 0,0
14
2007-2015 Microchip Technology Inc.
DS20001836J-page 7
25AA1024
2.0
FUNCTIONAL DESCRIPTION
2.1
Principles of Operation
The 25AA1024 is a 131,072 byte Serial EEPROM
designed to interface directly with the Serial Peripheral
Interface (SPI) port of many of today’s popular
microcontroller families, including Microchip’s PIC
®
microcontrollers. It may also interface with
microcontrollers that do not have a built-in SPI port by
using discrete I/O lines programmed properly in
firmware to match the SPI protocol.
The 25AA1024 contains an 8-bit instruction register.
The device is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. The CS pin must
be low and the HOLD pin must be high for the entire
operation.
Table 2-1
contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses and data are transferred MSB first, LSB last.
Data (SI) is sampled on the first rising edge of SCK
after CS goes low. If the clock line is shared with other
peripheral devices on the SPI bus, the user can assert
the HOLD input and place the 25AA1024 in ‘HOLD’
mode. After releasing the HOLD pin, operation will
resume from the point when the HOLD was asserted.
BLOCK DIAGRAM
TABLE 2-1:
INSTRUCTION SET
SI
SO
SCK
CS
HOLD
WP
STATUS
Register
I/O Control
Memory
Control
Logic
X
Dec
HV Generator
EEPROM
Array
Page Latches
Y Decoder
Sense Amp.
R/W Control
Logic
V
CC
V
SS
Instruction Name
Instruction Format
Description
READ
0000 0011
Read data from memory array beginning at selected address
WRITE
0000 0010
Write data to memory array beginning at selected address
WREN
0000 0110
Set the write enable latch (enable write operations)
WRDI
0000 0100
Reset the write enable latch (disable write operations)
RDSR
0000 0101
Read STATUS register
WRSR
0000 0001
Write STATUS register
PE
0100 0010
Page Erase – erase one page in memory array
SE
1101 1000
Sector Erase – erase one sector in memory array
CE
1100 0111
Chip Erase – erase all sectors in memory array
RDID
1010 1011
Release from Deep Power-down and Read Electronic Signature
DPD
1011 1001
Deep Power-Down mode
25AA1024
DS20001836J-page 8
2007-2015 Microchip Technology Inc.
Read Sequence
The device is selected by pulling CS low. The 8-bit
READ
instruction is transmitted to the 25AA1024
followed by the 24-bit address, with seven MSBs of the
address being “don’t care” bits. After the correct READ
instruction and address are sent, the data stored in the
memory at the selected address is shifted out on the
SO pin.
The data stored in the memory at the next address can
be read sequentially by continuing to provide clock
pulses. The internal Address Pointer is automatically
incremented to the next higher address after each byte
of data is shifted out. When the highest address is
reached (1FFFFh), the address counter rolls over to
address, 00000h, allowing the read cycle to be
continued indefinitely. The read operation is terminated
by raising the CS pin (
Figure 2-1
).
FIGURE 2-1:
READ SEQUENCE
SO
SI
SCK
CS
0
2
3
4
5
6
7
8
9 10 11
29 30 31 32 33 34 35 36 37 38 39
1
0
1
0
0
0
0
0
1
23 22 21 20
2
1
0
7
6
5
4
3
2
1
0
Instruction
24-bit Address
Data Out
High-Impedance
2007-2015 Microchip Technology Inc.
DS20001836J-page 9
25AA1024
2.2
Write Sequence
Prior to any attempt to write data to the 25AA1024, the
write enable latch must be set by issuing the WREN
instruction (
Figure 2-4
). This is done by setting CS low
and then clocking out the proper instruction into the
25AA1024. After all eight bits of the instruction are
transmitted, the CS must be brought high to set the
write enable latch. If the write operation is initiated
immediately after the WREN instruction without CS
being brought high, the data will not be written to the
array because the write enable latch will not have been
properly set.
A write sequence includes an automatic, self-timed
erase cycle. It is not required to erase any portion of the
memory prior to issuing a Write command.
Once the write enable latch is set, the user may
proceed by setting the CS low, issuing a WRITE
instruction, followed by the 24-bit address, with seven
MSBs of the address being “don’t care” bits, and then
the data to be written. Up to 256 bytes of data can be
sent to the device before a write cycle is necessary.
The only restriction is that all of the bytes must reside
in the same page.
For the data to be actually written to the array, the CS
must be brought high after the Least Significant bit (D0)
of the n
th
data byte has been clocked in. If CS is
brought high at any other time, the write operation will
not be completed. Refer to
Figure 2-2
and
Figure 2-3
for more detailed illustrations on the byte write
sequence and the page write sequence, respectively.
While the write is in progress, the STATUS register may
be read to check the status of the WPEN, WIP, WEL,
BP1 and BP0 bits (
Figure 2-6
). A read attempt of a
memory array location will not be possible during a
write cycle. When the write cycle is completed, the
write enable latch is reset.
FIGURE 2-2:
BYTE WRITE SEQUENCE
Note:
When doing a write of less than 256 bytes
the data in the rest of the page is
refreshed along with the data bytes being
written. This will force the entire page to
endure a write cycle, for this reason
endurance is specified per page.
Note:
Page write operations are limited to
writing bytes within a single physical page,
regardless
of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size
(or ‘page size’), and end at addresses that
are integer multiples of page size – 1. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
SO
SI
CS
9 10 11
29 30 31 32 33 34 35 36 37 38 39
0
0
0
0
0
0
0
1
23 22 21 20
2
1
0 7
6
5
4
3
2
1
0
Instruction
24-bit Address
Data Byte
High-Impedance
SCK
0
2
3
4
5
6
7
1
8
T
WC
25AA1024
DS20001836J-page 10
2007-2015 Microchip Technology Inc.
FIGURE 2-3:
PAGE WRITE SEQUENCE
SI
CS
9 10 11
29 30 31 32 33 34 35 36 37 38 39
0
0
0
0
0
0
0
1
23 22 21 20
2
1
0
7
6
5
4
3
2
1
0
Instruction
24-bit Address
Data Byte 1
SCK
0
2
3
4
5
6
7
1
8
SI
CS
49 50 51
54 55
7
6
5
4
3
2
1
0
Data Byte n (256 max.)
SCK
40
42 43 44 45 46 47
41
48
7
6
5
4
3
2
1
0
Data Byte 3
7
6
5
4
3
2
1
0
Data Byte 2
52 53