25AA040A/25LC040A Data Sheet

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 2003-2012 Microchip Technology Inc.

DS21827H-page 1

25AA040A/25LC040A

Device Selection Table

Features:

• Max. Clock 10 MHz
• Low-Power CMOS Technology:

- Max. Write Current: 5 mA at 5.5V, 10 MHz
- Read Current: 5 mA at 5.5V, 10 MHz
- Standby Current: 5 

A at 5.5V

• 512 x 8-Bit Organization
• Write Page mode (up to 16 bytes)
• Sequential Read 
• Self-timed Erase and Write Cycles (5 ms max.)
• Block Write Protection:

- Protect none, 1/4, 1/2 or all of array

• Built-in Write Protection:

- Power-on/off data protection circuitry
- Write enable latch
- Write-protect pin

• High Reliability:

- Endurance: 1,000,000 Erase/Write cycles 
- Data retention: >200 years
- ESD protection: >4000V

• Temperature Ranges Supported:

• Pb-Free and RoHS Compliant

Pin Function Table

Description:

The Microchip Technology Inc. 25XX040A* is a 4 Kbit
Serial Electrically Erasable Programmable Read-Only
Memory (EEPROM). The memory is accessed via a
simple Serial Peripheral Interface (SPI) compatible
serial bus. The bus signals required are a clock input
(SCK) plus separate data in (SI) and data out (SO)
lines. Access to the device is controlled through a Chip
Select (CS) input.
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused, transi-
tions on its inputs will be ignored, with the exception of
Chip Select, allowing the host to service higher priority
interrupts.
The 25XX040A is available in standard packages
including 8-lead PDIP and SOIC, and advanced

packages including 8-lead MSOP, 8-lead TSSOP

and rotated TSSOP, 8-lead 2x3 DFN and TDFN, and
6-lead SOT-23.

Package Types (not to scale)

Part Number

V

CC

 Range

Page Size

Temp. Ranges

Packages

25AA040A

1.8-5.5V

16 Bytes

I

P, MS, SN, ST, MN, MC, OT

25LC040A

2.5-5.5V

16 Bytes

I, E

P, MS, SN, ST, MN, MC, OT

- Industrial (I):

-40

C to +85C

- Automotive (E):

-40

C to +125C

Name

Function

CS

Chip Select Input

SO

Serial Data Output

WP

Write-Protect

V

SS

Ground

SI

Serial Data Input

SCK

Serial Clock Input

HOLD

Hold Input

V

CC

Supply Voltage

CS

SO

WP

V

SS

1
2
3
4

8
7
6
5

V

CC

HOLD
SCK
SI

PDIP/SOIC

(P, SN)

CS

SO

WP

V

SS

1
2
3

4

8
7

6

5

V

CC

HOLD

SCK

SI

CS

SO

WP

V

SS

1
2
3

4

8
7

6

5

V

CC

HOLD

SCK

SI

TSSOP/MSOP

(ST, MS)

X-Rotated TSSOP

HOLD

V

CC

CS

SO

1
2
3

4

8
7

6

5

SCK

SI

V

SS

WP

(X/ST)

V

SS

1

2

3

4

6

5

V

DD

CS

SO

      (OT)

SOT-23

SCK

SI

CS
SO

WP

V

SS

1
2
3
4

8
7
6
5

V

CC

HOLD

SCK

SI

(MC, MN)

DFN/TDFN

4K SPI Bus Serial EEPROM

*25XX040A is used in this document as a generic part number
for the 25AA040A and the 25LC040A.

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25AA040A/25LC040A

DS21827H-page 2

 2003-2012 Microchip Technology Inc.

1.0

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

(†)

V

CC

.............................................................................................................................................................................6.5V

All inputs and outputs w.r.t. V

SS

......................................................................................................... -0.6V to V

CC

 +1.0V

Storage temperature .................................................................................................................................-65°C to 150°C
Ambient temperature under bias ...............................................................................................................-40°C to 125°C
ESD protection on all pins ..........................................................................................................................................4 kV   

TABLE 1-1:

DC CHARACTERISTICS 

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability.

DC CHARACTERISTICS

Industrial (I):

T

A

 = -40°C to +85°C

 V

CC

 = 1.8V to 5.5V

Automotive (E):

T

A

 = -40°C to +125°C

 V

CC

 = 2.5V to 5.5V

Param.

No.

Sym.

Characteristic

Min.

Max.

Units

Test Conditions

D001

V

IH

1

High-level Input 
Voltage

0.7 V

CC

V

CC

 +1

V

D002

V

IL

1

Low-level Input
Voltage

-0.3

0.3 V

CC

V

V

CC

2.7V (

Note 1

)

D003

V

IL

2

-0.3

0.2 V

CC

V

V

CC

 < 2.7V (

Note 1

)

D004

V

OL

Low-level Output
Voltage

0.4

V

I

OL

 = 2.1 mA

D005

V

OL

0.2

V

I

OL

 = 1.0 mA, V

CC

 = 2.5V

D006

V

OH

High-level Output
Voltage

V

CC

 -0.5

V

I

OH

 = -400

A

D007

I

LI

Input Leakage 
Current

±1

A

CS = V

CC

, V

IN

 = V

SS

 or V

CC

D008

I

LO

Output Leakage 
Current

±1

A

CS = V

CC

, V

OUT

 = V

SS

 or V

CC

D009

C

INT

Internal Capacitance
(all inputs and 
outputs)

7

pF

T

A

 = 25°C, CLK = 1.0 MHz,

V

CC

 = 5.0V (

Note 1

)

D010

I

CC

 Read

Operating Current

5

2.5

mA

mA

V

CC

 = 5.5V; F

CLK

 = 10.0 MHz; 

SO = Open
V

CC

 = 2.5V; F

CLK

 = 5.0 MHz; 

SO = Open

D011

I

CC

 Write


5
3

mA
mA

V

CC

 = 5.5V

V

CC

 = 2.5V

D012

I

CCS

Standby Current

5

1

A

A

CS = V

CC

 = 5.5V, Inputs tied to V

CC

 or 

V

SS

, T

A

 = +125°C

CS = V

CC

 = 2.5V, Inputs tied to V

CC

 or 

V

SS

, T

A

 = +85°C

Note 1: This parameter is periodically sampled and not 100% tested.

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DS21827H-page 3

25AA040A/25LC040A

TABLE 1-2:

AC CHARACTERISTICS

AC CHARACTERISTICS

Industrial (I):

T

A

 = -40°C to +85°C

V

CC

 = 1.8V to 5.5V

Automotive (E): T

A

 = -40°C to +125°C

 V

CC

 = 2.5V to 5.5V

Param.

No.

Sym.

Characteristic

Min.

Max.

Units

Test Conditions

1

F

CLK

Clock Frequency



10

5
3

MHz
MHz
MHz

4.5V 

V

CC

 

 5.5V

2.5V 

V

CC

 

 4.5V

1.8V 

V

CC

 

 2.5V

2

T

CSS

CS Setup Time

50

100
150



ns
ns
ns

4.5V 

V

CC

 

 5.5V

2.5V 

V

CC

 

 4.5V

1.8V 

V

CC

 

 2.5V

3

T

CSH

CS Hold Time

100
200
250



ns
ns
ns

4.5V 

V

CC

 

 5.5V

2.5V 

V

CC

 

 4.5V

1.8V 

V

CC

 

 2.5V

4

T

CSD

CS Disable Time

50

ns

5

Tsu

Data Setup Time

10
20
30



ns
ns
ns

4.5V 

V

CC

 

 5.5V

2.5V 

V

CC

 

 4.5V

1.8V 

V

CC

 

 2.5V

6

T

HD

Data Hold Time

20
40
50



ns
ns
ns

4.5V 

V

CC

 

 5.5V

2.5V 

V

CC

 

 4.5V

1.8V 

V

CC

 

 2.5V

7

T

R

CLK Rise Time

100

ns

(

Note 1

)

8

T

F

CLK Fall Time

100

ns

(

Note 1

)

9

T

HI

Clock High Time

50

100
150



ns
ns
ns

4.5V 

V

CC

 

 5.5V

2.5V 

V

CC

 

 4.5V

1.8V 

V

CC

 

 2.5V

10

T

LO

Clock Low Time

50

100
150



ns
ns
ns

4.5V 

V

CC

 

 5.5V

2.5V 

V

CC

 

 4.5V

1.8V 

V

CC

 

 2.5V

11

T

CLD

Clock Delay Time

50

ns

12

T

CLE

Clock Enable Time

50

ns

13

T

V

Output Valid from Clock 
Low



50

100
160

ns
ns
ns

4.5V 

V

CC

 

 5.5V

2.5V 

V

CC

 

 4.5V

1.8V 

V

CC

 

 2.5V

14

T

HO

Output Hold Time

0

ns

(

Note 1

)

15

T

DIS

Output Disable Time



40
80

160

ns
ns
ns

4.5V 

V

CC

 

 5.5V (

Note 1

)

2.5V 

V

CC

 

 4.5V (

Note 1

)

1.8V 

V

CC

 

 2.5V (

Note 1

)

16

T

HS

HOLD Setup Time

20
40
80



ns
ns
ns

4.5V 

V

CC

 

 5.5V

2.5V 

V

CC

 

 4.5V

1.8V 

V

CC

 

 2.5V

Note 1: This parameter is periodically sampled and not 100% tested.

2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site:
www.microchip.com.

3: T

WC

 begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle

is complete.

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25AA040A/25LC040A

DS21827H-page 4

 2003-2012 Microchip Technology Inc.

TABLE 1-3:

AC TEST CONDITIONS

17

T

HH

HOLD Hold Time

20
40
80



ns
ns
ns

4.5V 

V

CC

 

 5.5V

2.5V 

V

CC

 

 4.5V

1.8V 

V

CC

 

 2.5V

18

T

HZ

HOLD Low to Output 
High-Z

30
60

160



ns
ns
ns

4.5V 

V

CC

 

 5.5V (

Note 1

)

2.5V 

V

CC

 

 4.5V (

Note 1

)

1.8V 

V

CC

 

 2.5V (

Note 1

)

19

T

HV

HOLD High to Output 
Valid

30
60

160



ns
ns
ns

4.5V 

V

CC

 

 5.5V

2.5V 

V

CC

 

 4.5V

1.8V 

V

CC

 

 2.5V

20

T

WC

Internal Write Cycle Time 
(byte or page)

5

ms

(

Note 3

)

21

Endurance

1M

E/W 

Cycles

25°C, V

CC

 = 5.5V (

Note 2

)

TABLE 1-2:

AC CHARACTERISTICS (CONTINUED)

AC CHARACTERISTICS

Industrial (I):

T

A

 = -40°C to +85°C

V

CC

 = 1.8V to 5.5V

Automotive (E): T

A

 = -40°C to +125°C

 V

CC

 = 2.5V to 5.5V

Param.

No.

Sym.

Characteristic

Min.

Max.

Units

Test Conditions

Note 1: This parameter is periodically sampled and not 100% tested.

2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site:
www.microchip.com.

3: T

WC

 begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle

is complete.

AC Waveform: 

V

LO

 = 0.2V

V

HI

 = V

CC

 - 0.2V 

(

Note 1

)

V

HI

 = 4.0V

(

Note 2

)

C

L

 = 100 pF

Timing Measurement Reference Level

Input

0.5 V

CC

Output

0.5 V

CC

Note 1: For V

CC

 

 4.0V

2: For V

CC

 

4.0V

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DS21827H-page 5

25AA040A/25LC040A

FIGURE 1-1:

HOLD TIMING

FIGURE 1-2:

SERIAL INPUT TIMING

FIGURE 1-3:

SERIAL OUTPUT TIMING

CS

SCK

SO

SI

HOLD

17

16

16

17

19

18

Don’t Care

5

High-Impedance

n + 2

n + 1

n

n - 1

n

n + 2

n + 1

n

n

n - 1

CS

SCK

SI

SO

6

5

8

7

11

3

LSB in

MSB in

High-Impedance

12

Mode 1,1
Mode 0,0

2

4

CS

SCK

SO

10

9

13

MSB out

ISB out

3

15

Don’t Care

SI

Mode 1,1
Mode 0,0

14

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25AA040A/25LC040A

DS21827H-page 6

 2003-2012 Microchip Technology Inc.

2.0

FUNCTIONAL DESCRIPTION

2.1

Principles of Operation

The 25XX040A is a 512-byte Serial EEPROM
designed to interface directly with the Serial Peripheral
Interface (SPI) port of many of today’s popular
microcontroller families, including Microchip’s PIC

®

microcontrollers. It may also interface with microcon-
trollers that do not have a built-in SPI port by using dis-
crete I/O lines programmed properly in firmware to
match the SPI protocol. 
The 25XX040A contains an 8-bit instruction register.
The device is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. The CS pin must
be low and the HOLD pin must be high for the entire
operation.

Table 2-1

 contains a list of the possible instruction

bytes and format for device operation. All instructions,
addresses and data are transferred MSb first, LSb last.
Data (SI) is sampled on the first rising edge of SCK
after CS goes low. If the clock line is shared with other
peripheral devices on the SPI bus, the user can assert
the HOLD input and place the 25XX040A in ‘HOLD’
mode. After releasing the HOLD pin, operation will
resume from the point when the HOLD was asserted.

2.2

Read Sequence

The device is selected by pulling CS low. The 8-bit
READ instruction is transmitted to the 25XX040A
followed by a 9-bit address. The MSb (A8) is sent to the
slave during the instruction sequence. See Figure 2-1
for more details.
After the correct READ instruction and address are sent,
the data stored in the memory at the selected address
is shifted out on the SO pin. Data stored in the memory
at the next address can be read sequentially by
continuing to provide clock pulses to the slave. The
internal Address Pointer is automatically incremented
to the next higher address after each byte of data is
shifted out. When the highest address is reached
(1FFh), the address counter rolls over to address 000h
allowing the read cycle to be continued indefinitely. The
read operation is terminated by raising the CS pin
(

Figure 2-1

).

2.3

Write Sequence

Prior to any attempt to write data to the 25XX040A, the
write enable latch must be set by issuing the WREN
instruction (

Figure 2-4

). This is done by setting CS low

and then clocking out the proper instruction into the
25XX040A. After all eight bits of the instruction are
transmitted, CS must be driven high to set the write
enable latch.

If the write operation is initiated immediately after the
WREN

 instruction without CS driven high, data will not

be written to the array since the write enable latch was
not properly set.
After setting the write enable latch, the user may
proceed by driving CS low, issuing a WRITE instruction,
followed by the remainder of the address, and then the
data to be written. Keep in mind that the Most
Significant address bit (A8) is included in the instruction
byte for the 25XX040A. Up to 16 bytes of data can be
sent to the device before a write cycle is necessary.
The only restriction is that all of the bytes must reside
in the same page. Additionally, a page address begins
with ‘XXXX 0000’ and ends with ‘XXXX 1111’. If the
internal address counter reaches ‘XXXX 1111’ and
clock signals continue to be applied to the chip, the
address counter will roll back to the first address of the
page and over-write any data that previously existed in
those locations.

For the data to be actually written to the array, the CS
must be brought high after the Least Significant bit (D0)
of the n

th

 data byte has been clocked in. If CS is driven

high at any other time, the write operation will not be
completed. Refer to 

Figure 2-2

 and 

Figure 2-3

 for more

detailed illustrations on the byte write sequence and
the page write sequence, respectively. While the write
is in progress, the STATUS register may be read to
check the status of the WPEN, WIP, WEL, BP1 and
BP0 bits (

Figure 2-6

). Attempting to read a memory

array location will not be possible during a write cycle.
Polling the WIP bit in the STATUS register is recom-
mended in order to determine if a write cycle is in prog-
ress. When the write cycle is completed, the write
enable latch is reset.

Note:

Page write operations are limited to
writing bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size
(or ‘page size’) and, end at addresses that
are integer multiples of page size – 1. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.

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DS21827H-page 7

25AA040A/25LC040A

BLOCK DIAGRAM

FIGURE 2-1:

READ SEQUENCE

SI

SO

SCK

CS

HOLD

WP

STATUS

Register

I/O Control

Memory

Control

Logic

X

Dec

HV Generator

EEPROM

Array

Page Latches

Y Decoder

Sense Amp.
R/W Control

Logic

V

CC

V

SS

TABLE 2-1:

INSTRUCTION SET

Instruction Name

Instruction Format

Description

READ

0000 A

8

011

Read data from memory array beginning at selected address

WRITE

0000 A

8

010

Write data to memory array beginning at selected address

WRDI

0000 x100

Reset the write enable latch (disable write operations)

WREN

0000 x110

Set the write enable latch (enable write operations)

RDSR

0000 x101

Read STATUS register

WRSR

0000 x001

Write STATUS register 

Note:

A

8

 is the 9

th

 address bit, which is used to address the entire 512 byte array.

x

 = don’t care.

SO

SI

SCK

CS

0

2

3

4

5

6

7

8

9 10 11

1

0

1

A

8

0

0

0

0

1

A

7

A

6

A

5

A

4

A

1

A

0

7

6

5

4

3

2

1

0

Data Out

High-Impedance

A

3

A

2

Lower Address Byte

12 13 14 15 16 17 18 19 20 21 22 23

Instruction+Address MSb

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25AA040A/25LC040A

DS21827H-page 8

 2003-2012 Microchip Technology Inc.

FIGURE 2-2:

BYTE WRITE SEQUENCE

FIGURE 2-3:

PAGE WRITE SEQUENCE

SI

CS

9 10 11

0

0

A

8

0

0

0

0

1

7

6

5

4

3

2

1

0

Data Byte 

SCK

0

2

3

4

5

6

7

1

8

Instruction+Address MSb

Lower Address Byte

A

7

A

6

A

5

A

4

A

3

A

1

A

0

A

2

12 13 14 15 16 17 18 19 20 21 22 23

Twc

SO

High-Impedance

SI

CS

9 10 11

0

0

A

8

0

0

0

0

1

7

6

5

4

3

2

1

0

Data Byte 1

SCK

0

2

3

4

5

6

7

1

8

SI

CS

33 34 35

38 39

7

6

5

4

3

2

1

0

Data Byte n (16 max.)

SCK

24

26 27 28 29 30 31

25

32

7

6

5

4

3

2

1

0

Data Byte 3

7

6

5

4

3

2

1

0

Data Byte 2

36 37

Instruction+Address MSb

Lower Address Byte

A

7

A

6

A

5

A

4

A

3

A

1

A

0

A

2

12 13 14 15 16 17 18 19 20 21 22 23

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 2003-2012 Microchip Technology Inc.

DS21827H-page 9

25AA040A/25LC040A

2.4

Write Enable (WREN) and Write 
Disable (WRDI)

The 25XX040A contains a write enable latch.   See

Table 2-4

 for the Write-Protect Functionality Matrix.

This latch must be set before any write operation will be
completed internally. The WREN instruction will set the
latch, and the WRDI will reset the latch. 

The following is a list of conditions under which the
write enable latch will be reset:
• Power-up
• WRDI instruction successfully executed
• WRSR instruction successfully executed
• WRITE instruction successfully executed
• WP pin is brought low

FIGURE 2-4:

WRITE ENABLE SEQUENCE (WREN)

FIGURE 2-5:

WRITE DISABLE SEQUENCE (WRDI)

SCK

0

2

3

4

5

6

7

1

SI

High-Impedance

SO

CS

0

1

0

0

0

0

0

1

SCK

0

2

3

4

5

6

7

1

SI

High-Impedance

SO

CS

0

1

0

0

0

0

0

10

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25AA040A/25LC040A

DS21827H-page 10

 2003-2012 Microchip Technology Inc.

2.5

Read Status Register Instruction 
(RDSR)

The Read Status Register instruction (RDSR) provides
access to the STATUS register. See 

Figure 2-6

 for the

RDSR

 timing sequence. The STATUS register may be

read at any time, even during a write cycle. The
STATUS register is formatted as follows:

TABLE 2-2:

STATUS REGISTER

The Write-In-Process (WIP) bit indicates whether the
25XX040A is busy with a write operation. When set to
a ‘

1

’, a write is in progress, when set to a ‘

0

’, no write

is in progress. This bit is read-only.

The Write Enable Latch (WEL) bit indicates the status
of the write enable latch and is read-only. When set to
a ‘

1

’, the latch allows writes to the array, when set to a

0

’, the latch prohibits writes to the array. The state of

this bit can always be updated via the WREN or WRDI
commands regardless of the state of write protection
on the STATUS register. These commands are shown
in 

Figure 2-4

 and 

Figure 2-5

.

The  Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction, which
is shown in Figure 2-7. These bits are nonvolatile and
are described in more detail in 

Table 2-3

.

FIGURE 2-6:

READ STATUS REGISTER TIMING SEQUENCE (RDSR)

7

6

5

4

3

2

1

0

W/R

W/R

R

R

X

X

X

X

BP1

BP0

WEL

WIP

W/R = writable/readable.  R = read-only.

SO

SI

CS

9

10

11

12

13

14

15

1

1

0

0

0

0

0

0

7

6

5

4

2

1

0

Instruction

Data from STATUS Register

High-Impedance

SCK

0

2

3

4

5

6

7

1

8

3

Maker
Microchip Technology Inc.
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