A Microchip Technology Company
©2011 Silicon Storage Technology, Inc.
DS25041A
05/11
Data Sheet
www.microchip.com
8 Mbit (x16) Multi-Purpose Flash Plus
SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C
Features
• Organized as 512K x16
• Single Voltage Read and Write Operations
– 2.7-3.6V for SST39VF801C/802C
– 3.0-3.6V for SST39LF801C/802C
• Superior Reliability
– Endurance: 100,000 Cycles (Typical)
– Greater than 100 years Data Retention
• Low Power Consumption (typical values at 5 MHz)
– Active Current: 5 mA (typical)
– Standby Current: 3 µA (typical)
– Auto Low Power Mode: 3 µA (typical)
• Hardware Block-Protection/WP# Input Pin
– Top Block-Protection (top 8 KWord)
– Bottom Block-Protection (bottom 8 KWord)
• Sector-Erase Capability
– Uniform 2 KWord sectors
• Block-Erase Capability
– Flexible block architecture; one 8-, two 4-, one 16-, and
fifteen 32-KWord blocks
• Chip-Erase Capability
• Erase-Suspend/Erase-Resume Capabilities
• Hardware Reset Pin (RST#)
• Latched Address and Data
• Security-ID Feature
– SST: 128 bits; User: 128 words
• Fast Read Access Time:
– 70 ns for SST39VF801C/802C
– 55 ns for SST39LF801C/802C
• Fast Erase and Word-Program:
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 40 ms (typical)
– Word-Program Time: 7 µs (typical)
• Automatic Write Timing
– Internal V
PP
Generation
• End-of-Write Detection
– Toggle Bits
– Data# Polling
– Ready/Busy# Pin
• CMOS I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pinouts and command sets
• Packages Available
– 48-lead TSOP (12mm x 20mm)
– 48-ball TFBGA (6mm x 8mm)
– 48-ball WFBGA (4mm x 6mm)
• All devices are RoHS compliant
The SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C are 512K
x16 CMOS Multi-Purpose Flash Plus (MPF+) manufactured with SST proprietary,
high performance CMOS SuperFlash® technology. The split-gate cell design and
thick-oxide tunneling injector attain better reliability and manufacturability com-
pared with alternate approaches. The SST39VF801C / SST39VF802C /
SST39LF801C / SST39LF802C write (Program or Erase) with a 2.7-3.6V power
supply. These devices conforms to JEDEC standard pinouts for x16 memories.
©2011 Silicon Storage Technology, Inc.
DS25041A
05/11
2
8 Mbit (x16) Multi-Purpose Flash Plus
SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C
Data Sheet
A Microchip Technology Company
Product Description
The SST39VF801C/802C and SST39LF801C/802C devices are 512K x16 CMOS Multi-Purpose Flash
Plus (MPF+) manufactured with SST proprietary, high performance CMOS SuperFlash technology.
The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability
compared with alternate approaches. The SST39VF801C/802C and SST39LF801C/802C write (Program
or Erase) with a 2.7-3.6V power supply. These devices conform to JEDEC standard pinouts for x16
memories.
Featuring high performance Word-Program, the SST39VF801C/802C and SST39LF801C/802C
devices provide a typical Word-Program time of 7 µsec. These devices use Toggle Bit, Data# Polling,
or the RY/BY# pin to indicate the completion of Program operation. To protect against inadvertent
write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured,
and tested for a wide spectrum of applications, these devices are offered with a guaranteed typical
endurance of 100,000 cycles. Data retention is rated at greater than 100 years.
The SST39VF801C/802C and SST39LF801C/802C devices are suited for applications that require
convenient and economical updating of program, configuration, or data memory. For all system appli-
cations, they significantly improve performance and reliability, while lowering power consumption. They
inherently use less energy during Erase and Program than alternative flash technologies. The total
energy consumed is a function of the applied voltage, current, and time of application. Since for any
given voltage range, the SuperFlash technology uses less current to program and has a shorter erase
time, the total energy consumed during any Erase or Program operation is less than alternative flash
technologies. These devices also improve flexibility while lowering the cost for program, data, and con-
figuration storage applications.
The SuperFlash technology provides fixed Erase and Program times, independent of the number of
Erase/Program cycles that have occurred. Therefore the system software or hardware does not have
to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Pro-
gram times increase with accumulated Erase/Program cycles.
To meet high density, surface mount requirements, the SST39VF801C/802C and SST39LF801C/802C
are offered in 48-lead TSOP, 48-ball TFBGA, and 48-ball WFBGA packages. See Figures 2, 3, and 4
for pin assignments.
©2011 Silicon Storage Technology, Inc.
DS25041A
05/11
3
8 Mbit (x16) Multi-Purpose Flash Plus
SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C
Data Sheet
A Microchip Technology Company
Block Diagrams
Figure 1: Functional Block Diagram
Y-Decoder
I/O Buffers and Data Latches
1434 B1.0
Address Buffer Latches
X-Decoder
DQ
15
- DQ
0
Memory Address
OE#
CE#
WE#
SuperFlash
Memory
Control Logic
WP#
RESET#
RY/BY#
©2011 Silicon Storage Technology, Inc.
DS25041A
05/11
4
8 Mbit (x16) Multi-Purpose Flash Plus
SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C
Data Sheet
A Microchip Technology Company
Pin Assignment
Figure 2: Pin Assignments for 48-Lead TSOP
Figure 3: Pin Assignments for 48-Ball TFBGA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1434 48-tsop EK P1.0
Standard Pinout
Top View
Die Up
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RST#
NC
WP#
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
A13
A9
WE#
RY/BY#
A7
A3
A12
A8
RST#
WP#
A17
A4
A14
A10
NC
A18
A6
A2
A15
A11
NC
NC
A5
A1
A16
DQ7
DQ5
DQ2
DQ0
A0
NC
DQ14
DQ12
DQ10
DQ8
CE#
DQ15
DQ13
VDD
DQ11
DQ9
OE#
VSS
DQ6
DQ4
DQ3
DQ1
VSS
1434 48-tfbga B3K P2.0
TOP VIEW (balls facing down)
6
5
4
3
2
1
A
B
C
D
E
F
G
H
©2011 Silicon Storage Technology, Inc.
DS25041A
05/11
5
8 Mbit (x16) Multi-Purpose Flash Plus
SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C
Data Sheet
A Microchip Technology Company
Figure 4: Pin Assignments for 48-Ball WFBGA
Table 1: Pin Description
Symbol
Pin Name
Functions
A
MS
1
-A
0
1. A
MS
= Most significant address
A
MS
= A
18
Address Inputs
To provide memory addresses.
During Sector-Erase A
MS
-A
11
address lines will select the sector.
During Block-Erase A
MS
-A
15
address lines will select the block.
DQ
15
-DQ
0
Data Input/output To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
WP#
Write Protect
To protect the top/bottom boot block from Erase/Program operation when
grounded.
RST#
Reset
To reset and return the device to Read mode.
CE#
Chip Enable
To activate the device when CE# is low.
OE#
Output Enable
To gate the data output buffers.
WE#
Write Enable
To control the Write operations.
V
DD
Power Supply
To provide power supply voltage: 2.7-3.6V
V
SS
Ground
NC
No Connection
Unconnected pins.
RY/BY#
Ready/Busy#
To output the status of a Program or Erase operation
RY/BY# is a open drain output, so a 10K
- 100K pull-up resistor is required
to allow RY/BY# to transition high indicating the device is ready to read.
T1.2 25041
A2
A1
A0
CE#
VSS
A4
A3
A5
DQ8
OE#
DQ0
A6
A7
A18
DQ10
DQ9
DQ1
A17
WP#
NC
DQ2
NC
DQ3
NC
VDD
WE#
DQ12
RST#
RY/BY#
NC
DQ13
A9
A10
A8
DQ4
DQ5
DQ14
A11
A13
A12
DQ11
DQ6
DQ15
A14
A15
A16
DQ7
VSS
TOP VIEW (balls facing down)
A B C D E F G H J K L
6
5
4
3
2
1
1434 48-wfbga MAQ P3.0
©2011 Silicon Storage Technology, Inc.
DS25041A
05/11
6
8 Mbit (x16) Multi-Purpose Flash Plus
SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C
Data Sheet
A Microchip Technology Company
Table 2: Top / Bottom Boot Block Address
Top Boot Block Address
SST39VF802C/SST39LF802C
Bottom Boot Block Address
SST39VF801C/SST39LF801C
#
Size
(KWord)
Address Range
#
Size
(KWord)
Address Range
18
8
7E000H-7FFFFH
18
32
78000H-7FFFFH
17
4
7D000H-7DFFFH
17
32
70000H-77FFFH
16
4
7C000H-7CFFFH
16
32
68000H-6FFFFH
15
16
78000H-7BFFFH
15
32
60000H-67FFFH
14
32
70000H-77FFFH
14
32
58000H-5FFFFH
13
32
68000H-6FFFFH
13
32
50000H-57FFFH
12
32
60000H-67FFFH
12
32
48000H-4FFFFH
11
32
58000H-5FFFFH
11
32
40000H-47FFFH
10
32
50000H-57FFFH
10
32
38000H-3FFFFH
9
32
48000H-4FFFFH
9
32
30000H-37FFFH
8
32
40000H-47FFFH
8
32
28000H-2FFFFH
7
32
38000H-3FFFFH
7
32
20000H-27FFFH
6
32
30000H-37FFFH
6
32
18000H-1FFFFH
5
32
28000H-2FFFFH
5
32
10000H-17FFFH
4
32
20000H-27FFFH
4
32
08000H-0FFFFH
3
32
18000H-1FFFFH
3
16
04000H-07FFFH
2
32
10000H-17FFFH
2
4
03000H-03FFFH
1
32
08000H-0FFFFH
1
4
02000H-02FFFH
0
32
00000H-07FFFH
0
8
00000H-01FFFH
T2.25041
©2011 Silicon Storage Technology, Inc.
DS25041A
05/11
7
8 Mbit (x16) Multi-Purpose Flash Plus
SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C
Data Sheet
A Microchip Technology Company
Device Operation
Commands are used to initiate the memory operation functions of the device. Commands are written
to the device using standard microprocessor write sequences. A command is written by asserting WE#
low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever
occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.
The SST39VF801C/802C and SST39LF801C/802C also have the Auto Low Power mode which puts
the device in a near standby mode after data has been accessed with a valid Read operation. This
reduces the I
DD
active read current from typically 5 mA to typically 3 µA. The Auto Low Power mode
reduces the typical I
DD
active read current to the range of 2 mA/MHz of Read cycle time. The device
exits the Auto Low Power mode with any address transition or control signal transition used to initiate
another Read cycle, with no access time penalty. Note that the device does not enter Auto-Low Power
mode after power-up with CE# held steadily low, until the first address transition or CE# is driven high.
Read
The Read operation of the SST39VF801C/802C and SST39LF801C/802C is controlled by CE# and OE#,
both have to be low for the system to obtain data from the outputs. CE# is used for device selection.
When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output con-
trol and is used to gate data from the output pins. The data bus is in high impedance state when either
CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 6).
Word-Program Operation
The SST39VF801C/802C and SST39LF801C/802C are programmed on a word-by-word basis. Before
programming, the sector where the word exists must be fully erased. The Program operation is accom-
plished in three steps. The first step is the three-byte load sequence for Software Data Protection. The
second step is to load word address and word data. During the Word-Program operation, the
addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is
latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal
Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs
first. The Program operation, once initiated, will be completed within 10 µs. See Figures 7 and 8 for
WE# and CE# controlled Program operation timing diagrams and Figure 22 for flowcharts. During the
Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program
operation, the host is free to perform additional tasks. Any commands issued during the internal Pro-
gram operation are ignored. During the command sequence, WP# should be statically held high or low.
Sector/Block-Erase Operation
The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or
block-by-block) basis. The SST39VF801C/802C and SST39LF801C/802C offer both Sector-Erase and
Block-Erase mode.
The sector architecture is based on a uniform sector size of 2 KWord. The Block-Erase mode is based
on non-uniform block sizes—fifteen 32 KWord, one 16 KWord, two 4 KWord, and one 8 KWord blocks.
See Figure 2 for top and bottom boot device block addresses. The Sector-Erase operation is initiated
by executing a six-byte command sequence with Sector-Erase command (50H) and sector address
(SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command
sequence with Block-Erase command (30H) and block address (BA) in the last bus cycle. The sector
or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or
50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the
©2011 Silicon Storage Technology, Inc.
DS25041A
05/11
8
8 Mbit (x16) Multi-Purpose Flash Plus
SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C
Data Sheet
A Microchip Technology Company
sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Toggle
Bit methods. See Figures 12 and 13 for timing waveforms and Figure 26 for the flowchart. Any com-
mands issued during the Sector- or Block-Erase operation are ignored. When WP# is low, any attempt
to Sector- (Block-) Erase the protected block will be ignored. During the command sequence, WP#
should be statically held high or low.
Erase-Suspend/Erase-Resume Commands
The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing
data to be read from any memory location, or program data into any sector/block that is not suspended
for an Erase operation. The operation is executed by issuing one byte command sequence with Erase-
Suspend command (B0H). The device automatically enters read mode typically within 20 µs after the
Erase-Suspend command had been issued. Valid data can be read from any sector or block that is not
suspended from an Erase operation. Reading at address location within erase-suspended sectors/
blocks will output DQ
2
toggling and DQ
6
at ‘1’. While in Erase-Suspend mode, a Word-Program opera-
tion is allowed except for the sector or block selected for Erase-Suspend.
To resume Sector-Erase or Block-Erase operation which has been suspended the system must issue
Erase Resume command. The operation is executed by issuing one byte command sequence with
Erase Resume command (30H) at any address in the last Byte sequence.
Chip-Erase Operation
The SST39VF801C/802C and SST39LF801C/802C provide a Chip-Erase operation, which allows the
user to erase the entire memory array to the ‘1’ state. This is useful when the entire device must be
quickly erased.
The Chip-Erase operation is initiated by executing a six-byte command sequence with Chip-Erase
command (10H) at address 555H in the last byte sequence. The Erase operation begins with the rising
edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is
Toggle Bit or Data# Polling. See Table 7 for the command sequence, Figure 11 for timing diagram, and
Figure 26 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. When
WP# is low, any attempt to Chip-Erase will be ignored. During the command sequence, WP# should
be statically held high or low.
Write Operation Status Detection
The SST39VF801C/802C and SST39LF801C/802C provide two software means to detect the comple-
tion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time. The software
detection includes two status bits: Data# Polling (DQ
7
) and Toggle Bit (DQ
6
). The End-of-Write detec-
tion mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase opera-
tion.
The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a
Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this
occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with
either DQ
7
or DQ
6
. In order to prevent spurious rejection, if an erroneous result occurs, the software
routine should include a loop to read the accessed location an additional two (2) times. If both reads
are valid, then the device has completed the Write cycle, otherwise the rejection is valid.
©2011 Silicon Storage Technology, Inc.
DS25041A
05/11
9
8 Mbit (x16) Multi-Purpose Flash Plus
SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C
Data Sheet
A Microchip Technology Company
Ready/Busy# (RY/BY#)
The devices include a Ready/Busy# (RY/BY#) output signal. RY/BY# is an open drain output pin that
indicates whether an Erase or Program operation is in progress. Since RY/BY# is an open drain out-
put, it allows several devices to be tied in parallel to V
DD
via an external pull-up resistor. After the rising
edge of the final WE# pulse in the command sequence, the RY/BY# status is valid.
When RY/BY# is actively pulled low, it indicates that an Erase or Program operation is in progress.
When RY/BY# is high (Ready), the devices may be read or left in standby mode.
Data# Polling (DQ
7
)
When the SST39VF801C/802C and SST39LF801C/802C are in the internal Program operation, any
attempt to read DQ
7
will produce the complement of the true data. Once the Program operation is
completed, DQ
7
will produce true data. Note that even though DQ
7
may have valid data immediately follow-
ing the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on
the entire data bus will appear in subsequent successive Read cycles after an interval of 1 µs. During internal
Erase operation, any attempt to read DQ
7
will produce a ‘0’. Once the internal Erase operation is com-
pleted, DQ
7
will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#)
pulse for Program operation. For Sector-, Block- or Chip-Erase, the Data# Polling is valid after the ris-
ing edge of sixth WE# (or CE#) pulse. See Figure 9 for Data# Polling timing diagram and Figure 23 for
a flowchart.
Toggle Bits (DQ6 and DQ2)
During the internal Program or Erase operation, any consecutive attempts to read DQ
6
will produce
alternating ‘1’s and ‘0’s, i.e., toggling between 1 and 0. When the internal Program or Erase operation
is completed, the DQ
6
bit will stop toggling. The device is then ready for the next operation. For Sector-
, Block-, or Chip-Erase, the toggle bit (DQ
6
) is valid after the rising edge of sixth WE# (or CE#) pulse.
DQ
6
will be set to ‘1’ if a Read operation is attempted on an Erase-Suspended Sector/Block. If Pro-
gram operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ
6
will toggle.
An additional Toggle Bit is available on DQ
2
, which can be used in conjunction with DQ
6
to check
whether a particular sector is being actively erased or erase-suspended. Table 3 shows detailed status
bits information. The Toggle Bit (DQ
2
) is valid after the rising edge of the last WE# (or CE#) pulse of
Write operation. See Figure 10 for Toggle Bit timing diagram and Figure 23 for a flowchart.
Note: DQ
7
and DQ
2
require a valid address when reading status information.
Table 3: Write Operation Status
Status
DQ
7
DQ
6
DQ
2
RY/BY#
Normal Operation
Standard Program
DQ
7
#
Toggle
No Toggle
0
Standard Erase
0
Toggle
Toggle
0
Erase-Suspend
Mode
Read from Erase-Sus-
pended Sector/Block
1
1
Toggle
1
Read from Non-Erase-
Suspended Sector/Block
Data
Data
Data
1
Program
DQ
7
#
Toggle
N/A
0
T3.0 25041
©2011 Silicon Storage Technology, Inc.
DS25041A
05/11
10
8 Mbit (x16) Multi-Purpose Flash Plus
SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C
Data Sheet
A Microchip Technology Company
Data Protection
The SST39VF801C/802C and SST39LF801C/802C provide both hardware and software features to pro-
tect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle.
V
DD
Power Up/Down Detection: The Write operation is inhibited when V
DD
is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This pre-
vents inadvertent writes during power-up or power-down.
Hardware Block Protection
The SST39VF802C/SST39LF802C support top hardware block protection, which protects the top 8
KWord block of the device. The SST39VF801C/SST39LF801C support bottom hardware block protec-
tion, which protects the bottom 8KWord block of the device. The Boot Block address ranges are
described in Table 4. Program and Erase operations are prevented on the 8 KWord when WP# is low.
If WP# is left floating, it is internally held high via a pull-up resistor, and the Boot Block is unprotected,
enabling Program and Erase operations on that block.
Hardware Reset (RST#)
The RST# pin provides a hardware method of resetting the device to read array data. When the RST#
pin is held low for at least T
RP,
any in-progress operation will terminate and return to Read mode. When
no internal Program/Erase operation is in progress, a minimum period of T
RHR
is required after RST#
is driven high before a valid Read can take place (see Figure 18).
The Erase or Program operation that has been interrupted needs to be re-initiated after the device
resumes normal operation mode to ensure data integrity.
Software Data Protection (SDP)
The SST39VF801C/802C and SST39LF801C/802C provide the JEDEC approved Software Data Pro-
tection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation
requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the
Program operation, providing optimal protection from inadvertent Write operations, e.g., during the
system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence.
These devices are shipped with the Software Data Protection permanently enabled. See Table 7 for
Table 4: Boot Block Address Ranges
Product
Address Range
Bottom Boot Block
SST39VF801C/SST39LF801C
00000H - 01FFFH
Top Boot Block
SST39VF802C/SST39LF802C
7E000H - 7FFFFH
T4.0 25041