©2012 Silicon Storage Technology, Inc.
DS25024C
10/12
Not Recommended for New Designs
www.microchip.com
Features
• Single Voltage Read and Write Operations
– 1.65-1.95V
• Serial Interface Architecture
– SPI Compatible: Mode 0 and Mode 3
• High Speed Clock Frequency
– 75 MHz
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Ultra-Low Power Consumption:
– Active Read Current: 2 mA (typical @ 33 MHz)
– Standby Current: 5 µA (typical)
• Flexible Erase Capability
– Uniform 4 KByte sectors
– Uniform 32 KByte overlay blocks
– Uniform 64 KByte overlay blocks
• Fast Erase and Byte-Program:
– Chip-Erase Time: 35 ms (typical)
– Sector-/Block-Erase Time: 18 ms (typical)
– Byte-Program Time: 14 µS (typical)
• Auto Address Increment (AAI) Programming
– Decrease total chip programming time over Byte-Pro-
gram operations
• End-of-Write Detection
– Software polling the BUSY bit in Status Register
– Busy Status readout on SO pin
• Reset Pin (RST#) or Programmable Hold Pin
(HOLD#) option
– Hardware Reset pin as default
– Hold pin option to suspend a serial sequence without
deselecting the device
• Write Protection (WP#)
– Enables/Disables the Lock-Down function of the status
register
• Software Write Protection
– Write protection through Block-Protection bits in status
register
• Temperature Range
– Industrial: -40°C to +85°C
• Packages Available
– 8-lead SOIC (150 mils)
– 8-bump XFBGA
• All devices are RoHS compliant
8 Mbit 1.8V SPI Serial Flash
SST25WF080
The SST25WF080 is a member of the Serial Flash 25 Series family and features
a four-wire, SPI-compatible interface that allows for a low pin-count package
which occupies less board space and ultimately lowers total system costs.
SST25WF080 SPI serial flash memory is manufactured with SST proprietary,
high-performance CMOS SuperFlash technology. The split-gate cell design and
thick-oxide tunneling injector attain better reliability and manufacturability com-
pared with alternate approaches.
Not recommended for new designs. Please
contact Microchip Sales for more details.
©2012 Silicon Storage Technology, Inc.
DS25024C
10/12
2
8 Mbit 1.8V SPI Serial Flash
SST25WF080
Not Recommended for New Designs
Product Description
The SST25WF080 is a member of the Serial Flash 25 Series family and features a four-wire, SPI-com-
patible interface that allows for a low pin-count package which occupies less board space and ulti-
mately lowers total system costs. SST25WF080 SPI serial flash memory is manufactured with SST
proprietary, high-performance CMOS SuperFlash technology. The split-gate cell design and thick-
oxide tunneling injector attain better reliability and manufacturability compared with alternate
approaches.
The SST25WF080 significantly improves performance and reliability, while lowering power consump-
tion. The device writes (Program or Erase) with a single power supply of 1.65-1.95V for SST25WF080.
The total energy consumed is a function of the applied voltage, current, and time of application. Since
for any given voltage range, the SuperFlash technology uses less current to program and has a shorter
erase time, the total energy consumed during any Erase or Program operation is less than alternative
flash memory technologies.
The SST25WF080 is offered in both an 8-lead, 150 mils SOIC package and an 8-bump XFBGA pack-
age. See Figures 2 and 3 for the pin assignments.
©2012 Silicon Storage Technology, Inc.
DS25024C
10/12
3
8 Mbit 1.8V SPI Serial Flash
SST25WF080
Not Recommended for New Designs
Block Diagram
Figure 1: Functional Block Diagram
1203 F01.0
I/O Buffers
and
Data Latches
SuperFlash
Memory
X - Decoder
Control Logic
Address
Buffers
and
Latches
CE#
Y - Decoder
SCK
SI
SO
WP#
RST#/HOLD#
Serial Interface
Note: In AAI mode, the SO pin functions as an RY/BY# pin when configured as a ready/
busy status pin. See “End-of-Write Detection” on page 15 for more information.
©2012 Silicon Storage Technology, Inc.
DS25024C
10/12
4
8 Mbit 1.8V SPI Serial Flash
SST25WF080
Not Recommended for New Designs
Pin Description
Figure 2: Pin Assignment for 8-Lead SOIC
Figure 3: Pin Assignment for 8-bump XFBGA
1
2
3
4
8
7
6
5
CE#
SO
WP#
V
SS
V
DD
RST#/HOLD#
SCK
SI
Top View
1203.25WF 08-soic-P0.0
Top View
(Balls Facing Down)
1328.25WF 8-xfbga P1.0
SI
V
SS
SCK
WP#
SO
V
DD
CE#
A B C D
2
1
RST#/
HOLD#
©2012 Silicon Storage Technology, Inc.
DS25024C
10/12
5
8 Mbit 1.8V SPI Serial Flash
SST25WF080
Not Recommended for New Designs
Table 1: Pin Description
Symbol
Pin Name
Functions
SCK
Serial Clock
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock input,
while output data is shifted out on the falling edge of the clock input.
SI
Serial Data Input
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
SO
Serial Data Out-
put
To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
Flash busy status pin in AAI mode if SO is configured as a hardware RY/BY# pin. See
“End-of-Write Detection” on page 15 for more information.
CE#
Chip Enable
The device is enabled by a high to low transition on CE#. CE# must remain low for the
duration of any command sequence.
WP#
Write Protect
The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
RST#/
HOLD#
Reset
To reset the operation of the device and the internal logic. The device powers on with
RST# pin functionality as default.
Hold
To temporarily stop serial communication with SPI Flash memory while device is
selected. This is selected by an instruction sequence; see “Reset/Hold Mode” on page 7.
V
DD
Power Supply
To provide power supply voltage: 1.65-1.95V for SST25WF080
V
SS
Ground
T1.0 25024
©2012 Silicon Storage Technology, Inc.
DS25024C
10/12
6
8 Mbit 1.8V SPI Serial Flash
SST25WF080
Not Recommended for New Designs
Memory Organization
The SST25WF080 SuperFlash memory arrays are organized in uniform 4 KByte sectors with 16 KByte,
32 KByte, and 64 KByte overlay erasable blocks.
Device Operation
The SST25WF080 are accessed through the SPI (Serial Peripheral Interface) bus compatible protocol.
The SPI bus consist of four control lines; Chip Enable (CE#) is used to select the device, and data is
accessed through the Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK).
The SST25WF080 support both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The difference
between the two modes, as shown in Figure 4, is the state of the SCK signal when the bus master is in
Stand-by mode and no data is being transferred. The SCK signal is low for Mode 0 and SCK signal is
high for Mode 3. For both modes, the Serial Data In (SI) is sampled at the rising edge of the SCK clock
signal and the Serial Data Output (SO) is driven after the falling edge of the SCK clock signal.
Figure 4: SPI Protocol
1203 F03.0
MODE 3
SCK
SI
SO
CE#
MODE 3
DON'T CARE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MODE 0
MODE 0
HIGH IMPEDANCE
MSB
MSB
©2012 Silicon Storage Technology, Inc.
DS25024C
10/12
7
8 Mbit 1.8V SPI Serial Flash
SST25WF080
Not Recommended for New Designs
Reset/Hold Mode
The RST#/HOLD# pin provides either a hardware reset or a hold pin. From power-on, the RST#/
HOLD# pin defaults as a hardware reset pin (RST#). The Hold mode for this pin is a user selected
option where an Enable-Hold instruction enables the Hold mode. Once selected as a hold pin
(HOLD#), the RST#/HOLD# pin will be configured as a HOLD# pin, and goes back to RST# pin only
after a power-off and power-on sequence.
Reset
If the RST#/HOLD# pin is used as a reset pin, RST# pin provides a hardware method for resetting the
device. Driving the RST# pin high puts the device in normal operating mode. The RST# pin must be
driven low for a minimum of T
RST
time to reset the device. The SO pin is in high impedance state while
the device is in reset. A successful reset will reset the status register to its power-up state. See Table 4
for default power-up modes. A device reset during an active Program or Erase operation aborts the
operation and data of the targeted address range may be corrupted or lost due to the aborted erase or
program operation. The device exits AAI Programming Mode in progress and places the SO pin in high
impedance state.
Figure 5: Reset Timing Diagram
Table 2: Reset Timing Parameters
Symbol
Parameter
Min
Max
Units
T
RST
1
1. For reset while in a Programming or Erase mode, the reset pulse must be >5µs
Reset Pulse Width
100
ns
T
RHZ
Reset to High-Z Output
107
ns
T
RECR
Reset Recovery from Read
100
ns
T
RECP
Reset Recovery from Program
10
µs
T
RECE
Reset Recovery from Erase
1
ms
T2.25024
1203 F04.0
CE#
SO
SI
SCK
RST#
T
RECR
T
RECP
T
RECE
T
RST
T
RHZ
©2012 Silicon Storage Technology, Inc.
DS25024C
10/12
8
8 Mbit 1.8V SPI Serial Flash
SST25WF080
Not Recommended for New Designs
Hold
The Hold operation enables the hold pin functionality of the RST#/HOLD# pin. Once set to hold pin
mode, the RST#/HOLD# pin continues functioning as a hold pin until the device is powered off and
then powered on. After a power-off and power-on, the pin functionality returns to a reset pin (RST#)
mode. See “Enable-Hold (EHLD)” on page 22 for detailed timing of the Hold instruction.
In the hold mode, serial sequences underway with the SPI Flash memory are paused without resetting
the clocking sequence. To activate the HOLD# mode, CE# must be in active low state. The HOLD#
mode begins when the SCK active low state coincides with the falling edge of the HOLD# signal. The
Hold mode ends when the rising edge of the HOLD# signal coincides with the SCK active low state. If
the falling edge of the HOLD# signal does not coincide with the SCK active low state, then the device
enters Hold mode when the SCK next reaches the active low state. Similarly, if the rising edge of the
HOLD# signal does not coincide with the SCK active low state, then the device exits Hold mode when
the SCK next reaches the active low state. See Figure 6 for Hold Condition waveform.
Once the device enters Hold mode, SO will be in high-impedance state while SI and SCK can be V
IL
or V
IH.
If CE# is driven active high during a Hold condition, the device returns to standby mode. The device
can then be re-initiated with the command sequences listed in Table 6. As long as HOLD# signal is
low, the memory remains in the Hold condition. To resume communication with the device, HOLD#
must be driven active high, and CE# must be driven active low. See Figure 6 for Hold timing.
Figure 6: Hold Condition Waveform
Write Protection
SST25WF080 provide software Write protection. The Write Protect pin (WP#) enables or disables the
lock-down function of the status register. The Block-Protection bits (BP3, BP2, BP1, BP0, and BPL) in
the status register provide Write protection to the memory array and the status register. See Table 5 for
the Block-Protection description.
Write Protect Pin (WP#)
The Write Protect (WP#) pin enables the lock-down function of the BPL bit (bit 7) in the status register.
When WP# is driven low, the execution of the Write-Status-Register (WRSR) instruction is determined by
the value of the BPL bit (see Table 3). When WP# is high, the lock-down function of the BPL bit is disabled.
Table 3: Conditions to execute Write-Status-Register (WRSR) Instruction
WP#
BPL
Execute WRSR Instruction
L
1
Not Allowed
L
0
Allowed
H
X
Allowed
T3.0 25024
Active
Hold
Active
Hold
Active
1203 F05.0
SCK
HOLD#
©2012 Silicon Storage Technology, Inc.
DS25024C
10/12
9
8 Mbit 1.8V SPI Serial Flash
SST25WF080
Not Recommended for New Designs
Status Register
The software status register provides status on whether the flash memory array is available for any
Read or Write operation, whether the device is Write enabled, and the state of the Memory Write pro-
tection. During an internal Erase or Program operation, the status register may be read only to deter-
mine the completion of an operation in progress. Table 4 describes the function of each bit in the
software status register.
Busy
The Busy bit determines whether there is an internal Erase or Program operation in progress. A ‘1’ for
the Busy bit indicates the device is busy with an operation in progress. A ‘0’ indicates the device is
ready for the next valid operation.
Write Enable Latch (WEL)
The Write-Enable-Latch bit indicates the status of the internal Write-Enable-Latch memory. If the WEL
bit is set to ‘1’, it indicates the device is Write enabled. If the bit is set to ‘0’ (reset), it indicates the
device is not Write enabled and does not accept any Write (Program/Erase) commands. The Write-
Enable-Latch bit is automatically reset under the following conditions:
•
Device Reset
•
Power-up
•
Write-Disable (WRDI) instruction completion
•
Byte-Program instruction completion
•
Auto Address Increment (AAI) programming is completed or reached its highest unpro-
tected memory address
•
Sector-Erase instruction completion
•
Block-Erase instruction completion
•
Chip-Erase instruction completion
•
Write-Status-Register instructions
Table 4: Software Status Register
Bit
Name
Function
Default at
Power-up
Read/Write
0
BUSY
1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
0
R
1
WEL
1 = Device is memory Write enabled
0 = Device is not memory Write enabled
0
R
2
BP0
Indicate current level of block write protection (See Table 5)
1
R/W
3
BP1
Indicate current level of block write protection (See Table 5)
1
R/W
4
BP2
Indicate current level of block write protection (See Table 5)
1
R/W
5
BP3
Indicate current level of block write protection (See Table 5)
0
R/W
6
AAI
Auto Address Increment Programming status
1 = AAI programming mode
0 = Byte-Program mode
0
R
7
BPL
1 = BP3, BP2, BP1 and BP0 are read-only bits
0 = BP3, BP2, BP1 and BP0 are read/writable
0
R/W
T4.1 25024
©2012 Silicon Storage Technology, Inc.
DS25024C
10/12
10
8 Mbit 1.8V SPI Serial Flash
SST25WF080
Not Recommended for New Designs
Auto Address Increment (AAI)
The Auto Address Increment Programming-Status bit provides status on whether the device is in AAI
programming mode or Byte-Program mode. The default at power up is Byte-Program mode.
Block-Protection (BP3, BP2, BP1, BP0)
The Block-Protection (BP3, BP2, BP1, BP0) bits define the size of the memory area to be software
protected against any memory Write (Program or Erase) operation, see Table 5. The Write-Status-
Register (WRSR) instruction is used to program the BP3, BP2, BP1 and BP0 bits as long as WP# is
high or the Block-Protect-Lock (BPL) bit is ‘0’. Chip-Erase can only be executed if Block-Protection bits
are all ‘0’. After power-up, BP3, BP2, BP1 and BP0 are set to defaults. See Table 4 for defaults at
power-up.
Block Protection Lock-Down (BPL)
When the WP# pin is driven low (V
IL
), it enables the Block-Protection-Lock-Down (BPL) bit. When BPL
is set to ‘1’, it prevents any further alteration of the BPL, BP3, BP2, BP1, and BP0 bits. When the WP#
pin is driven high (V
IH
), the BPL bit has no effect and its value is ‘Don’t Care’. After power-up, the BPL
bit is reset to ‘0’.
Table 5: Software Status Register Block Protection for SST25WF080
Protection Level
Status Register Bit
Protected Memory Address
BP3
1
1. X = Don’t Care (Reserved), default is ‘0’.
BP2
2
2. Default at power-up for BP2, BP1 and BP0 is ‘11’.
BP1
2
BP0
2
8 Mbit
None
X
0
0
0
None
1 (Upper 16th Memory, Blocks 30 and 31)
X
0
0
1
F0000H-FFFFFH
2 (Upper 8th Memory, Blocks 28 to 31)
X
0
1
0
E0000H-FFFFFH
3 (Upper Quarter Memory, Blocks 24 to 31)
X
0
1
1
C0000H-FFFFFH
4 (Upper Half Memory, Blocks 16 to 31)
X
1
0
0
80000H-FFFFFH
5 (Full Memory, Blocks 0 to 31)
X
1
0
1
00000H-FFFFFH
X
1
1
0
X
1
1
1
T5.1 25024