1996-2018 Microchip Technology Inc.
DS20001178J-page 1
24AA00/24LC00/24C00
Device Selection Table
Features
• Single Supply with Operation down to 1.8V for
24AA00 Devices, 2.5V for 24LC00 Devices
• Low-Power CMOS Technology:
- Read current 500
A, typical
- Standby current 100 nA, typical
• 2-Wire Serial Interface, I
2
C Compatible
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• Page Write Time 3 ms, Typical
• Self-Timed Erase/Write Cycle
• ESD Protection >4000V
• More than 1 Million Erase/Write Cycles
• Data Retention >200 Years
• Factory Programming Available
• Packages include 8-lead PDIP, SOIC, TSSOP,
DFN, TDFN and 5-lead SOT-23
• Pb-Free and RoHS Compliant
• Temperature Ranges Available:
- Industrial (I): -40
C to +85C
- Automotive (E): -40
C to +125C
Description
The Microchip Technology Inc. 24AA00/24LC00/
24C00 (24XX00*) is a 128-bit Electrically Erasable
PROM memory organized as 16 x 8 with a 2-wire
serial interface. Low-voltage design permits operation
down to 1.8 volts for the 24AA00 version, and every
version maintains a maximum standby current of only
1
A and typical active current of only 500 A. This
device was designed for where a small amount of
EEPROM is needed for the storage of calibration
values, ID numbers or manufacturing information, etc.
The 24XX00 is available in 8-pin PDIP, 8-pin SOIC
(3.90 mm), 8-pin TSSOP, 8-pin 2x3 DFN, TDFN and
the 5-pin SOT-23 packages.
Package Types
Block Diagram
Device
V
CC
Range
Temp Range
24AA00
1.8-5.5
I
24LC00
2.5-5.5
I
24C00
4.5-5.5
I,E
1
2
3
4
8
7
6
5
1
5
4
3
8-PIN PDIP/SOIC
8-PIN TSSOP
5-PIN SOT-23
NC
NC
NC
Vss
V
CC
NC
SCL
SDA
NC
NC
NC
V
SS
V
CC
NC
SCL
SDA
SCL
V
SS
SDA
V
CC
NC
1
2
3
4
8
7
6
5
2
DFN/TDFN
NC
NC
NC
V
SS
NC
SCL
SDA
V
CC
8
7
6
5
1
2
3
4
HV Generator
EEPROM
Array
YDEC
XDEC
Sense AMP
R/W Control
Memory
Control
Logic
I/O
Control
Logic
SDA
SCL
V
CC
V
SS
128-Bit I
2
C Bus Serial EEPROM
*24XX00 is used in this document as a generic part number for
the 24AA00/24LC00/24C00 devices.
24AA00/24LC00/24C00
DS20001178J-page 2
1996-2018 Microchip Technology Inc.
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
V
CC
.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. V
SS
......................................................................................................... -0.6V to V
CC
+1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ................................................................................................-40°C to +125°C
ESD protection on all pins ..........................................................................................................................................4 kV
FIGURE 1-1:
BUS TIMING DATA
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
All Parameters apply across the
recommended operating ranges unless
otherwise noted
Industrial (I):
T
A
= -40°C to +85°C,
V
CC
= 1.8V to 5.5V
Automotive (E)
T
A
= -40°C to +125°C, V
CC
= 4.5V to 5.5V
Parameter
Symbol
Min.
Max.
Units
Conditions
SCL and SDA pins:
High-level input voltage
V
IH
0.7 V
CC
—
V
(Note)
Low-level input voltage
V
IL
—
0.3 V
CC
V
(Note)
Hysteresis of Schmitt Trigger
inputs
V
HYS
.05 V
CC
—
V
V
CC
2.5V (Note)
Low-level output voltage
V
OL
—
0.4
V
I
OL
= 3.0 mA, V
CC
= 4.5V
I
OL
= 2.1 mA, V
CC
= 2.5V
Input leakage current
I
LI
—
±1
A
V
IN
= V
CC
or V
SS
Output leakage current
I
LO
—
±1
A
V
OUT
= V
CC
or V
SS
Pin capacitance (all inputs/outputs)
C
IN
,
C
OUT
—
10
pF
V
CC
= 5.0V (Note)
T
A
= 25°C, F
CLK
= 1 MHz
Operating current
I
CC
Write
—
2
mA
V
CC
= 5.5V, SCL = 400 kHz
I
CC
Read
—
1
mA
V
CC
= 5.5V, SCL = 400 kHz
Standby current
I
CCS
—
1
A
V
CC
= 5.5V, SDA = SCL = V
CC
Note:
This parameter is periodically sampled and not 100% tested.
T
F
T
HIGH
T
R
T
SU
:
STA
T
LOW
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
BUF
T
AA
T
SP
SCL
SDA
IN
SDA
OUT
T
HD
:
STA
1996-2018 Microchip Technology Inc.
DS20001178J-page 3
24AA00/24LC00/24C00
TABLE 1-2:
AC CHARACTERISTICS
All Parameters apply across all
recommended operating ranges
unless otherwise noted
Industrial (I):
T
A
= -40°C to +85°C, V
CC
= 1.8V to 5.5V
Automotive (E):
T
A
= -40°C to +125°C, V
CC
= 4.5V to 5.5V
Parameter
Symbol
Min
Max
Units
Conditions
Clock frequency
F
CLK
—
—
—
100
100
400
kHz
4.5V
Vcc 5.5V (E Temp range)
1.8V
Vcc 4.5V
4.5V
Vcc 5.5V
Clock high time
T
HIGH
4000
4000
600
—
—
—
ns
4.5V
Vcc 5.5V (E Temp range)
1.8V
Vcc 4.5V
4.5V
Vcc 5.5V
Clock low time
T
LOW
4700
4700
1300
—
—
—
ns
4.5V
Vcc 5.5V (E Temp range)
1.8V
Vcc 4.5V
4.5V
Vcc 5.5V
SDA and SCL rise time
(
Note 1
)
T
R
—
—
—
1000
1000
300
ns
4.5V
Vcc 5.5V (E Temp range)
1.8V
Vcc 4.5V
4.5V
Vcc 5.5V
SDA and SCL fall time
T
F
—
300
ns
(
Note 1
)
Start condition hold time
T
HD
:
STA
4000
4000
600
—
—
—
ns
4.5V
Vcc 5.5V (E Temp range)
1.8V
Vcc 4.5V
4.5V
Vcc 5.5V
Start condition setup time
T
SU
:
STA
4700
4700
600
—
—
—
ns
4.5V
Vcc 5.5V (E Temp range)
1.8V
Vcc 4.5V
4.5V
Vcc 5.5V
Data input hold time
T
HD
:
DAT
0
—
ns
(
Note 2
)
Data input setup time
T
SU
:
DAT
250
250
100
—
—
—
ns
4.5V
Vcc 5.5V (E Temp range)
1.8V
Vcc 4.5V
4.5V
Vcc 5.5V
Stop condition setup time
T
SU
:
STO
4000
4000
600
—
—
—
ns
4.5V
Vcc 5.5V (E Temp range)
1.8V
Vcc 4.5V
4.5V
Vcc 5.5V
Output valid from clock
(
Note 2
)
T
AA
—
—
—
3500
3500
900
ns
4.5V
Vcc 5.5V (E Temp range)
1.8V
Vcc 4.5V
4.5V
Vcc 5.5V
Bus free time: Time the bus must
be free before a new transmis-
sion can start
T
BUF
4700
4700
1300
—
—
—
ns
4.5V
Vcc 5.5V (E Temp range)
1.8V
Vcc 4.5V
4.5V
Vcc 5.5V
Output fall time from V
IH
minimum to V
IL
maximum
T
OF
20+0.1
CB
250
ns
(
Note 1
), CB
100 pF
Input filter spike suppression
(SDA and SCL pins)
T
SP
—
50
ns
(
Notes 1
,
3
)
Write cycle time
T
WC
—
4
ms
Endurance
1M
—
cycles (
Note 4
)
Note 1: Not 100% tested. C
B
= total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined T
SP
and V
HYS
specifications are due to new Schmitt Trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained at www.microchip.com.
24AA00/24LC00/24C00
DS20001178J-page 4
1996-2018 Microchip Technology Inc.
2.0
PIN DESCRIPTIONS
Pin Function Table
2.1
SDA Serial Data
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to V
CC
(typical 10 k
for 100 kHz, 2 k for
400 kHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.2
SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
2.3
Noise Protection
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation even on a noisy bus.
Name
PDIP
SOIC
TSSOP
DFN
(
1
)
TDFN
(
1
)
SOT-23
Description
NC
1, 2, 3, 7
1, 2, 3, 7
1, 2, 3, 7
1, 2, 3, 7
1, 2, 3, 7
4
Not Connected
V
SS
4
4
4
4
4
2
Ground
SDA
5
5
5
5
5
3
Serial Address/Data I/O
SCL
6
6
6
6
6
1
Serial Clock
V
CC
8
8
8
8
8
5
+1.8V to 5.5V Power Supply
Note 1: The exposed pad on the DFN/TDFN packages can be connected to V
SS
or left floating.
1996-2018 Microchip Technology Inc.
DS20001178J-page 5
24AA00/24LC00/24C00
3.0
FUNCTIONAL DESCRIPTION
The 24XX00 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, and a device
receiving data as a receiver. The bus has to be
controlled by a master device which generates the
Serial Clock (SCL), controls the bus access, and
generates the Start and Stop conditions, while the
24XX00 works as slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is activated.
4.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (
Figure 4-1
).
4.1
Bus Not Busy (A)
Both data and clock lines remain high.
4.2
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
4.4
Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is
theoretically unlimited.
24AA00/24LC00/24C00
DS20001178J-page 6
1996-2018 Microchip Technology Inc.
4.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
The device that acknowledges has to pull down the
SDA line during the Acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an Acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line high to enable
the master to generate the Stop condition (
Figure 4-2
).
FIGURE 4-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
FIGURE 4-2:
ACKNOWLEDGE TIMING
Note:
The 24XX00 does not generate any
Acknowledge bits if an internal program-
ming cycle is in progress.
(A)
(B)
(C)
(D)
(A)
(C)
SCL
SDA
Start
Condition
Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
SCL
9
8
7
6
5
4
3
2
1
1
2
3
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
Receiver must release the SDA line at this point
so the Transmitter can continue sending data.
Data from transmitter
Data from transmitter
SDA
Acknowledge
Bit
1996-2018 Microchip Technology Inc.
DS20001178J-page 7
24AA00/24LC00/24C00
5.0
DEVICE ADDRESSING
After generating a Start condition, the bus master
transmits a control byte consisting of a slave address
and a Read/Write bit that indicates what type of
operation is to be performed. The slave address for the
24XX00 consists of a 4-bit device code ‘1010’ followed
by three “don’t care” bits.
The last bit of the control byte determines the operation
to be performed. When set to a one a read operation is
selected, and when set to a zero a write operation is
selected (
Figure 5-1
). The 24XX00 monitors the bus for
its corresponding slave address all the time. It
generates an Acknowledge bit if the slave address was
true and it is not in a programming mode.
FIGURE 5-1:
CONTROL BYTE FORMAT
1
0
1
0
x
x
x
S
ACK
R/W
Device Select
Bits
Don’t Care
Bits
Slave Address
Acknowledge Bit
Start Bit
Read/Write Bit
24AA00/24LC00/24C00
DS20001178J-page 8
1996-2018 Microchip Technology Inc.
6.0
WRITE OPERATIONS
6.1
Byte Write
Following the Start signal from the master, the device
code (4 bits), the “don’t care” bits (3 bits), and the R/W
bit (which is a logic low) are placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will
follow after it has generated an Acknowledge bit during
the ninth clock cycle. Therefore, the next byte transmit-
ted by the master is the word address and will be
written into the Address Pointer of the 24XX00. Only
the lower four address bits are used by the device, and
the upper four bits are “don’t cares.” The 24XX00 will
acknowledge the address byte and the master device
will then transmit the data word to be written into the
addressed memory location. The 24XX00 acknowl-
edges again and the master generates a Stop
condition. This initiates the internal write cycle, and
during this time the 24XX00 will not generate Acknowl-
edge signals (
Figure 6-1
). After a byte Write command,
the internal address counter will not be incremented
and will point to the same address location that was just
written. If a Stop bit is transmitted to the device at any
point in the Write command sequence before the entire
sequence is complete, then the command will abort
and no data will be written. If more than 8 data bits are
transmitted before the Stop bit is sent, then the device
will clear the previously loaded byte and begin loading
the data buffer again. If more than one data byte is
transmitted to the device and a Stop bit is sent before a
full eight data bits have been transmitted, then the
Write command will abort and no data will be written.
The 24XX00 employs a V
CC
threshold detector circuit
which disables the internal erase/write logic if the V
CC
is below 1.5V (24AA00 and 24LC00) or 3.8V (24C00)
at nominal conditions.
FIGURE 6-1:
BYTE WRITE
S
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
S
T
O
P
Control
Byte
Word
Address
Data
A
C
K
A
C
K
A
C
K
1 0
x
1 0
x
x
x
x = “don’t care” bit
x x x
0
1996-2018 Microchip Technology Inc.
DS20001178J-page 9
24AA00/24LC00/24C00
7.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition followed by the control byte
for a Write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If no ACK is returned, then the Start bit and control byte
must be re-sent. If the cycle is complete, then the
device will return the ACK and the master can then
proceed with the next Read or Write command. See
Figure 7-1
for flow diagram.
FIGURE 7-1:
ACKNOWLEDGE
POLLING FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
Next
Operation
No
Yes
24AA00/24LC00/24C00
DS20001178J-page 10
1996-2018 Microchip Technology Inc.
8.0
READ OPERATIONS
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read
and sequential read.
8.1
Current Address Read
The 24XX00 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous read
access was to address n, the next current address read
operation would access data from address n + 1. Upon
receipt of the slave address with the R/W bit set to one,
the device issues an acknowledge and transmits the
eight-bit data word. The master will not acknowledge
the transfer, but does generate a Stop condition and the
device discontinues transmission (
Figure 8-1
).
8.2
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
device as part of a write operation.
After the word address is sent, the master generates a
Start condition following the acknowledge. This termi-
nates the write operation, but not before the internal
Address Pointer is set. Then the master issues the
control byte again, but with the R/W bit set to a one.
The 24XX00 will then issue an acknowledge and trans-
mits the eight bit data word. The master will not
acknowledge the transfer, but does generate a Stop
condition and the device discontinues transmission
(
Figure 8-2
). After this command, the internal address
counter will point to the address location following the
one that was just read.
8.3
Sequential Read
Sequential reads are initiated in the same way as a
random read except that after the device transmits the
first data byte, the master issues an acknowledge as
opposed to a Stop condition in a random read. This
directs the device to transmit the next sequentially
addressed 8-bit word (
Figure 8-3
).
To provide sequential reads the 24XX00 contains an
internal Address Pointer which is incremented by one
at the completion of each read operation. This Address
Pointer allows the entire memory contents to be serially
read during one operation.
FIGURE 8-1:
CURRENT ADDRESS READ
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
P
S
S
T
O
P
Control
Byte
S
T
A
R
T
Data
A
C
K
N
O
A
C
K
1
1
0
0 x x x 1
x = “don’t care” bit
1996-2018 Microchip Technology Inc.
DS20001178J-page 1
24AA00/24LC00/24C00
Device Selection Table
Features
• Single Supply with Operation down to 1.8V for
24AA00 Devices, 2.5V for 24LC00 Devices
• Low-Power CMOS Technology:
- Read current 500
A, typical
- Standby current 100 nA, typical
• 2-Wire Serial Interface, I
2
C Compatible
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• Page Write Time 3 ms, Typical
• Self-Timed Erase/Write Cycle
• ESD Protection >4000V
• More than 1 Million Erase/Write Cycles
• Data Retention >200 Years
• Factory Programming Available
• Packages include 8-lead PDIP, SOIC, TSSOP,
DFN, TDFN and 5-lead SOT-23
• Pb-Free and RoHS Compliant
• Temperature Ranges Available:
- Industrial (I): -40
C to +85C
- Automotive (E): -40
C to +125C
Description
The Microchip Technology Inc. 24AA00/24LC00/
24C00 (24XX00*) is a 128-bit Electrically Erasable
PROM memory organized as 16 x 8 with a 2-wire
serial interface. Low-voltage design permits operation
down to 1.8 volts for the 24AA00 version, and every
version maintains a maximum standby current of only
1
A and typical active current of only 500 A. This
device was designed for where a small amount of
EEPROM is needed for the storage of calibration
values, ID numbers or manufacturing information, etc.
The 24XX00 is available in 8-pin PDIP, 8-pin SOIC
(3.90 mm), 8-pin TSSOP, 8-pin 2x3 DFN, TDFN and
the 5-pin SOT-23 packages.
Package Types
Block Diagram
Device
V
CC
Range
Temp Range
24AA00
1.8-5.5
I
24LC00
2.5-5.5
I
24C00
4.5-5.5
I,E
1
2
3
4
8
7
6
5
1
5
4
3
8-PIN PDIP/SOIC
8-PIN TSSOP
5-PIN SOT-23
NC
NC
NC
Vss
V
CC
NC
SCL
SDA
NC
NC
NC
V
SS
V
CC
NC
SCL
SDA
SCL
V
SS
SDA
V
CC
NC
1
2
3
4
8
7
6
5
2
DFN/TDFN
NC
NC
NC
V
SS
NC
SCL
SDA
V
CC
8
7
6
5
1
2
3
4
HV Generator
EEPROM
Array
YDEC
XDEC
Sense AMP
R/W Control
Memory
Control
Logic
I/O
Control
Logic
SDA
SCL
V
CC
V
SS
128-Bit I
2
C Bus Serial EEPROM
*24XX00 is used in this document as a generic part number for
the 24AA00/24LC00/24C00 devices.
24AA00/24LC00/24C00
DS20001178J-page 2
1996-2018 Microchip Technology Inc.
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
V
CC
.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. V
SS
......................................................................................................... -0.6V to V
CC
+1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ................................................................................................-40°C to +125°C
ESD protection on all pins ..........................................................................................................................................4 kV
FIGURE 1-1:
BUS TIMING DATA
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
All Parameters apply across the
recommended operating ranges unless
otherwise noted
Industrial (I):
T
A
= -40°C to +85°C,
V
CC
= 1.8V to 5.5V
Automotive (E)
T
A
= -40°C to +125°C, V
CC
= 4.5V to 5.5V
Parameter
Symbol
Min.
Max.
Units
Conditions
SCL and SDA pins:
High-level input voltage
V
IH
0.7 V
CC
—
V
(Note)
Low-level input voltage
V
IL
—
0.3 V
CC
V
(Note)
Hysteresis of Schmitt Trigger
inputs
V
HYS
.05 V
CC
—
V
V
CC
2.5V (Note)
Low-level output voltage
V
OL
—
0.4
V
I
OL
= 3.0 mA, V
CC
= 4.5V
I
OL
= 2.1 mA, V
CC
= 2.5V
Input leakage current
I
LI
—
±1
A
V
IN
= V
CC
or V
SS
Output leakage current
I
LO
—
±1
A
V
OUT
= V
CC
or V
SS
Pin capacitance (all inputs/outputs)
C
IN
,
C
OUT
—
10
pF
V
CC
= 5.0V (Note)
T
A
= 25°C, F
CLK
= 1 MHz
Operating current
I
CC
Write
—
2
mA
V
CC
= 5.5V, SCL = 400 kHz
I
CC
Read
—
1
mA
V
CC
= 5.5V, SCL = 400 kHz
Standby current
I
CCS
—
1
A
V
CC
= 5.5V, SDA = SCL = V
CC
Note:
This parameter is periodically sampled and not 100% tested.
T
F
T
HIGH
T
R
T
SU
:
STA
T
LOW
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
BUF
T
AA
T
SP
SCL
SDA
IN
SDA
OUT
T
HD
:
STA
1996-2018 Microchip Technology Inc.
DS20001178J-page 3
24AA00/24LC00/24C00
TABLE 1-2:
AC CHARACTERISTICS
All Parameters apply across all
recommended operating ranges
unless otherwise noted
Industrial (I):
T
A
= -40°C to +85°C, V
CC
= 1.8V to 5.5V
Automotive (E):
T
A
= -40°C to +125°C, V
CC
= 4.5V to 5.5V
Parameter
Symbol
Min
Max
Units
Conditions
Clock frequency
F
CLK
—
—
—
100
100
400
kHz
4.5V
Vcc 5.5V (E Temp range)
1.8V
Vcc 4.5V
4.5V
Vcc 5.5V
Clock high time
T
HIGH
4000
4000
600
—
—
—
ns
4.5V
Vcc 5.5V (E Temp range)
1.8V
Vcc 4.5V
4.5V
Vcc 5.5V
Clock low time
T
LOW
4700
4700
1300
—
—
—
ns
4.5V
Vcc 5.5V (E Temp range)
1.8V
Vcc 4.5V
4.5V
Vcc 5.5V
SDA and SCL rise time
(
Note 1
)
T
R
—
—
—
1000
1000
300
ns
4.5V
Vcc 5.5V (E Temp range)
1.8V
Vcc 4.5V
4.5V
Vcc 5.5V
SDA and SCL fall time
T
F
—
300
ns
(
Note 1
)
Start condition hold time
T
HD
:
STA
4000
4000
600
—
—
—
ns
4.5V
Vcc 5.5V (E Temp range)
1.8V
Vcc 4.5V
4.5V
Vcc 5.5V
Start condition setup time
T
SU
:
STA
4700
4700
600
—
—
—
ns
4.5V
Vcc 5.5V (E Temp range)
1.8V
Vcc 4.5V
4.5V
Vcc 5.5V
Data input hold time
T
HD
:
DAT
0
—
ns
(
Note 2
)
Data input setup time
T
SU
:
DAT
250
250
100
—
—
—
ns
4.5V
Vcc 5.5V (E Temp range)
1.8V
Vcc 4.5V
4.5V
Vcc 5.5V
Stop condition setup time
T
SU
:
STO
4000
4000
600
—
—
—
ns
4.5V
Vcc 5.5V (E Temp range)
1.8V
Vcc 4.5V
4.5V
Vcc 5.5V
Output valid from clock
(
Note 2
)
T
AA
—
—
—
3500
3500
900
ns
4.5V
Vcc 5.5V (E Temp range)
1.8V
Vcc 4.5V
4.5V
Vcc 5.5V
Bus free time: Time the bus must
be free before a new transmis-
sion can start
T
BUF
4700
4700
1300
—
—
—
ns
4.5V
Vcc 5.5V (E Temp range)
1.8V
Vcc 4.5V
4.5V
Vcc 5.5V
Output fall time from V
IH
minimum to V
IL
maximum
T
OF
20+0.1
CB
250
ns
(
Note 1
), CB
100 pF
Input filter spike suppression
(SDA and SCL pins)
T
SP
—
50
ns
(
Notes 1
,
3
)
Write cycle time
T
WC
—
4
ms
Endurance
1M
—
cycles (
Note 4
)
Note 1: Not 100% tested. C
B
= total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined T
SP
and V
HYS
specifications are due to new Schmitt Trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained at www.microchip.com.
24AA00/24LC00/24C00
DS20001178J-page 4
1996-2018 Microchip Technology Inc.
2.0
PIN DESCRIPTIONS
Pin Function Table
2.1
SDA Serial Data
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to V
CC
(typical 10 k
for 100 kHz, 2 k for
400 kHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.2
SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
2.3
Noise Protection
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation even on a noisy bus.
Name
PDIP
SOIC
TSSOP
DFN
(
1
)
TDFN
(
1
)
SOT-23
Description
NC
1, 2, 3, 7
1, 2, 3, 7
1, 2, 3, 7
1, 2, 3, 7
1, 2, 3, 7
4
Not Connected
V
SS
4
4
4
4
4
2
Ground
SDA
5
5
5
5
5
3
Serial Address/Data I/O
SCL
6
6
6
6
6
1
Serial Clock
V
CC
8
8
8
8
8
5
+1.8V to 5.5V Power Supply
Note 1: The exposed pad on the DFN/TDFN packages can be connected to V
SS
or left floating.
1996-2018 Microchip Technology Inc.
DS20001178J-page 5
24AA00/24LC00/24C00
3.0
FUNCTIONAL DESCRIPTION
The 24XX00 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, and a device
receiving data as a receiver. The bus has to be
controlled by a master device which generates the
Serial Clock (SCL), controls the bus access, and
generates the Start and Stop conditions, while the
24XX00 works as slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is activated.
4.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (
Figure 4-1
).
4.1
Bus Not Busy (A)
Both data and clock lines remain high.
4.2
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
4.4
Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is
theoretically unlimited.
24AA00/24LC00/24C00
DS20001178J-page 6
1996-2018 Microchip Technology Inc.
4.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
The device that acknowledges has to pull down the
SDA line during the Acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an Acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line high to enable
the master to generate the Stop condition (
Figure 4-2
).
FIGURE 4-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
FIGURE 4-2:
ACKNOWLEDGE TIMING
Note:
The 24XX00 does not generate any
Acknowledge bits if an internal program-
ming cycle is in progress.
(A)
(B)
(C)
(D)
(A)
(C)
SCL
SDA
Start
Condition
Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
SCL
9
8
7
6
5
4
3
2
1
1
2
3
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
Receiver must release the SDA line at this point
so the Transmitter can continue sending data.
Data from transmitter
Data from transmitter
SDA
Acknowledge
Bit
1996-2018 Microchip Technology Inc.
DS20001178J-page 7
24AA00/24LC00/24C00
5.0
DEVICE ADDRESSING
After generating a Start condition, the bus master
transmits a control byte consisting of a slave address
and a Read/Write bit that indicates what type of
operation is to be performed. The slave address for the
24XX00 consists of a 4-bit device code ‘1010’ followed
by three “don’t care” bits.
The last bit of the control byte determines the operation
to be performed. When set to a one a read operation is
selected, and when set to a zero a write operation is
selected (
Figure 5-1
). The 24XX00 monitors the bus for
its corresponding slave address all the time. It
generates an Acknowledge bit if the slave address was
true and it is not in a programming mode.
FIGURE 5-1:
CONTROL BYTE FORMAT
1
0
1
0
x
x
x
S
ACK
R/W
Device Select
Bits
Don’t Care
Bits
Slave Address
Acknowledge Bit
Start Bit
Read/Write Bit
24AA00/24LC00/24C00
DS20001178J-page 8
1996-2018 Microchip Technology Inc.
6.0
WRITE OPERATIONS
6.1
Byte Write
Following the Start signal from the master, the device
code (4 bits), the “don’t care” bits (3 bits), and the R/W
bit (which is a logic low) are placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will
follow after it has generated an Acknowledge bit during
the ninth clock cycle. Therefore, the next byte transmit-
ted by the master is the word address and will be
written into the Address Pointer of the 24XX00. Only
the lower four address bits are used by the device, and
the upper four bits are “don’t cares.” The 24XX00 will
acknowledge the address byte and the master device
will then transmit the data word to be written into the
addressed memory location. The 24XX00 acknowl-
edges again and the master generates a Stop
condition. This initiates the internal write cycle, and
during this time the 24XX00 will not generate Acknowl-
edge signals (
Figure 6-1
). After a byte Write command,
the internal address counter will not be incremented
and will point to the same address location that was just
written. If a Stop bit is transmitted to the device at any
point in the Write command sequence before the entire
sequence is complete, then the command will abort
and no data will be written. If more than 8 data bits are
transmitted before the Stop bit is sent, then the device
will clear the previously loaded byte and begin loading
the data buffer again. If more than one data byte is
transmitted to the device and a Stop bit is sent before a
full eight data bits have been transmitted, then the
Write command will abort and no data will be written.
The 24XX00 employs a V
CC
threshold detector circuit
which disables the internal erase/write logic if the V
CC
is below 1.5V (24AA00 and 24LC00) or 3.8V (24C00)
at nominal conditions.
FIGURE 6-1:
BYTE WRITE
S
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
S
T
O
P
Control
Byte
Word
Address
Data
A
C
K
A
C
K
A
C
K
1 0
x
1 0
x
x
x
x = “don’t care” bit
x x x
0
1996-2018 Microchip Technology Inc.
DS20001178J-page 9
24AA00/24LC00/24C00
7.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition followed by the control byte
for a Write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If no ACK is returned, then the Start bit and control byte
must be re-sent. If the cycle is complete, then the
device will return the ACK and the master can then
proceed with the next Read or Write command. See
Figure 7-1
for flow diagram.
FIGURE 7-1:
ACKNOWLEDGE
POLLING FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
Next
Operation
No
Yes
24AA00/24LC00/24C00
DS20001178J-page 10
1996-2018 Microchip Technology Inc.
8.0
READ OPERATIONS
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read
and sequential read.
8.1
Current Address Read
The 24XX00 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous read
access was to address n, the next current address read
operation would access data from address n + 1. Upon
receipt of the slave address with the R/W bit set to one,
the device issues an acknowledge and transmits the
eight-bit data word. The master will not acknowledge
the transfer, but does generate a Stop condition and the
device discontinues transmission (
Figure 8-1
).
8.2
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
device as part of a write operation.
After the word address is sent, the master generates a
Start condition following the acknowledge. This termi-
nates the write operation, but not before the internal
Address Pointer is set. Then the master issues the
control byte again, but with the R/W bit set to a one.
The 24XX00 will then issue an acknowledge and trans-
mits the eight bit data word. The master will not
acknowledge the transfer, but does generate a Stop
condition and the device discontinues transmission
(
Figure 8-2
). After this command, the internal address
counter will point to the address location following the
one that was just read.
8.3
Sequential Read
Sequential reads are initiated in the same way as a
random read except that after the device transmits the
first data byte, the master issues an acknowledge as
opposed to a Stop condition in a random read. This
directs the device to transmit the next sequentially
addressed 8-bit word (
Figure 8-3
).
To provide sequential reads the 24XX00 contains an
internal Address Pointer which is incremented by one
at the completion of each read operation. This Address
Pointer allows the entire memory contents to be serially
read during one operation.
FIGURE 8-1:
CURRENT ADDRESS READ
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
P
S
S
T
O
P
Control
Byte
S
T
A
R
T
Data
A
C
K
N
O
A
C
K
1
1
0
0 x x x 1
x = “don’t care” bit