24AA64F/24LC64F/24FC64F Data Sheet

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 2009-2012 Microchip Technology Inc.

DS22154B-page 1

24AA64F/24LC64F/24FC64F

Device Selection Table

Features:

• Single-Supply with Operation down to 1.7V for 

24AA64F/24FC64F Devices, 2.5V for 24LC64F 
Devices

• Low-Power CMOS Technology:

- Read current 400

A, max.

- Standby current 1

A, max. (I-temp)

• 2-Wire Serial Interface, I

2

C™ Compatible

• Packages with Three Address Pins are 

Cascadable up to Eight Devices

• Schmitt Trigger Inputs for Noise Suppression

• Output Slope Control to Eliminate Ground Bounce

• 100 kHz and 400 kHz Clock Compatibility

• 1 MHz Clock for FC Versions

• Page Write Time 5 ms, typical

• Self-timed Erase/Write Cycle

• 32-Byte Page Write Buffer

• Hardware Write-Protect for 1/4 Array 

(1800h-1FFFh)

• ESD Protection > 4,000V

• More than One Million Erase/Write Cycles

• Data Retention > 200 Years

• Factory Programming Available

• Packages include 8-Lead PDIP, SOIC, TSSOP, 

MSOP, TDFN, 5-Lead SOT-23

• Pb-Free and RoHS Compliant

• Temperature Ranges:

- Industrial (I): -40°C to +85°C

- Automotive (E): -40°C to +125°C

Description:

The Microchip Technology Inc. 24AA64F/24LC64F/
24FC64F (24XX64F*) is a 64 Kbit Electrically Erasable 
PROM. The device is organized as a single block of 
8K x 8-bit memory with a 2-wire serial interface. Low-
voltage design permits operation down to 1.7V, with 
standby and read currents of only 1

A and 400 A, 

respectively. It has been developed for advanced, low-
power applications such as personal communications 
or data acquisition. The 24XX64F also has a page 
write capability for up to 32 bytes of data. Functional 
address lines allow up to eight devices on the same 
bus, for up to 512 Kbits address space. The 24XX64F 
is available in the standard 8-pin PDIP, surface mount 
SOIC, TSSOP, TDFN and MSOP packages. The 
24XX64F is also available in the 5-lead SOT-23 
package.

Block Diagram

Package Types

Part 

Number

V

CC

 

Range

Max. Clock 

Frequency

Temp. 

Ranges

24AA64F

1.7-5.5

400 kHz

(1)

I

24LC64F

2.5-5.5

400 kHz

I, E

24FC64F

1.7-5.5

1 MHz

(2)

I

Note 1:

100 kHz for V

CC

 <2.5V.

2:

400 kHz for V

CC

 <2.5V.

HV

 

EEPROM

 

Array

Page

 

YDEC

XDEC

Sense Amp.

Memory

Control

Logic

I/O

Control

Logic

I/O

WP

SDA

SCL

V

CC

V

SS

R/W Control

Latches

Generator

A2

A1

A0

A0

A1

A2

V

SS

V

CC

WP

SCL

SDA

1

2

3

4

8

7

6

5

PDIP/MSOP/SOIC/TSSOP

TDFN

A0

A1

A2

V

SS

WP

SCL

SDA

V

CC

8

7

6

5

1

2

3

4

SOT-23

1

2

3

4

5

WP

V

CC

SCL

V

SS

SDA

64K I

2

C™ Serial EEPROM with Quarter-Array Write-Protect

*24XX64F is used in this document as a generic part number for the 24AA64F/24LC64F/24FC64F devices.

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24AA64F/24LC64F/24FC64F

DS22154B-page 2

 2009-2012 Microchip Technology Inc.

1.0

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings 

(†)

V

CC

.............................................................................................................................................................................6.5V

All inputs and outputs w.r.t. V

SS

......................................................................................................... -0.3V to V

CC

 +1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied ................................................................................................-40°C to +125°C

ESD protection on all pins

  4 kV

TABLE 1-1:

DC CHARACTERISTICS

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.

DC CHARACTERISTICS

Industrial (I): 

T

A

 = -40°C to +85°C, V

CC

 = +1.7V to +5.5V

Automotive (E):  T

A

 = -40°C to +125°C, V

CC

 = +2.5V to +5.5V

Param.

No.

Sym.

Characteristic

Min.

Typ.

Max.

Units

Conditions

A0, A1, A2, WP, SCL 
and SDA pins

D1

V

IH

High-level input voltage

0.7 V

CC

V

D2

V

IL

Low-level input voltage

0.3 V

CC

0.2 V

CC

V
V

V

CC

 

 2.5V

V

CC

 

 2.5V

D3

V

HYS

Hysteresis of Schmitt
Trigger inputs (SDA, 
SCL pins)

0.05 V

CC

V

V

CC

 

 2.5V (

Note

 1)

D4

V

OL

Low-level output voltage

0.40

V

I

OL

 = 3.0 mA @ V

CC

 = 4.5V

I

OL

 = 2.1 mA @ V

CC

 = 2.5V

D5

I

LI

Input leakage current

±1

A

V

IN

 = V

SS

 or V

CC

D6

I

LO

Output leakage current

±1

A

V

OUT

 = V

SS

 or V

CC

D7

C

IN

C

OUT

Pin capacitance
(all inputs/outputs)

10

pF

V

CC

 = 5.0V (

Note

 1)

T

A

 = 25°C, F

CLK

 = 1 MHz

D8

I

CC

 write

Operating current

0.1

3

mA

V

CC

 = 5.5V, SCL = 400 kHz

D9

I

CC

 read

0.05

400

A

D10

I

CCS

Standby current


.01

1
5

A
A

Industrial
Automotive
SDA = SCL = V

CC

A0, A1, A2, WP = V

SS

Note 1:

This parameter is periodically sampled and not 100% tested.

2:

Typical measurements taken at room temperature.

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 2009-2012 Microchip Technology Inc.

DS22154B-page 3

24AA64F/24LC64F/24FC64F

TABLE 1-2:

AC CHARACTERISTICS

AC CHARACTERISTICS

Electrical Characteristics:
Industrial (I):

V

CC

 = +1.7V to 5.5V

T

A

 = -40°C to +85°C

Automotive (E):

V

CC

 = +2.5V to 5.5V

T

A

 = -40°C to 125°C

Param.

No.

Sym.

Characteristic

Min.

Max.

Units

Conditions

1

F

CLK

Clock frequency




100
400
400

1000

kHz

1.7V 

 V

CC

 

 2.5V 

2.5V 

 V

CC

 

 5.5V

1.7V 

 V

CC

 

 2.5V 24FC64F

2.5V 

 V

CC

 

 5.5V 24FC64F

2

T

HIGH

Clock high time

4000

600
600
500




ns

1.7V 

 V

CC

 

 2.5V 

2.5V 

 V

CC

 

 5.5V

1.7V 

 V

CC

 

 2.5V 24FC64F

2.5V 

 V

CC

 

 5.5V 24FC64F

3

T

LOW

Clock low time

4700
1300
1300

500




ns

1.7V 

 V

CC

 

 2.5V 

2.5V 

 V

CC

 

 5.5V

1.7V 

 V

CC

 

 2.5V 24FC64F

2.5V 

 V

CC

 

 5.5V 24FC64F

4

T

R

SDA and SCL rise time
(

Note 1

)



1000

300
300

ns

1.7V 

 V

CC

 

 2.5V 

2.5V 

 V

CC

 

 5.5V

1.7V 

 V

CC

 

 5.5V 24FC64F

5

T

F

SDA and SCL fall time
(

Note 1

)


300
100

ns

All except, 24FC64F
1.7V 

 V

CC

 

 5.5V 24FC64F

6

T

HD

:

STA

Start condition hold time

4000

600
600
250




ns

1.7V 

 V

CC

 

 2.5V 

2.5V 

 V

CC

 

 5.5V

1.7V 

 V

CC

 

 2.5V 24FC64F

2.5V 

 V

CC

 

 5.5V 24FC64F

7

T

SU

:

STA

Start condition setup time

4700

600
600
250




ns

1.7V 

 V

CC

 

 2.5V 

2.5V 

 V

CC

 

 5.5V

1.7V 

 V

CC

 

 2.5V 24FC64F

2.5V 

 V

CC

 

 5.5V 24FC64F

8

T

HD

:

DAT

Data input hold time

0

ns

(

Note 2

)

9

T

SU

:

DAT

Data input setup time

250
100
100



ns

1.7V 

 V

CC

 

 2.5V 

2.5V 

 V

CC

 

 5.5V

1.7V 

 V

CC

 

 5.5V 24FC64F

10

T

SU

:

STO

Stop condition setup time

4000

600
600
250




ns

1.7 V 

 V

CC

 

 2.5V 

2.5 V 

 V

CC

 

 5.5V

1.7V 

 V

CC

 

 2.5V 24FC64F

2.5 V 

 V

CC

 

 5.5V 24FC64F

11

T

SU

:

WP

WP setup time

4000

600
600



ns

1.7V 

 V

CC

 

 2.5V 

2.5V 

 V

CC

 

 5.5V

1.7V 

 V

CC

 

 5.5V 24FC64F

12

T

HD

:

WP

WP hold time

4700
1300
1300



ns

1.7V 

 V

CC

 

 2.5V 

2.5V 

 V

CC

 

 5.5V

1.7V 

 V

CC

 

 5.5V 24FC64F

Note 1: Not 100% tested. C

B

 = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

3: The combined T

SP

 and V

HYS

 specifications are due to new Schmitt Trigger inputs, which provide improved

noise spike suppression. This eliminates the need for a T

I

 specification for standard operation.

4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site
at www.microchip.com.

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24AA64F/24LC64F/24FC64F

DS22154B-page 4

 2009-2012 Microchip Technology Inc.

FIGURE 1-3:

BUS TIMING DATA 

13

T

AA

Output valid from clock
(

Note 2

)




3500

900
900
400

ns

1.7V 

 V

CC

 

 2.5V 

2.5V 

 V

CC

 

 5.5V

1.7V 

 V

CC

 

 2.5V 24FC64F

2.5V 

 V

CC

 

 5.5V 24FC64F

14

T

BUF

Bus free time: Time the bus 
must be free before a new 
transmission can start

4700
1300
1300

500




ns

1.7V 

 V

CC

 

 2.5V 

2.5V 

 V

CC

 

 5.5V

1.7V 

 V

CC

 

 2.5V 24FC64F

2.5V 

 V

CC

 

 5.5V 24FC64F

15

T

OF

Output fall time from V

IH

minimum to V

IL

 maximum

C

B

 

 100 pF

10 + 0.1C

B

250
250

ns

All except, 24FC64F (

Note 1

)

24FC64F (

Note 1

)

16

T

SP

Input filter spike suppression
(SDA and SCL pins)

50

ns

All except, 24FC64F (

Notes 1

 

and

3

)

17

T

WC

Write cycle time (byte or 
page)

5

ms

18

Endurance

1,000,000

cycles

Page Mode 25°C, 5.5V (

Note 4

)

TABLE 1-2:

AC CHARACTERISTICS (CONTINUED)

AC CHARACTERISTICS

Electrical Characteristics:
Industrial (I):

V

CC

 = +1.7V to 5.5V

T

A

 = -40°C to +85°C

Automotive (E):

V

CC

 = +2.5V to 5.5V

T

A

 = -40°C to 125°C

Param.

No.

Sym.

Characteristic

Min.

Max.

Units

Conditions

Note 1: Not 100% tested. C

B

 = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

3: The combined T

SP

 and V

HYS

 specifications are due to new Schmitt Trigger inputs, which provide improved

noise spike suppression. This eliminates the need for a T

I

 specification for standard operation.

4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site
at www.microchip.com.

(unprotected)

(protected)

SCL

SDA
IN

SDA
OUT

WP

5

7

6

16

3

2

8

9

13

D3

4

10

11

12

14

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 2009-2012 Microchip Technology Inc.

DS22154B-page 5

24AA64F/24LC64F/24FC64F

2.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in 

Table 2-1

.

TABLE 2-1:

PIN FUNCTION TABLE

2.1

A0, A1, A2 Chip Address Inputs

The A0, A1 and A2 inputs are used by the 24XX64F for
multiple device operation. The levels on these inputs
are compared with the corresponding bits in the slave
address. The chip is selected if the compare is true.

Up to eight devices may be connected to the same bus
by using different Chip Select bit combinations. These
inputs must be connected to either V

CC

 or V

SS

In most applications, the chip address inputs A0, A1
and A2 are hard-wired to logic ‘0’ or logic ‘1’. For
applications in which these pins are controlled by a
microcontroller or other programmable device, the chip
address pins must be driven to logic ‘0’ or logic ‘1’
before normal device operation can proceed. Address
pins are not available in the SOT-23 package.

2.2

Serial Data (SDA)

SDA is a bidirectional pin used to transfer addresses
and data into and out of the device. Since it is an open-
drain terminal, the SDA bus requires a pull-up resistor
to V

CC

 (typical 10 k

 for 100 kHz, 2 kfor 400 kHz).

For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.

2.3

Serial Clock (SCL)

The SCL input is used to synchronize the data transfer
from and to the device.

2.4

Write-Protect (WP)

This pin must be connected to either V

SS

 or V

CC

. If tied

to V

SS

, write operations are enabled. If tied to V

CC

,

write operations are inhibited for upper 1/4 of the array
(1800h-1FFFh), but read operations are not affected.

3.0

FUNCTIONAL DESCRIPTION

The 24XX64F supports a bidirectional, 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, while a device
receiving data is defined as a receiver. The bus has to
be controlled by a master device which generates the
Serial Clock (SCL), controls the bus access and
generates the Start and Stop conditions, while the
24XX64F works as slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is activated.

Name

PDIP

SOIC

TSSOP

TDFN

MSOP

SOT-23

Description

A0

1

1

1

1

1

Chip Address Input

A1

2

2

2

2

2

Chip Address Input

A2

3

3

3

3

3

Chip Address Input

V

SS

4

4

4

4

4

2

Ground

SDA

5

5

5

5

5

3

Serial Address/Data I/O

SCL

6

6

6

6

6

1

Serial Clock

WP

7

7

7

7

7

5

Write-Protect Input

V

CC

8

8

8

8

8

4

+1.7V to 5.5V Power Supply

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24AA64F/24LC64F/24FC64F

DS22154B-page 6

 2009-2012 Microchip Technology Inc.

4.0

BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus 

is not busy

• During data transfer, the data line must remain 

stable whenever the clock line is high. Changes in 
the data line while the clock line is high will be 
interpreted as a Start or Stop condition

Accordingly, the following bus conditions have been
defined (

Figure 4-1

).

4.1

Bus Not Busy (A)

Both data and clock lines remain high.

4.2

Start Data Transfer (B)

A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.

4.3

Stop Data Transfer (C)

A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.

4.4

Data Valid (D)

The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.

The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.

Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of data
bytes transferred between Start and Stop conditions is
determined by the master device and is, theoretically,
unlimited (although only the last thirty two will be stored
when doing a write operation). When an overwrite does
occur, it will replace data in a first-in first-out (FIFO)
fashion.

4.5

Acknowledge

Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.

The device that acknowledges has to pull down the
SDA line during the Acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the slave by not generating an Acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (24XX64F) will leave the data
line high to enable the master to generate the Stop
condition.

FIGURE 4-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

Note:

The 24XX64F does not generate any
Acknowledge bits if an internal
programming cycle is in progress.

SCL

SDA

(A)

(B)

(D)

(D)

(A)

(C)

Start

Condition

Address or

Acknowledge

Valid

Data

Allowed

to Change

Stop

Condition

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DS22154B-page 7

24AA64F/24LC64F/24FC64F

5.0

DEVICE ADDRESSING 

A control byte is the first byte received following the
Start condition from the master device (

Figure 5-1

).

The control byte consists of a four-bit control code. For
the 24XX64F, this is set as ‘1010’ binary for read and
write operations. The next three bits of the control byte
are the Chip Select bits (A2, A1, A0). The Chip Select
bits allow the use of up to eight 24XX64F devices on
the same bus and are used to select which device is
accessed. The Chip Select bits in the control byte must
correspond to the logic levels on the corresponding A2,
A1 and A0 pins for the device to respond. These bits
are, in effect, the three Most Significant bits of the word
address. 

For the SOT-23 package, the address pins are not
available. During device addressing, the A2, A1 and A0
Chip Select bits (

Figure 5-2

) should be set to ‘0’.

The last bit of the control byte defines the operation to
be performed. When set to a ‘1’, a read operation is
selected. When set to a ‘0’, a write operation is
selected. The next two bytes received define the
address of the first data byte (

Figure 5-2

). Because

only A12...A0 are used, the upper-three address bits
are “don’t care” bits. The upper-address bits are
transferred first, followed by the Less Significant bits. 

Following the Start condition, the 24XX64F monitors
the SDA bus, checking the device-type identifier being
transmitted. Upon receiving a ‘1010’ code and appro-
priate device-select bits, the slave device outputs an
Acknowledge signal on the SDA line. Depending on the
state of the R/W bit, the 24XX64F will select a read or
write operation.

FIGURE 5-1:

CONTROL BYTE FORMAT

5.1

Contiguous Addressing Across 
Multiple Devices

The Chip Select bits A2, A1 and A0 can be used to
expand the contiguous address space for up to 512K
bits by adding up to eight 24XX64F devices on the
same bus. In this case, software can use A0 of the con-
trol byte as address bit A13; A1 as address bit A14; and
A2 as address bit A15. It is not possible to sequentially
read across device boundaries.

The SOT-23 package does not support multiple device
addressing on the same bus.

FIGURE 5-2:

ADDRESS SEQUENCE BIT ASSIGNMENTS

1

0

1

0

A2

A1

A0

S

ACK

R/W

Control Code

Chip Select

Bits

Slave Address

Acknowledge Bit

Start Bit

Read/Write Bit

1

0

1

0

A

2

A

1

A

0 R/W

x

x

x

A

11

A

10

A

9

A

7

A

0

A

8

A

12

Control Byte

Address High Byte

Address Low Byte

Control

Code

Chip

Select

bits

x

 = “don’t care” bit

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DS22154B-page 8

 2009-2012 Microchip Technology Inc.

6.0

WRITE OPERATIONS

6.1

Byte Write

Following the Start condition from the master, the
control code (four bits), the Chip Select (three bits) and
the R/W bit (which is a logic low) are clocked onto the
bus by the master transmitter. This indicates to the
addressed slave receiver that the address high byte will
follow once it has generated an Acknowledge bit during
the ninth clock cycle. Therefore, the next byte transmit-
ted by the master is the high-order byte of the word
address and will be written into the Address Pointer of
the 24XX64F. The next byte is the Least Significant
Address Byte. After receiving another Acknowledge
signal from the 24XX64F, the master device will trans-
mit the data word to be written into the addressed mem-
ory location. The 24XX64F acknowledges again and
the master generates a Stop condition. This initiates
the internal write cycle and, during this time, the
24XX64F will not generate Acknowledge signals
(

Figure 6-1

). If an attempt is made to write to the array

with the WP pin held high, the device will acknowledge
the command, but no write cycle will occur, no data will
be written and the device will immediately accept a new
command. After a byte Write command, the internal
address counter will point to the address location fol-
lowing the one that was just written. 

6.2

Page Write 

The write control byte, word address and the first data
byte are transmitted to the 24XX64F in the same way
as in a byte write. However, instead of generating a
Stop condition, the master transmits up to 31 additional
bytes which are temporarily stored in the on-chip page
buffer and will be written into memory once the master
has transmitted a Stop condition. Upon receipt of each
word, the five lower Address Pointer bits are internally
incremented by one. If the master should transmit more
than 32 bytes prior to generating the Stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the Stop condition is received, an inter-
nal write cycle will begin (

Figure 6-2

). If an attempt is

made to write to the array with the WP pin held high, the
device will acknowledge the command, but no write
cycle will occur, no data will be written, and the device
will immediately accept a new command.

6.3

Write Protection

The WP pin allows the user to write-protect 1/4 of the
array (1800h-1FFFh) when the pin is tied to V

CC

. If tied

to V

SS

 the write protection is disabled. The WP pin is

sampled at the Stop bit for every Write command
(

Figure 4-1

). Toggling the WP pin after the Stop bit will

have no effect on the execution of the write cycle. 

Note:

Page write operations are limited to writ-
ing bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size
(or ‘page size’) and end at addresses that
are integer multiples of [page size – 1]. If
a Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page, as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.

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DS22154B-page 9

24AA64F/24LC64F/24FC64F

FIGURE 6-1:

BYTE WRITE

FIGURE 6-2:

PAGE WRITE

x x x

Bus Activity
Master

SDA Line

Bus Activity

S

T

A

R

T

Control

Byte

Address

High Byte

Address
Low Byte

Data

S

T

O

P

A

C

K

A

C

K

A

C

K

A

C

K

x

 = “don’t care” bit

S 1 0 1 0

0

A

2

A

1

A

0

P

x x x

Bus Activity
Master

SDA Line

Bus Activity

S

T

A
R

T

Control

Byte

Address

High Byte

Address
Low Byte

Data Byte 0

S

T

O

P

A

C

K

A

C

K

A

C

K

A

C

K

Data Byte 31

A

C

K

x

 = “don’t care” bit

S 1 0 1 0

0

A

2

A

1

A

0

P

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DS22154B-page 10

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7.0

ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally-timed write cycle and ACK polling
can then be initiated immediately. This involves the
master sending a Start condition followed by the control
byte for a Write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If no ACK is returned, the Start bit and control byte must
be re-sent. If the cycle is complete, the device will
return the ACK and the master can then proceed with
the next Read or Write command. See 

Figure 7-1

 for a

flow diagram of this operation.

FIGURE 7-1:

ACKNOWLEDGE POLLING 
FLOW

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

Next

Operation

No

Yes

Maker
Microchip Technology Inc.
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