2002 Microchip Technology Inc.
DS21189F-page 1
24AA64/24LC64
Device Selection Table
Features
• Single supply with operation down to 1.8V
• Low power CMOS technology
- 1 mA active current typical
- 1 µA standby current (max.) (I-temp)
• Organized as 8 blocks of 8K bit (64K bit)
• 2-wire serial interface bus, I
2
C™ compatible
• Cascadable for up to eight devices
• Schmitt Trigger inputs for noise suppression
• Output slope control to eliminate ground bounce
• 100 kHz (24AA64) and 400 kHz (24LC64) com-
patibility
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 32 bytes
• 2 ms typical write cycle time for page-write
• Hardware write protect for entire memory
• Can be operated as a serial ROM
• Factory programming (QTP) available
• ESD protection > 4,000V
• 1,000,000 erase/write cycles
• Data retention > 200 years
• 8-lead PDIP, SOIC, TSSOP, and MSOP package
• Available temperature ranges:
Description
The Microchip Technology Inc. 24AA64/24LC64
(24XX64*) is a 64 Kbit Electrically Erasable PROM.
The device is organized as eight blocks of 1K x 8-bit
memory with a 2-wire serial interface. Low voltage
design permits operation down to 1.8V with standby
and active currents of only 1 µA and 1 mA respectively.
It has been developed for advanced, low power appli-
cations such as personal communications or data
acquisition. The 24XX64 also has a page-write capabil-
ity for up to 32 bytes of data. Functional address lines
allow up to eight devices on the same bus, for up to
512 Kbits address space. The 24XX64 is available in
the standard 8-pin PDIP, surface mount SOIC, TSSOP
and MSOP packages.
Package Types
Block Diagram
Part
Number
V
CC
Range
Max Clock
Frequency
Temp
Ranges
24AA64
1.8-5.5
400 kHz
(1)
I
24LC64
2.5-5.5
400 kHz
I, E
Note 1: 100 kHz for V
CC
<2.5V
- Industrial (I):
-40°C to
+85°C
- Automotive (E):
-40°C to +125°C
24XX64
A0
A1
A2
Vss
1
2
3
4
8
7
6
5
Vcc
WP
SCL
SDA
PDIP/SOIC/TSSOP/MSOP
24XX64X
WP
Vcc
A0
A1
SCL
SDA
Vss
A2
1
2
3
4
8
7
6
5
ROTATED TSSOP
(24AA64X/24LC64X)
HV GENERATOR
EEPROM
ARRAY
PAGE LATCHES
YDEC
XDEC
SENSE AMP
R/W CONTROL
I/O
CONTROL
LOGIC
I/O
MEMORY
CONTROL
LOGIC
A0 A1
WP
A2
SCL
SDA
V
CC
V
SS
64K I
2
C
™
Serial EEPROM
*24XX64 is used in this document as a generic part number for the 24AA64/24LC64 devices.
24AA64/24LC64
DS21189F-page 2
2002 Microchip Technology Inc.
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
V
CC
.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. V
SS
......................................................................................................... -0.3V to V
CC
+1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temp. with power applied ..........................................................................................................-40°C to +125°C
ESD protection on all pins
......................................................................................................................................................≥ 4 kV
1.1
DC C
haracteristics
† NOTICE: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
DC CHARACTERISTICS
V
CC
= +1.8V to +5.5V
Industrial (I):
T
AMB
= -40°C to +85°C
Automotive (E): T
AMB
= -40°C to +125°C
Param.
No.
Sym
Characteristic
Min
Typ
Max
Units
Conditions
D1
V
IH
WP, SCL and SDA pins
—
—
—
—
—
D2
—
High level input voltage
0.7 V
CC
—
—
V
—
D3
V
IL
Low level input voltage
—
—
0.3 V
CC
V
—
D4
V
HYS
Hysteresis of Schmitt
Trigger inputs
0.05 V
CC
—
—
V
(Note 1)
D5
V
OL
Low level output voltage
—
—
0.40
V
I
OL
= 3.0 mA, V
CC
= 2.5V
D6
I
LI
Input leakage current
—
—
±10
µA
V
IN
=.1V to V
CC
D7
I
LO
Output leakage current
—
—
±10
µA
V
OUT
=.1V to V
CC
D8
C
IN
,
C
OUT
Pin capacitance
(all inputs/outputs)
—
—
10
pF
V
CC
= 5.0V (Note 1)
T
AMB
= 25°C, F
CLK
= 1 MHz
D9
I
CC
write Operating current
—
0.1
3
mA
V
CC
= 5.5V, SCL = 400 kHz
D10
I
CC
read
—
0.05
1
mA
—
D11
I
CCS
Standby current
—
—
.01
—
1
5
µA
µA
Industrial
Automotive
SDA = SCL = V
CC
WP = V
SS
Note 1: This parameter is periodically sampled and not 100% tested.
2: Typical measurements taken at room temperature.
2002 Microchip Technology Inc.
DS21189F-page 3
24AA64/24LC64
1.2
AC C
haracteristics
AC CHARACTERISTICS
V
CC
= +1.8V to +5.5V
Industrial (I):
T
AMB
= -40°C to +85°C
Automotive (E):
T
AMB
= -40°C to +125°C
Param.
No.
Sym
Characteristic
Min
Max
Units
Conditions
1
F
CLK
Clock frequency
—
—
400
100
kHz
2.5V
≤ V
CC
≤ 5.5V
1.8V
≤ V
CC
< 2.5V (24AA64)
2
T
HIGH
Clock high time
600
4000
—
—
ns
2.5V
≤ V
CC
≤ 5.5V
1.8V
≤ V
CC
< 2.5V (24AA64)
3
T
LOW
Clock low time
1300
4700
—
—
ns
2.5V
≤ V
CC
≤ 5.5V
1.8V
≤ V
CC
< 2.5V (24AA64)
4
T
R
SDA and SCL rise time
(Note 1)
—
—
300
1000
ns
2.5V
≤ V
CC
≤ 5.5V
1.8V
≤ V
CC
< 2.5V (24AA64)
5
T
F
SDA and SCL fall time
—
300
ns
(Note 1)
6
T
HD
:
STA
START condition hold time
600
4000
—
—
ns
2.5V
≤ V
CC
≤ 5.5V
1.8V
≤ V
CC
< 2.5V (24AA64)
7
T
SU
:
STA
START condition setup time
600
4700
—
—
ns
2.5V
≤ V
CC
≤ 5.5V
1.8V
≤ V
CC
< 2.5V (24AA64)
8
T
HD
:
DAT
Data input hold time
0
—
ns
(Note 2)
9
T
SU
:
DAT
Data input setup time
100
250
—
—
ns
2.5V
≤ V
CC
≤ 5.5V
1.8V
≤ V
CC
< 2.5V (24AA64)
10
T
SU
:
STO
STOP condition setup time
600
4000
—
—
ns
2.5V
≤ V
CC
≤ 5.5V
1.8V
≤ V
CC
< 2.5V (24AA64)
11
T
AA
Output valid from clock
(Note 2)
—
—
900
3500
ns
2.5V
≤ V
CC
≤ 5.5V
1.8V
≤ V
CC
< 2.5V (24AA64)
12
T
BUF
Bus free time: Time the bus
must be free before a new
transmission can start
1300
4700
—
—
ns
2.5V
≤ V
CC
≤ 5.5V
1.8V
≤ V
CC
< 2.5V (24AA64)
13
T
OF
Output fall time from V
IH
min-
imum to V
IL
maximum
20+0.1C
B
—
250
250
ns
2.5V
≤ V
CC
≤ 5.5V
1.8V
≤ V
CC
≤ 2.5V (24AA64)
14
T
SP
Input filter spike suppression
(SDA and SCL pins)
—
50
ns
(Notes 1 and 3)
15
T
WC
Write cycle time (byte or
page)
—
5
ms
—
16
—
Endurance
1M
—
cycles
25°C, V
CC
= 5.0V, Block Mode
(Note 4)
Note 1: Not 100% tested. C
B
= total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined T
SP
and V
HYS
specifications are due to new Schmitt Trigger inputs which provide improved
noise spike suppression. This eliminates the need for a
T
I
specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on Microchip’s website:
www.microchip.com.
24AA64/24LC64
DS21189F-page 4
2002 Microchip Technology Inc.
FIGURE 1-1:
BUS TIMING DATA
FIGURE 1-2:
BUS TIMING START/STOP
7
5
2
4
8
9
10
12
11
14
6
SCL
SDA
IN
SDA
OUT
3
7
6
D4
10
START
STOP
SCL
SDA
2002 Microchip Technology Inc.
DS21189F-page 5
24AA64/24LC64
2.0
FUNCTIONAL DESCRIPTION
The 24XX64 supports a bi-directional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCL), controls the bus access and generates the
START and STOP conditions, while the 24XX64 works
as slave. Both master and slave can operate as trans-
mitter or receiver, but the master device determines
which mode is activated.
3.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
3.4
Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last six-
teen will be stored when doing a write operation. When
an overwrite does occur it will replace data in a first-in
first-out (FIFO) fashion.
3.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
The device that acknowledges, has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the slave by not generating an Acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (24XX64) will leave the data line
HIGH to enable the master to generate the STOP con-
dition.
FIGURE 3-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
Note:
The 24XX64 does not generate any
Acknowledge bits if an internal program-
ming cycle is in progress.
SCL
SDA
(A)
(B)
(D)
(D)
(A)
(C)
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
24AA64/24LC64
DS21189F-page 6
2002 Microchip Technology Inc.
3.6
Device Addressing
A control byte is the first byte received following the
START condition from the master device (Figure 3-2).
The control byte consists of a four bit control code; for
the 24XX64 this is set as 1010 binary for read and write
operations. The next three bits of the control byte are
the chip select bits (A2, A1, A0). The chip select bits
allow the use of up to eight 24XX64 devices on the
same bus and are used to select which device is
accessed. The chip select bits in the control byte must
correspond to the logic levels on the corresponding A2,
A1, and A0 pins for the device to respond. These bits
are in effect the three Most Significant bits of the word
address.
The last bit of the control byte defines the operation to
be performed. When set to a one a read operation is
selected, and when set to a zero a write operation is
selected. The next two bytes received define the
address of the first data byte (Figure 3-3). Because
only A12...A0 are used, the upper three address bits
are don’t care bits. The upper address bits are trans-
ferred first, followed by the less significant bits.
Following the START condition, the 24XX64 monitors
the SDA bus checking the device type identifier being
transmitted. Upon receiving a 1010 code and appropri-
ate device select bits, the slave device outputs an
Acknowledge signal on the SDA line. Depending on the
state of the R/W bit, the 24XX64 will select a read or
write operation.
FIGURE 3-2:
CONTROL BYTE FORMAT
3.7
Contiguous Addressing Across
Multiple Devices
The chip select bits A2, A1, A0 can be used to expand
the contiguous address space for up to 512K bits by
adding up to eight 24XX64's on the same bus. In this
case, software can use A0 of the control byte as
address bit A13, A1 as address bit A14, and A2 as
address bit A15. It is not possible to sequentially read
across device boundaries.
FIGURE 3-3:
ADDRESS SEQUENCE BIT ASSIGNMENTS
1
0
1
0
A2
A1
A0
S
ACK
R/W
Control Code
Chip Select
Bits
Slave Address
Acknowledge Bit
START Bit
Read/Write Bit
1
0
1
0
A
2
A
1
A
0 R/W
X
X
X
A
11
A
10
A
9
A
7
A
0
A
8
•
•
•
•
•
•
A
12
CONTROL BYTE
ADDRESS HIGH BYTE
ADDRESS LOW BYTE
CONTROL
CODE
CHIP
SELECT
BITS
X = Don’t Care Bit
2002 Microchip Technology Inc.
DS21189F-page 7
24AA64/24LC64
4.0
WRITE OPERATIONS
4.1
Byte Write
Following the START condition from the master, the
control code (four bits), the chip select (three bits), and
the R/W bit (which is a logic low) are clocked onto the
bus by the master transmitter. This indicates to the
addressed slave receiver that the address high byte will
follow after it has generated an Acknowledge bit during
the ninth clock cycle. Therefore, the next byte transmit-
ted by the master is the high-order byte of the word
address and will be written into the address pointer of
the 24XX64. The next byte is the Least Significant
Address Byte. After receiving another Acknowledge
signal from the 24XX64 the master device will transmit
the data word to be written into the addressed memory
location. The 24XX64 acknowledges again and the
master generates a STOP condition. This initiates the
internal write cycle, and during this time the 24XX64
will not generate Acknowledge signals (Figure 4-1). If
an attempt is made to write to the array with the WP pin
held high, the device will acknowledge the command
but no write cycle will occur, no data will be written and
the device will immediately accept a new command.
After a byte write command, the internal address
counter will point to the address location following the
one that was just written.
4.2
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24XX64 in the same way as
in a byte write. But instead of generating a STOP con-
dition, the master transmits up to 31 additional bytes
which are temporarily stored in the on-chip page buffer
and will be written into memory after the master has
transmitted a STOP condition. After receipt of each
word, the five lower address pointer bits are internally
incremented by one. If the master should transmit more
than 32 bytes prior to generating the STOP condition,
the address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the STOP condition is received, an
internal write cycle will begin (Figure 4-2). If an attempt
is made to write to the array with the WP pin held high,
the device will acknowledge the command but no write
cycle will occur, no data will be written and the device
will immediately accept a new command.
4.3
Write Protection
The WP pin allows the user to write protect the entire
array (0000-1FFF) when the pin is tied to V
CC
. If tied to
V
SS
or left floating, the write protection is disabled. The
WP pin is sampled at the STOP bit for every write com-
mand (Figure 3-1) Toggling the WP pin after the STOP
bit will have no effect on the execution of the write
cycle.
Note: Page write operations are limited to writ-
ing bytes within a single physical page,
regardless of the number of bytes actu-
ally being written. Physical page bound-
aries start at addresses that are integer
multiples of the page buffer size (or
‘page size’) and end at addresses that
are integer multiples of [page size - 1]. If
a page write command attempts to write
across a physical page boundary, the
result is that the data wraps around to
the beginning of the current page (over-
writing data previously stored there),
instead of being written to the next page
as might be expected. It is therefore
necessary for the application software to
prevent page write operations that
would attempt to cross a page boundary.
24AA64/24LC64
DS21189F-page 8
2002 Microchip Technology Inc.
FIGURE 4-1:
BYTE WRITE
FIGURE 4-2:
PAGE WRITE
X X X
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
CONTROL
BYTE
ADDRESS
HIGH BYTE
ADDRESS
LOW BYTE
DATA
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
X = don’t care bit
S 1 0 1 0
0
A
2
A
1
A
0
P
X X X
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
CONTROL
BYTE
ADDRESS
HIGH BYTE
ADDRESS
LOW BYTE
DATA BYTE 0
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
DATA BYTE 31
A
C
K
X = don’t care bit
S 1 0 1 0
0
A
2
A
1
A
0
P
2002 Microchip Technology Inc.
DS21189F-page 9
24AA64/24LC64
5.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the STOP condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send-
ing a START condition followed by the control byte for
a write command (R/W = 0). If the device is still busy
with the write cycle, then no ACK will be returned. If no
ACK is returned, then the START bit and control byte
must be re-sent. If the cycle is complete, then the
device will return the ACK and the master can then pro-
ceed with the next read or write command. See
Figure 5-1 for flow diagram.
FIGURE 5-1:
ACKNOWLEDGE POLLING
FLOW
Send
Write Command
Send STOP
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
Next
Operation
NO
YES
24AA64/24LC64
DS21189F-page 10
2002 Microchip Technology Inc.
6.0
READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
control byte is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read.
6.1
Current Address Read
The 24XX64 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous read
access was to address n (n is any legal address), the
next current address read operation would access data
from address n + 1.
Upon receipt of the control byte with R/W bit set to one,
the 24XX64 issues an acknowledge and transmits the
eight bit data word. The master will not acknowledge
the transfer but does generate a STOP condition and
the 24XX64 discontinues transmission (Figure 6-1).
6.2
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24XX64 as part of a write operation (R/W bit set to 0).
After the word address is sent, the master generates a
START condition following the acknowledge. This ter-
minates the write operation, but not before the internal
address pointer is set. Then the master issues the
control byte again but with the R/W bit set to a one. The
24XX64 will then issue an acknowledge and transmit
the 8-bit data word. The master will not acknowledge
the transfer but does generate a STOP condition which
causes the 24XX64 to discontinue transmission
(Figure 6-2). After a random read command, the inter-
nal address counter will point to the address location
following the one that was just read.
6.3
Sequential Read
Sequential reads are initiated in the same way as a ran-
dom read except that after the 24XX64 transmits the
first data byte, the master issues an acknowledge as
opposed to the STOP condition used in a random read.
This acknowledge directs the 24XX64 to transmit the
next sequentially addressed 8-bit word (Figure 6-3).
Following the final byte transmitted to the master, the
master will NOT generate an acknowledge but will gen-
erate a STOP condition. To provide sequential reads
the 24XX64 contains an internal address pointer which
is incremented by one at the completion of each oper-
ation. This address pointer allows the entire memory
contents to be serially read during one operation. The
internal address pointer will automatically roll over from
address 1FFF to address 0000 if the master acknowl-
edges the byte received from the array address 1FFF.
FIGURE 6-1:
CURRENT ADDRESS READ
S
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
O
P
CONTROL
BYTE
DATA (n)
A
C
K
N
O
A
C
K
S
T
A
R
T