1996-2011 Microchip Technology Inc.
DS21166K-page 1
24AA52/24LCS52
Device Selection Table
Features:
• Single Supply with Operation Down to 1.8V
• Low-Power CMOS Technology:
- 1 mA active current, typical
- 1
A standby current, typical (I-temp)
• Organized as 1 Block of 256 Bytes (256 x 8)
• Software Write Protection for Lower 128 Bytes
• Hardware Write Protection for Entire Array
• 2-Wire Serial Interface Bus, I
2
C™ Compatible
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz (24AA52) and 400 kHz (24LCS52)
Compatibility
• Self-Timed Write Cycle (including auto-erase)
• Page Write Buffer for up to 16 Bytes
• ESD Protection > 4,000V
• 1,000,000 Erase/Write Cycles
• Data Retention > 200 Years
• 8-Lead PDIP, SOIC, TSSOP, MSOP, DFN and
TDFN Packages
• Pb-Free Finishes Available
• Available for Extended Temperature Ranges:
- Industrial (I): -40°C to +85°C
Package Types
Description:
The Microchip Technology Inc. 24AA52/24LCS52
(24XXX52*) is a 2 Kbit Electrically Erasable PROM
capable of operation across a broad voltage range
(1.8V to 5.5V). This device has a software write-protect
feature for the lower half of the array, as well as an
external pin that can be used to write-protect the entire
array. The software write-protect feature is enabled by
sending the device a special command. Once this
feature has been enabled, it cannot be reversed. In
addition to the software protect feature, there is a WP
pin that can be used to write-protect the entire array,
regardless of whether the software write-protect
register has been written or not. This allows the system
designer to protect none, half, or all of the array,
depending on the application. The device is organized
as one block of 256 x 8-bit memory with a 2-wire serial
interface. Low-voltage design permits operation down
to 1.8V, with standby and active currents of only 1
A
and 1 mA, respectively. The 24XXX52 also has a page
write capability for up to 16 bytes of data. The 24XXX52
is available in the standard 8-pin PDIP, surface mount
SOIC, TSSOP, MSOP, DFN and TDFN packages.
Block Diagram
Part
Number
V
CC
Range
Max Clock
Frequency
Temp
Ranges
24AA52
1.8-5.5
400 kHz
(1)
I
24LCS52
2.2-5.5
400 kHz
I
Note 1:
100 kHz for V
CC
<2.2V
A0
A1
A2
V
SS
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
PDIP/SOIC/TSSOP/MSOP/DFN/TDFN
A0
A1
A2
V
SS
WP
SCL
SDA
V
CC
8
7
6
5
1
2
3
4
I/O
Control
Logic
Memory
Control
Logic
XDEC
HV Generator
Standard
Array
Software write
Write-Protect
Circuitry
YDEC
V
CC
V
SS
Sense Amp.
R/W Control
SDA SCL
A0 A1 A2
WP
protected area
(00h-7Fh)
2K 2.2V I
2
C
™
Serial EEPROM with Software Write-Protect
*24XXX52 is used in this document as a generic part number
for the 24AA52/24LCS52 devices.
24AA52/24LCS52
DS21166K-page 2
1996-2011 Microchip Technology Inc.
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
V
CC
.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. V
SS
......................................................................................................... -0.3V to V
CC
+1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-40°C to +125°C
ESD protection on all pins
4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
TABLE 1-1:
DC SPECIFICATIONS
DC CHARACTERISTICS
V
CC
= +1.8V to +5.5V
Industrial (I): T
A
= -40°C to +85°C
Param.
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
D1
V
IH
A0, A1, A2, SCL, SDA
and WP pins
—
—
—
—
—
D2
—
High-level input voltage
0.7 V
CC
—
—
V
—
D3
V
IL
Low-level input voltage
—
—
0.3 V
CC
V
0.2 V
CC
for V
CC
< 2.5V
D4
V
HYS
Hysteresis of Schmitt
Trigger inputs
0.05 V
CC
—
—
V
(Note)
D5
V
OL
Low-level output voltage
—
—
0.40
V
I
OL
= 3.0 mA, V
CC
= 2.5V
D6
I
LI
Input leakage current
—
—
±1
A
V
IN
= V
SS
or V
CC
D7
I
LO
Output leakage current
—
—
±1
A
V
OUT
= V
SS
or V
CC
D8
C
IN
,
C
OUT
Pin capacitance
(all inputs/outputs)
—
—
10
pF
V
CC
= 5.0V (Note)
T
A
= 25°C, F
CLK
= 1 MHz
D9
I
CC
write Operating current
—
1.0
3.0
mA
V
CC
= 5.5V, SCL = 400 kHz
D10
I
CC
read
—
0.20
1.0
mA
—
D11
I
CCS
Standby current
—
—
0.36
—
1.0
—
A
Industrial
SDA = SCL = V
CC
A0, A1, A2, WP = V
SS
Note:
This parameter is periodically sampled and not 100% tested.
1996-2011 Microchip Technology Inc.
DS21166K-page 3
24AA52/24LCS52
TABLE 1-2:
AC SPECIFICATIONS
AC CHARACTERISTICS
V
CC
= +1.8V to +5.5V
Industrial (I): T
A
= -40°C to +85°C
Param.
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
1
F
CLK
Clock frequency
—
—
—
—
400
100
kHz
2.2V
V
CC
5.5V
1.8V
V
CC
2.5V (24AA52)
2
T
HIGH
Clock high time
600
4000
—
—
—
—
ns
2.2V
V
CC
5.5V
1.8V
V
CC
2.5V (24AA52)
3
T
LOW
Clock low time
1300
4700
—
—
—
—
ns
2.2V
V
CC
5.5V
1.8V
V
CC
2.5V (24AA52)
4
T
R
SDA and SCL rise time
(Note 1)
—
—
—
—
300
1000
ns
2.2V
V
CC
5.5V
1.8V
V
CC
2.5V (24AA52)
5
T
F
SDA and SCL fall time
—
—
—
300
ns
(Note 1)
6
T
HD
:
STA
Start condition hold time
600
4000
—
—
—
—
ns
2.2V
V
CC
5.5V
1.8V
V
CC
2.5V (24AA52)
7
T
SU
:
STA
Start condition setup
time
600
4700
—
—
—
—
ns
2.2V
V
CC
5.5V
1.8V
V
CC
2.5V (24AA52)
8
T
HD
:
DAT
Data input hold time
0
—
—
—
ns
(Note 2)
9
T
SU
:
DAT
Data input setup time
100
250
—
—
—
—
ns
2.2V
V
CC
5.5V
1.8V
V
CC
2.5V (24AA52)
10
T
SU
:
STO
Stop condition setup
time
600
4000
—
—
—
—
ns
2.2V
V
CC
5.5V
1.8V
V
CC
2.5V (24AA52)
11
T
AA
Output valid from clock
(Note 2)
—
—
—
—
900
3500
ns
2.2V
V
CC
5.5V
1.8V
V
CC
2.5V (24AA52)
12
T
BUF
Bus free time: Time the
bus must be free before
a new transmission can
start
1300
4700
—
—
—
—
ns
2.2V
V
CC
5.5V
1.8V
V
CC
2.5V (24AA52)
13
T
OF
Output fall time from V
IH
minimum to V
IL
maximum
20 + 0.1 C
B
—
—
—
250
250
ns
2.2V
V
CC
5.5V
1.8V
V
CC
2.5V (24AA52)
14
T
SP
Input filter spike
suppression
(SDA and SCL pins)
—
—
50
ns
(Note 1 and Note 3)
15
T
WC
Write cycle time
(byte or page)
—
—
5
ms
—
16
—
Endurance
1M
—
—
cycles 25°C, V
CC
= 5.0V (Note 4)
Note 1: Not 100% tested. C
B
= total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined T
SP
and V
HYS
specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a T
I
specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site
at www.microchip.com.
24AA52/24LCS52
DS21166K-page 4
1996-2011 Microchip Technology Inc.
FIGURE 1-1:
BUS TIMING DATA
FIGURE 1-2:
BUS TIMING START/STOP
7
5
2
4
8
9
10
12
11
14
6
SCL
SDA
IN
SDA
OUT
3
7
6
D4
10
Start
Stop
SCL
SDA
1996-2011 Microchip Technology Inc.
DS21166K-page 5
24AA52/24LCS52
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
PIN FUNCTION TABLE
2.1
A0, A1, A2
The levels on these inputs are compared with the
corresponding bits in the slave address. The chip is
selected if the compare is true.
Up to eight 24XXX52 devices may be connected to the
same bus by using different Chip Select bit
combinations. These inputs must be connected to
either V
SS
or V
CC
.
2.2
Serial Address/Data Input/Output
(SDA)
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal. Therefore, the SDA bus requires a pull-
up resistor to V
CC
(typical 10 k
for 100 kHz, 2 k for
400 kHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.3
Serial Clock (SCL)
This input is used to synchronize the data transfer to
and from the device.
2.4
Write-Protect (WP)
This is the hardware write-protect pin. It can be tied to
V
CC
or V
SS
. If tied to V
CC
, the hardware write protection
is enabled. If the WP pin is tied to V
SS
, the hardware
write protection is disabled.
Symbol
PDIP
SOIC
TSSOP
MSOP
DFN
(1)
TDFN
(1)
Description
A0
1
1
1
1
1
1
Chip Address Input
A1
2
2
2
2
2
2
Chip Address Input
A2
3
3
3
3
3
3
Chip Address Input
V
SS
4
4
4
4
4
4
Ground
SDA
5
5
5
5
5
5
Serial Address/Data I/O
SCL
6
6
6
6
6
6
Serial Clock
WP
7
7
7
7
7
7
Write-Protect Input
V
CC
8
8
8
8
8
8
+1.8V to 5.5V Power Supply
Note 1:
The exposed pad on the DFN/TDFN packages can be connected to V
SS
or left floating.
24AA52/24LCS52
DS21166K-page 6
1996-2011 Microchip Technology Inc.
3.0
FUNCTIONAL DESCRIPTION
The 24XXX52 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, and a device
receiving data, as a receiver. The bus has to be
controlled by a master device, which generates the
Serial Clock (SCL), controls the bus access and gener-
ates the Start and Stop conditions, while the 24XXX52
works as slave. Both master and slave can operate as
transmitter or receiver, but the master device
determines which mode is activated.
4.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1
Bus Not Busy (A)
Both data and clock lines remain high.
4.2
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
4.4
Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of data
bytes transferred between the Start and Stop
conditions is determined by the master device and is,
theoretically, unlimited; although only the last sixteen
will be stored when doing a write operation. When an
overwrite does occur, it will replace data in a first-in,
first-out (FIFO) fashion.
4.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an Acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse, which is associated with this Acknowledge bit.
The device that acknowledges has to pull down the
SDA line during the Acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end-of-
data to the slave by not generating an Acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (24XXX52) will leave the data
line high to enable the master to generate the Stop
condition.
FIGURE 4-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
Note:
The 24XXX52 does not generate any
Acknowledge bits if an internal
programming cycle is in progress.
SCL
SDA
(A)
(B)
(D)
(D)
(A)
(C)
Start
Condition
Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
1996-2011 Microchip Technology Inc.
DS21166K-page 7
24AA52/24LCS52
4.6
Device Addressing
A control byte is the first byte received following the
Start condition from the master device. The first part of
the control byte consists of a 4-bit control code which is
set to ‘1010’ for normal read and write operations and
‘0110’ for writing to the write-protect register. The
control byte is followed by three Chip Select bits (A2,
A1, A0). The Chip Select bits allow the use of up to
eight 24XXX52 devices on the same bus and are used
to determine which device is accessed. The Chip
Select bits in the control byte must correspond to the
logic levels on the corresponding A2, A1 and A0 pins
for the device to respond. The device will not acknowl-
edge if you attempt a Read command with the control
code set to ‘0110’.
The eighth bit of slave address determines if the master
device wants to read or write to the 24XXX52
(Figure 4-2). When set to a one, a read operation is
selected. When set to a zero, a write operation is
selected.
FIGURE 4-2:
CONTROL BYTE
ALLOCATION
5.0
WRITE OPERATIONS
5.1
Byte Write
Following the Start signal from the master, the device
code(4 bits), the Chip Select bits (3 bits) and the R/W
bit, which is a logic low, are placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow,
once it has generated an Acknowledge bit during the
ninth clock cycle. Therefore, the next byte transmitted
by the master is the word address and will be written
into the Address Pointer of the 24XXX52.
After receiving another Acknowledge signal from the
24XXX52, the master device will transmit the data word
to be written into the addressed memory location. The
24XXX52 acknowledges again and the master gener-
ates a Stop condition. This initiates the internal write
cycle, which means that during this time, the 24XXX52
will not generate Acknowledge signals (Figure 5-1). If
an attempt is made to write to the array when the soft-
ware or hardware write protection has been enabled,
the device will acknowledge the command, but no data
will be written. The write cycle time must be observed
even if the write protection is enabled.
5.2
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24XXX52 in the same way
as in a byte write. Instead of generating a Stop condi-
tion, the master transmits up to 15 additional data bytes
to the 24XXX52, which are temporarily stored in the on-
chip page buffer and will be written into the memory
after the master has transmitted a Stop condition. Upon
receipt of each word, the four lower order Address
Pointer bits are internally incremented by one. The
higher order four bits of the word address remain
constant. If the master should transmit more than 16
bytes prior to generating the Stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the Stop condition is received, an
internal write cycle will begin (Figure 5-2). If an attempt
is made to write to the array when the hardware write
protection has been enabled, the device will acknowl-
edge the command, but no data will be written. The
write cycle time must be observed even if the write
protection is enabled.
Operation
Control
Code
Chip
Select
R/W
Read
1010
A2 A1 A0
1
Write
1010
A2 A1 A0
0
Set Write-Protect
Register
0110
A2 A1 A0
0
OR
Start
Read/Write
Slave Address
R/W A
1
0
1
0
A2
A1
A0
0
1
1
0
A2
A1
A0
Note:
Page write operations are limited to writing
bytes within a single physical page,
regardless of the number of bytes actually
being written. Physical page boundaries
start at addresses that are integer multi-
ples of the page buffer size (or ‘page size’)
and end at addresses that are integer mul-
tiples of [page size – 1]. If a Page Write
command attempts to write across a phys-
ical page boundary, the result is that the
data wraps around to the beginning of the
current page (overwriting data previously
stored there), instead of being written to
the next page, as might be expected. It is
therefore necessary for the application
software to prevent page write operations
that would attempt to cross a page
boundary.
24AA52/24LCS52
DS21166K-page 8
1996-2011 Microchip Technology Inc.
FIGURE 5-1:
BYTE WRITE
FIGURE 5-2:
PAGE WRITE
S
P
Bus Activity
Master
SDA Line
Bus Activity
S
T
A
R
T
S
T
O
P
Control
Byte
Word
Address
Data
A
C
K
A
C
K
A
C
K
S
P
Bus Activity
Master
SDA Line
Bus Activity
S
T
A
R
T
Control
Byte
Word
Address
(n)
Data (n)
Data (n + 15)
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Data (n + 1)
1996-2011 Microchip Technology Inc.
DS21166K-page 9
24AA52/24LCS52
6.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition followed by the control byte
for a Write command (R/W =
0
). If the device is still
busy with the write cycle, then no ACK will be returned.
If the cycle is complete, then the device will return the
ACK and the master can then proceed with the next
Read or Write command. See Figure 6-1 for flow
diagram.
FIGURE 6-1:
ACKNOWLEDGE
POLLING FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
Next
Operation
No
Yes
24AA52/24LCS52
DS21166K-page 10
1996-2011 Microchip Technology Inc.
7.0
WRITE PROTECTION
The 24XXX52 has a software write-protect feature that
allows the lower half of the array (addresses 00h-7Fh)
to be permanently write-protected, as well as a WP pin
that can be used to protect the entire array.
7.1
Software Write-Protect
The software write-protect feature is invoked by writing
to the write-protect register. This is done by sending a
command similar to a normal Write command. As shown
in Figure 7-1, the write-protect register is written by
sending a Write command with the slave address set to
‘0110’ instead of ‘1010’ and the address bits and data
bits are “don’t cares.” Once the software write-protect
register has been written, the device will not
acknowledge the ‘0110’ control byte.
FIGURE 7-1:
SETTING WRITE-PROTECT REGISTER
7.2
Resetting the Software
Write-Protect Fuse
It is possible to reset the software write-protect feature
on the 24XXX52. This is done by sending a command
similar to setting the software write-protect command,
except the command is sent before the regular control
byte and is ‘1001’. The full command will be shown in
Figure 7-2. In order for the command to work, a voltage
of Vcc + 5.5V must be applied to the WP pin and must
be sustained for 1
S before the command is given. The
customer should also allow for a 5 ms delay after the
Stop bit for T
WC
.
S
P
Bus Activity
Master
SDA Line
Bus Activity
S
T
A
R
T
S
T
O
P
Control
Byte
Word
Address
Data
A
C
K
A
C
K
A
C
K
0
0
1
1