2002-2012 Microchip Technology Inc.
DS21713M-page 1
24AA32A/24LC32A
Device Selection Table
Features:
• Single Supply with Operation down to 1.7V for
24AA32A Devices, 2.5V for 24LC32A Devices
• Low-Power CMOS Technology:
- Active current 1 mA, typical
- Standby current 1
A, typical
• 2-Wire Serial Interface, I
2
C™ Compatible
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• Page Write Time 5 ms max.
• Self-Timed Erase/Write Cycle
• 32-Byte Page Write Buffer
• Hardware Write-Protect
• ESD Protection > 4,000V
• More than 1 Million Erase/Write Cycles
• Data Retention > 200 Years
• Factory Programming Available
• Packages Include 8-lead PDIP, SOIC, SOIJ,
TSSOP, X-Rotated TSSOP, MSOP, DFN, TDFN,
5-lead SOT-23 and Chip Scale
• Pb-Free and RoHS Compliant
• Temperature Ranges:
- Industrial (I):
-40°C to +85°C
- Automotive (E): -40°C to +125°C
Description:
The Microchip Technology Inc. 24AA32A/24LC32A
(24XX32A*) is a 32 Kbit Electrically Erasable PROM.
The device is organized as a single block of 4K x 8-bit
memory with a 2-wire serial interface. Low-voltage
design permits operation down to 1.7V, with standby
and active currents of only 1
A and 1
mA,
respectively. It has been developed for advanced, low-
power applications such as personal communications
or data acquisition. The 24XX32A also has a page write
capability for up to 32 bytes of data. Functional address
lines allow up to eight devices on the same bus, for up
to 256 Kbits address space. The 24XX32A is available
in the standard 8-pin PDIP, surface mount SOIC, SOIJ,
TSSOP, DFN, TDFN and MSOP packages. The
24XX32A is also available in the 5-lead SOT-23 and
Chip Scale packages.
Block Diagram
Package Types
Part
Number
V
CC
Range
Max. Clock
Frequency
Temp.
Ranges
24AA32A
1.7-5.5
400 kHz
(1)
I
24LC32A
2.5-5.5
400 kHz
I, E
Note 1:
100 kHz for V
CC
<2.5V.
HV Generator
EEPROM
Array
Page Latches
YDEC
XDEC
Sense Amp.
R/W Control
I/O
Control
Logic
I/O
Memory
Control
Logic
A0 A1
WP
A2
SCL
SDA
Vcc
V
SS
A0
A1
A2
V
SS
V
CC
WP
SCL
SDA
1
2
3
4
8
7
6
5
PDIP/MSOP/SOIC/SOIJ/TSSOP
DFN/TDFN
A0
A1
A2
V
SS
WP
SCL
SDA
V
CC
8
7
6
5
1
2
3
4
SOT-23
1
2
3
4
5
WP
V
CC
SCL
V
SS
SDA
CS (Chip Scale)
(1)
1
2
3
4
5
V
CC
WP
SDA
SCL
V
SS
(Top Down View,
Balls Not Visible)
Note 1:
Available in I-temp, “AA” only.
X-Rotated TSSOP
WP
V
CC
A0
A1
1
2
3
4
8
7
6
5
SCL
SDA
V
SS
A2
(X/ST)
32K I
2
C
™
Serial EEPROM
*24XX32A is used in this document as a generic part number for the 24AA32A/24LC32A devices.
24AA32A/24LC32A
DS21713M-page 2
2002-2012 Microchip Technology Inc.
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
V
CC
.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. V
SS
......................................................................................................... -0.3V to V
CC
+1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-40°C to +125°C
ESD protection on all pins
4 kV
TABLE 1-1:
DC CHARACTERISTICS
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
DC CHARACTERISTICS
Industrial (I):
T
A
= -40°C to +85°C, V
CC
= +1.7V to +5.5V
Automotive (E): T
A
= -40°C to +125°C, V
CC
= +2.5V to +5.5V
Param.
No.
Symbol
Characteristic
Min.
Typ.
Max.
Units
Conditions
D1
—
A0, A1, A2, WP, SCL
and SDA pins
—
—
—
—
—
D2
V
IH
High-level input voltage
0.7 V
CC
—
—
V
—
D3
V
IL
Low-level input voltage
—
—
0.3 V
CC
0.2 V
CC
V
V
V
CC
2.5V
V
CC
< 2.5V
D4
V
HYS
Hysteresis of Schmitt
Trigger inputs (SDA,
SCL pins)
0.05 V
CC
—
—
V
V
CC
2.5V (Note 1)
D5
V
OL
Low-level output voltage
—
—
0.40
V
I
OL
= 3.0 mA, V
CC
= 4.5V
I
OL
= 2.1 mA, Vcc = 2.5V
D6
I
LI
Input leakage current
—
—
±1
A
V
IN
= V
SS
or V
CC
D7
I
LO
Output leakage current
—
—
±1
A
V
OUT
= V
SS
or V
CC
D8
C
IN
,
C
OUT
Pin capacitance
(all inputs/outputs)
—
—
10
pF
V
CC
= 5.0V (Note 1)
T
A
= 25°C, F
CLK
= 1 MHz
D9
I
CC
write Operating current
—
0.1
3
mA
V
CC
= 5.5V, SCL = 400 kHz
D10
I
CC
read
—
0.05
400
A
D11
I
CCS
Standby current
—
—
0.01
—
1
5
A
A
Industrial
Automotive
SDA = SCL = V
CC
= 5.5V
A0, A1, A2, WP = V
SS
Note 1:
This parameter is periodically sampled and not 100% tested.
2:
Typical measurements taken at room temperature.
2002-2012 Microchip Technology Inc.
DS21713M-page 3
24AA32A/24LC32A
TABLE 1-2:
AC CHARACTERISTICS
AC CHARACTERISTICS
Industrial (I):
T
A
= -40°C to +85°C, V
CC
= +1.7V to +5.5V
Automotive (E):
T
A
= -40°C to +125°C, V
CC
= +2.5V to +5.5V
Param.
No.
Symbol
Characteristic
Min.
Max.
Units
Conditions
1
F
CLK
Clock Frequency
—
—
400
100
kHz
2.5V
V
CC
5.5V
1.7V
V
CC
2.5V (24AA32A)
2
T
HIGH
Clock High Time
600
4000
—
—
ns
2.5V
V
CC
5.5V
1.7V
V
CC
2.5V (24AA32A)
3
T
LOW
Clock Low Time
1300
4700
—
—
ns
2.5V
V
CC
5.5V
1.7V
V
CC
2.5V (24AA32A)
4
T
R
SDA and SCL Rise Time
(Note 1)
—
—
300
1000
ns
2.5V
V
CC
5.5V
1.7V
V
CC
2.5V (24AA32A)
5
T
F
SDA and SCL Fall Time
—
300
ns
(Note 1)
6
T
HD
:
STA
Start Condition Hold Time
600
4000
—
—
ns
2.5V
V
CC
5.5V
1.7V
V
CC
2.5V (24AA32A)
7
T
SU
:
STA
Start Condition Setup Time
600
4700
—
—
ns
2.5V
V
CC
5.5V
1.7V
V
CC
2.5V (24AA32A)
8
T
HD
:
DAT
Data Input Hold Time
0
—
ns
(Note 2)
9
T
SU
:
DAT
Data Input Setup Time
100
250
—
—
ns
2.5V
V
CC
5.5V
1.7V
V
CC
2.5V (24AA32A)
10
T
SU
:
STO
Stop Condition Setup Time
600
4000
—
—
ns
2.5V
V
CC
5.5V
1.7V
V
CC
2.5V (24AA32A)
11
T
SU
:
WP
WP Setup Time
600
4000
—
—
ns
2.5V
V
CC
5.5V
1.7V
V
CC
< 2.5V (24AA32A)
12
T
HD
:
WP
WP Hold Time
1300
4700
—
—
ns
2.5V
V
CC
5.5V
1.7V
V
CC
< 2.5V (24AA32A)
13
T
AA
Output Valid from Clock
(Note 2)
—
—
900
3500
ns
2.5V
V
CC
5.5V
1.7V
V
CC
2.5V (24AA32A)
14
T
BUF
Bus free time: Time the bus
must be free before a new
transmission can start
1300
4700
—
—
ns
2.5V
V
CC
5.5V
1.7V
V
CC
2.5V (24AA32A)
15
T
OF
Output Fall Time from V
IH
Minimum to V
IL
Maximum
20+0.1C
B
—
250
250
ns
2.5V
V
CC
5.5V
1.7V
V
CC
2.5V (24AA32A)
16
T
SP
Input Filter Spike Suppression
(SDA and SCL pins)
—
50
ns
(Notes 1 and 3)
17
T
WC
Write Cycle Time (byte or
page)
—
5
ms
—
18
—
Endurance
1M
—
cycles Page mode, 25°C, V
CC
5.5V
(Note 4)
Note 1:
Not 100% tested. C
B
= total capacitance of one bus line in pF.
2:
As a transmitter the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3:
The combined T
SP
and V
HYS
specifications are due to new Schmitt Trigger inputs which provide improved
noise spike suppression. This eliminates the need for a
T
I
specification for standard operation.
4:
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained on Microchip’s web site at
www.microchip.com.
24AA32A/24LC32A
DS21713M-page 4
2002-2012 Microchip Technology Inc.
FIGURE 1-1:
BUS TIMING DATA
FIGURE 1-2:
BUS TIMING START/STOP
(unprotected)
(protected)
SCL
SDA
IN
SDA
OUT
WP
5
7
6
16
3
2
8
9
13
D4
4
10
11
12
14
7
6
D4
10
Start
Stop
SCL
SDA
2002-2012 Microchip Technology Inc.
DS21713M-page 5
24AA32A/24LC32A
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
PIN FUNCTION TABLE
2.1
A0, A1, A2 Chip Address Inputs
The A0, A1 and A2 inputs are used by the 24XX32A for
multiple device operation. The levels on these inputs
are compared with the corresponding bits in the slave
address. The chip is selected if the comparison is true.
Up to eight devices may be connected to the same bus
by using different Chip Select bit combinations. These
inputs must be connected to either V
CC
or V
SS
.
In most applications, the chip address inputs A0, A1
and A2 are hard-wired to logic ‘0’ or logic ‘1’. For
applications in which these pins are controlled by a
microcontroller or other programmable device, the chip
address pins must be driven to logic ‘0’ or logic ‘1’
before normal device operation can proceed. Address
pins are not available in the SOT-23 and chip scale
packages.
2.2
Serial Data (SDA)
SDA is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open-drain
terminal, therefore, the SDA bus requires a pull-up
resistor to V
CC
(typical 10 k
for 100 kHz, 2 k for
400 kHz)
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating Start and Stop conditions.
2.3
Serial Clock (SCL)
The SCL input is used to synchronize the data transfer
to and from the device.
2.4
Write-Protect (WP)
This pin must be connected to either V
SS
or V
CC
. If tied
to V
SS
, write operations are enabled. If tied to V
CC
,
write operations are inhibited but read operations are
not affected.
Name PDIP SOIC SOIJ TSSOP
Rotated
TSSOP
DFN
(1)
TDFN
(1)
MSOP SOT-23 CS
Description
A0
1
1
1
1
3
1
1
1
—
—
Chip Address Input
A1
2
2
2
2
4
2
2
2
—
—
Chip Address Input
A2
3
3
3
3
5
3
3
3
—
—
Chip Address Input
V
SS
4
4
4
4
6
4
4
4
2
2
Ground
SDA
5
5
5
5
7
5
5
5
3
5
Serial Address/Data I/O
SCL
6
6
6
6
8
6
6
6
1
4
Serial Clock
WP
7
7
7
7
1
7
7
7
5
3
Write-Protect Input
V
CC
8
8
8
8
2
8
8
8
4
1
+1.7V to 5.5V Power Supply
Note 1: The exposed pad on the DFN/TDFN packages can be connected to V
SS
or left floating.
24AA32A/24LC32A
DS21713M-page 6
2002-2012 Microchip Technology Inc.
3.0
FUNCTIONAL DESCRIPTION
The 24XX32A supports a bidirectional, 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, while a device
receiving data is defined as a receiver. The bus has to
be controlled by a master device which generates the
Serial Clock (SCL), controls the bus access and gener-
ates the Start and Stop conditions, while the 24XX32A
works as slave. Both master and slave can operate as
transmitter or receiver, but the master device
determines which mode is activated.
4.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1
Bus Not Busy (A)
Both data and clock lines remain high.
4.2
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
4.4
Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of data
bytes transferred between Start and Stop conditions is
determined by the master device and is, theoretically,
unlimited (although only the last thirty-two bytes will be
stored when doing a write operation). When an over-
write does occur, it will replace data in a first-in first-out
(FIFO) fashion.
4.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an Acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
The device that acknowledges, has to pull down the
SDA line during the Acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the Acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the slave by not generating an Acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (24XX32A) will leave the data
line high to enable the master to generate the Stop
condition.
FIGURE 4-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
Note:
The 24XX32A does not generate any
Acknowledge bits if an internal
programming cycle is in progress.
SCL
SDA
(A)
(B)
(D)
(D)
(A)
(C)
Start
Condition
Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
2002-2012 Microchip Technology Inc.
DS21713M-page 7
24AA32A/24LC32A
5.0
DEVICE ADDRESSING
A control byte is the first byte received following the
Start condition from the master device (Figure 5-1).
The control byte consists of a four-bit control code. For
the 24XX32A, this is set as ‘1010’ binary for read and
write operations. The next three bits of the control byte
are the Chip Select bits (A2, A1, A0). The Chip Select
bits allow the use of up to eight 24XX32A devices on
the same bus and are used to select which device is
accessed. The Chip Select bits in the control byte must
correspond to the logic levels on the corresponding A2,
A1 and A0 pins for the device to respond. These bits
are in effect the three Most Significant bits of the word
address.
For the SOT-23 and chip scale packages, the address
pins are not available. During device addressing, the
A1, A2, and A0 Chip Selects bits (Figure 5-2) should be
set to ‘0’.
The last bit of the control byte defines the operation to
be performed. When set to a ‘1’, a read operation is
selected. When set to a zero, a write operation is
selected. The next two bytes received define the
address of the first data byte (Figure 5-2). Because
only A11 to A0 are used, the upper four address bits are
“don’t care” bits. The upper address bits are transferred
first, followed by the Less Significant bits.
Following the Start condition, the 24XX32A monitors
the SDA bus checking the device type identifier being
transmitted and, upon receiving a ‘1010’ code and
appropriate device select bits, the slave device outputs
an Acknowledge signal on the SDA line. Depending on
the state of the R/W bit, the 24XX32A will select a read
or write operation.
FIGURE 5-1:
CONTROL BYTE FORMAT
5.1
Contiguous Addressing Across
Multiple Devices
The Chip Select bits A2, A1 and A0 can be used to
expand the contiguous address space for up to 256K
bits by adding up to eight 24XX32A devices on the
same bus. In this case, software can use A0 of the con-
trol byte as address bit A12; A1 as address bit A13; and
A2 as address bit A14. It is not possible to sequentially
read across device boundaries.
The SOT-23 and chip scale packages do not support
multiple device addressing on the same bus.
FIGURE 5-2:
ADDRESS SEQUENCE BIT ASSIGNMENTS
1
0
1
0 A2 A1 A0
S
ACK
R/W
Control Code
Chip Select
Bits
Slave Address
Acknowledge Bit
Start Bit
Read/Write Bit
1
0
1
0
A
2
A
1
A
0 R/W
x
x
x
x
A
11
A
10
A
9
A
7
A
0
A
8
•
•
•
•
•
•
Control Byte
Address High Byte
Address Low Byte
Control
Code
Chip
Select
Bits
x = “don’t care” bit
24AA32A/24LC32A
DS21713M-page 8
2002-2012 Microchip Technology Inc.
6.0
WRITE OPERATIONS
6.1
Byte Write
Following the Start condition from the master, the
control code (4 bits), the Chip Select (3 bits), and the
R/W bit (which is a logic low) are clocked onto the bus
by the master transmitter. This indicates to the
addressed slave receiver that the address high byte
will follow once it has generated an Acknowledge bit
during the ninth clock cycle. Therefore, the next byte
transmitted by the master is the high-order byte of the
word address and will be written into the Address
Pointer of the 24XX32A. The next byte is the Least
Significant Address Byte. After receiving another
Acknowledge signal from the 24XX32A, the master
device will transmit the data word to be written into the
addressed memory location. The 24XX32A acknowl-
edges again and the master generates a Stop
condition. This initiates the internal write cycle and,
during this time, the 24XX32A will not generate
Acknowledge signals (Figure 6-1). If an attempt is
made to write to the array with the WP pin held high,
the device will acknowledge the command, but no
write cycle will occur. No data will be written and the
device will immediately accept a new command. After
a byte Write command, the internal address counter
will point to the address location following the one that
was just written.
6.2
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24XX32A in the same way
as in a byte write. However, instead of generating a
Stop condition, the master transmits up to 31 additional
bytes which are temporarily stored in the on-chip page
buffer and will be written into memory once the master
has transmitted a Stop condition. Upon receipt of each
word, the five lower Address Pointer bits are internally
incremented by ‘1’. If the master should transmit more
than 32 bytes prior to generating the Stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the Stop condition is received, an
internal write cycle will begin (Figure 6-2). If an attempt
is made to write to the array with the WP pin held high,
the device will acknowledge the command, but no write
cycle will occur, no data will be written, and the device
will immediately accept a new command.
6.3
Write Protection
The WP pin allows the user to write-protect the entire
array (000-FFF) when the pin is tied to V
CC
. If tied to
V
SS
the write protection is disabled. The WP pin is
sampled at the Stop bit for every Write command
(Figure 4-1). Toggling the WP pin after the Stop bit will
have no effect on the execution of the write cycle.
Note:
When doing a write of less than 32 bytes
the data in the rest of the page is refreshed
along with the data bytes being written.
This will force the entire page to endure a
write cycle, for this reason endurance is
specified per page.
Note:
Page write operations are limited to writing
bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size (or
‘page size’) and end at addresses that are
integer multiples of [page size – 1]. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
2002-2012 Microchip Technology Inc.
DS21713M-page 9
24AA32A/24LC32A
FIGURE 6-1:
BYTE WRITE
FIGURE 6-2:
PAGE WRITE
x x x
Bus Activity
Master
SDA Line
Bus Activity
S
T
A
R
T
Control
Byte
Address
High Byte
Address
Low Byte
Data
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
x = “don’t care” bit
S 1 0 1 0
0
A
2
A
1
A
0
P
x
x x x
Bus Activity
Master
SDA Line
Bus Activity
S
T
A
R
T
Control
Byte
Address
High Byte
Address
Low Byte
Data Byte 0
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
Data Byte 31
A
C
K
x = “don’t care” bit
S 1 0 1 0
0
A
2
A
1
A
0
P
x
24AA32A/24LC32A
DS21713M-page 10
2002-2012 Microchip Technology Inc.
7.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally-timed write cycle. ACK polling
can then be initiated immediately. This involves the
master sending a Start condition followed by the control
byte for a Write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If no ACK is returned, the Start bit and control byte must
be re-sent. If the cycle is complete, the device will
return the ACK and the master can then proceed with
the next Read or Write command. See Figure 7-1 for
flow diagram of this operation.
FIGURE 7-1:
ACKNOWLEDGE POLLING
FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
Next
Operation
No
Yes