1998-2018 Microchip Technology Inc.
DS20001203V-page 1
24AA256/24LC256/24FC256
Device Selection Table
Features
• Single Supply with Operation Down to 1.7V for
24AA256 and 24FC256 Devices, 2.5V for
24LC256 Devices
• Low-Power CMOS Technology:
- Read current: 400 uA max. at 5.5V, 400 kHz
- Standby current: 1 uA max. at 3.6V, I-temp
• 2-Wire Serial Interface, I
2
C Compatible
• Cascadable up to Eight Devices
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• Page Write Time 5 ms Max.
• Self-Timed Erase/Write Cycle
• 64-Byte Page Write Buffer
• Hardware Write-Protect
• ESD Protection >4000V
• More than One Million Erase/Write Cycles
• Data Retention >200 years
• Factory Programming Available
• Packages Include 8-lead PDIP, SOIC, SOIJ, DFN,
TDFN, TSSOP and MSOP
• RoHS Compliant
• Temperature Ranges:
Description
The Microchip Technology Inc. 24AA256/24LC256/
24FC256 (24XX256*) is a 32K x 8 (256 Kbit) Serial
Electrically Erasable PROM, capable of operation
across a broad voltage range (1.7V to 5.5V). It has
been developed for advanced, low-power applications
such as personal communications or data acquisition.
This device also has a page write capability of up to 64
bytes of data. This device is capable of both random
and sequential reads up to the 256K boundary.
Functional address lines allow up to eight devices on
the same bus, for up to 2 Mbit address space. This
device is available in the standard 8-pin plastic DIP,
SOIC, SOIJ, TSSOP, MSOP, DFN and TDFN pack-
ages. The 24AA256 is also available in the 8-lead Chip
Scale package.
Block Diagram
Package Types
*24XX256 is used in this document as a generic part number for the 24AA256/24LC256/24FC256 devices.
Part
Number
V
CC
Range
Max. Clock
Frequency
Temp.
Ranges
24AA256
1.7-5.5V
400 kHz
(1)
I, E
24LC256
2.5-5.5V
400 kHz
I, E
24FC256
1.7-5.5V
1 MHz
(2)
I
Note 1: 100 kHz for V
CC
< 2.5V.
2: 400 kHz for V
CC
< 2.5V.
- Industrial (I):
-40
C to +85C
- Automotive (E):
-40
C to +125C
HV Generator
EEPROM
Array
Page Latches
YDEC
XDEC
Sense Amp.
R/W Control
Memory
Control
Logic
I/O
Control
Logic
I/O
A0 A1A2
SDA
SCL
V
CC
V
SS
WP
A0
A1
A2
V
SS
V
CC
WP
SCL
SDA
1
2
3
4
8
7
6
5
24
XX2
56
PDIP/SOIC/SOIJ
TSSOP/MSOP
(1)
A0
A1
A2
V
SS
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
24XX
256
DFN/TDFN
A0
A1
A2
V
SS
WP
SCL
SDA
24
XX25
6
5
6
7
8
4
3
2
1
V
CC
Note 1: * Pins A0 and A1 are no connects for the MSOP package only.
Note 2: Available in I-temp, “AA” only.
CS (Chip Scale)
(2)
1
2
3
4
5
6
7
8
V
CC
A1 A0
WP
A2
SDA SCL V
SS
(TOP DOWN VIEW,
BALLS NOT VISIBLE)
256K I
2
C CMOS Serial EEPROM
24AA256/24LC256/24FC256
DS20001203V-page 2
1998-2018 Microchip Technology Inc.
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
V
CC
.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. V
SS
......................................................................................................... -0.6V to V
CC
+1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ................................................................................................-40°C to +125°C
ESD protection on all pins
4 kV
TABLE 1-1:
DC CHARACTERISTICS
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
DC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
V
CC
= +1.7V to 5.5V
T
A
= -40°C to +85°C
Automotive (E):
V
CC
= +1.7V to 5.5V
T
A
= -40°C to +125°C
Param.
No.
Sym.
Characteristic
Min.
Max.
Units
Conditions
—
A0, A1, A2, SCL, SDA
and WP pins:
—
—
—
—
D1
V
IH
High-level input voltage
0.7 V
CC
—
V
—
D2
V
IL
Low-level input voltage
—
0.3 V
CC
0.2 V
CC
V
V
V
CC
2.5V
V
CC
< 2.5V
D3
V
HYS
Hysteresis of Schmitt
Trigger inputs
(SDA, SCL pins)
0.05 V
CC
—
V
V
CC
2.5V (
Note
)
D4
V
OL
Low-level output voltage
—
0.40
V
I
OL
= 3.0 mA @ V
CC
= 4.5V
I
OL
= 2.1 mA @ V
CC
= 2.5V
D5
I
LI
Input leakage current
—
±1
A
V
IN
= V
SS
or V
CC
, WP = V
SS
V
IN
= V
SS
or V
CC
, WP = V
CC
D6
I
LO
Output leakage current
—
±1
A
V
OUT
= V
SS
or V
CC
D7
C
IN
,
C
OUT
Pin capacitance
(all inputs/outputs)
—
10
pF
V
CC
= 5.0V (
Note
)
T
A
= 25°C, F
CLK
= 1 MHz
D8
I
CC
Read Operating current
—
400
A
V
CC
= 5.5V, SCL = 400 kHz
I
CC
Write
—
3
mA
V
CC
= 5.5V
D9
I
CCS
Standby current
—
1.5
A
T
A
= -40°C to +85°C
SCL = SDA = V
CC
= 5.5V
A0, A1, A2, WP = V
SS
—
1
A
T
A
= -40°C to +85°C
SCL = SDA = V
CC
= 3.6V
A0, A1, A2, WP = V
SS
—
5
A
T
A
= -40°C to +125°C
SCL = SDA = V
CC
= 5.5V
A0, A1, A2, WP = V
SS
Note:
This parameter is periodically sampled and not 100% tested.
1998-2018 Microchip Technology Inc.
DS20001203V-page 3
24AA256/24LC256/24FC256
TABLE 1-2:
AC CHARACTERISTICS
AC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
V
CC
= +1.7V to 5.5V
T
A
= -40°C to +85°C
Automotive (E):
V
CC
= +1.7V to 5.5V
T
A
= -40°C to +125°C
Param.
No.
Sym.
Characteristic
Min.
Max.
Units
Conditions
1
F
CLK
Clock frequency
—
—
—
—
100
400
400
1000
kHz
1.7V
V
CC
2.5V
2.5V
V
CC
5.5V
1.7V
V
CC
2.5V 24FC256
2.5V
V
CC
5.5V 24FC256
2
T
HIGH
Clock high time
4000
600
600
500
—
—
—
—
ns
1.7V
V
CC
2.5V
2.5V
V
CC
5.5V
1.7V
V
CC
2.5V 24FC256
2.5V
V
CC
5.5V 24FC256
3
T
LOW
Clock low time
4700
1300
1300
500
—
—
—
—
ns
1.7V
V
CC
2.5V
2.5V
V
CC
5.5V
1.7V
V
CC
2.5V 24FC256
2.5V
V
CC
5.5V 24FC256
4
T
R
SDA and SCL rise time
(
Note 1
)
—
—
—
1000
300
300
ns
1.7V
V
CC
2.5V
2.5V
V
CC
5.5V
1.7V
V
CC
5.5V 24FC256
5
T
F
SDA and SCL fall time
(
Note 1
)
—
—
300
100
ns
All except, 24FC256
1.7V
V
CC
5.5V 24FC256
6
T
HD
:
STA
Start condition hold time
4000
600
600
250
—
—
—
—
ns
1.7V
V
CC
2.5V
2.5V
V
CC
5.5V
1.7V
V
CC
2.5V 24FC256
2.5V
V
CC
5.5V 24FC256
7
T
SU
:
STA
Start condition setup time
4700
600
600
250
—
—
—
—
ns
1.7V
V
CC
2.5V
2.5V
V
CC
5.5V
1.7V
V
CC
2.5V 24FC256
2.5V
V
CC
5.5V 24FC256
8
T
HD
:
DAT
Data input hold time
0
—
ns
(
Note 2
)
9
T
SU
:
DAT
Data input setup time
250
100
100
—
—
—
ns
1.7V
V
CC
2.5V
2.5V
V
CC
5.5V
1.7V
V
CC
5.5V 24FC256
10
T
SU
:
STO
Stop condition setup time
4000
600
600
250
—
—
—
—
ns
1.7V
V
CC
2.5V
2.5V
V
CC
5.5V
1.7V
V
CC
2.5V 24FC256
2.5V
V
CC
5.5V 24FC256
11
T
SU
:
WP
WP setup time
4000
600
600
—
—
—
ns
1.7V
V
CC
2.5V
2.5V
V
CC
5.5V
1.7V
V
CC
5.5V 24FC256
12
T
HD
:
WP
WP hold time
4700
1300
1300
—
—
—
ns
1.7V
V
CC
2.5V
2.5V
V
CC
5.5V
1.7V
V
CC
5.5V 24FC256
Note 1: Not 100% tested. C
B
= total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined T
SP
and V
HYS
specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a T
I
specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site
at www.microchip.com.
24AA256/24LC256/24FC256
DS20001203V-page 4
1998-2018 Microchip Technology Inc.
FIGURE 1-1:
BUS TIMING DATA
13
T
AA
Output valid from clock
(
Note 2
)
—
—
—
—
3500
900
900
400
ns
1.7 V
V
CC
2.5V
2.5 V
V
CC
5.5V
1.7V
V
CC
2.5V 24FC256
2.5 V
V
CC
5.5V 24FC256
14
T
BUF
Bus free time: Time the bus
must be free before a new
transmission can start
4700
1300
1300
500
—
—
—
—
ns
1.7V
V
CC
2.5V
2.5V
V
CC
5.5V
1.7V
V
CC
2.5V 24FC256
2.5V
V
CC
5.5V 24FC256
15
T
OF
Output fall time from V
IH
minimum to V
IL
maximum
C
B
100 pF
10 + 0.1CB
250
250
ns
All except, 24FC256 (
Note 1
)
16
T
SP
Input filter spike suppression
(SDA and SCL pins)
—
50
ns
All except, 24FC256 (
Notes 1
and
3
)
17
T
WC
Write cycle time (byte or
page)
—
5
ms
—
18
—
Endurance
1,000,000
—
cycles Page mode, 25°C, 5.5V (
Note 4
)
AC CHARACTERISTICS (Continued)
Electrical Characteristics:
Industrial (I):
V
CC
= +1.7V to 5.5V
T
A
= -40°C to +85°C
Automotive (E):
V
CC
= +1.7V to 5.5V
T
A
= -40°C to +125°C
Param.
No.
Sym.
Characteristic
Min.
Max.
Units
Conditions
Note 1: Not 100% tested. C
B
= total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined T
SP
and V
HYS
specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a T
I
specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site
at www.microchip.com.
(unprotected)
(protected)
SCL
SDA
IN
SDA
OUT
WP
5
7
6
16
3
2
8
9
13
D3
4
10
11
12
14
1998-2018 Microchip Technology Inc.
DS20001203V-page 5
24AA256/24LC256/24FC256
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in
Table 2-1
.
TABLE 2-1:
PIN FUNCTION TABLE
2.1
A0, A1, A2 Chip Address Inputs
The A0, A1 and A2 inputs are used by the 24XX256 for
multiple device operations. The levels on these inputs
are compared with the corresponding bits in the slave
address. The chip is selected if the compare is true.
For the MSOP package only, pins A0 and A1 are not
connected.
Up to eight devices (two for the MSOP package) may
be connected to the same bus by using different Chip
Select bit combinations. These inputs must be
connected to either V
CC
or V
SS
.
In most applications, the chip address inputs A0, A1
and A2 are hard-wired to logic ‘0’ or logic ‘1’. For
applications in which these pins are controlled by a
microcontroller or other programmable device, the chip
address pins must be driven to logic ‘0’ or logic ‘1’
before normal device operation can proceed.
2.2
Serial Data (SDA)
This is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open drain
terminal. Therefore, the SDA bus requires a pull-up
resistor to V
CC
(typical 10 k
for 100 kHz, 2 k for
400 kHz and 1 MHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.3
Serial Clock (SCL)
This input is used to synchronize the data transfer to
and from the device.
2.4
Write-Protect (WP)
This pin must be connected to either V
SS
or V
CC
. If tied
to V
SS
, write operations are enabled. If tied to V
CC
,
write operations are inhibited but read operations are
not affected.
3.0
FUNCTIONAL DESCRIPTION
The 24XX256 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter and a device
receiving data as a receiver. The bus must be
controlled by a master device which generates the
Serial Clock (SCL), controls the bus access, and
generates the Start and Stop conditions while the
24XX256 works as a slave. Both master and slave can
operate as a transmitter or receiver, but the master
device determines which mode is activated.
Name
PDIP
SOIC
SOIJ
TSSOP
MSOP
DFN
TDFN
CS
Function
A0
1
1
1
1
—
1
1
3
User Configurable Chip Select
A1
2
2
2
2
—
2
2
2
User Configurable Chip Select
(NC)
—
—
—
—
1, 2
—
—
—
Not Connected
A2
3
3
3
3
3
3
3
5
User Configurable Chip Select
V
SS
4
4
4
4
4
4
4
8
Ground
SDA
5
5
5
5
5
5
5
6
Serial Data
SCL
6
6
6
6
6
6
6
7
Serial Clock
WP
7
7
7
7
7
7
7
4
Write-Protect Input
V
CC
8
8
8
8
8
8
8
1
+1.7V to 5.5V (24AA256)
+2.5V to 5.5V (24LC256)
+1.7V to 5.5V (24FC256)
Note:
Exposed pad on DFN/TDFN can be connected to V
SS
or left floating.
24AA256/24LC256/24FC256
DS20001203V-page 6
1998-2018 Microchip Technology Inc.
4.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line, while the clock line is high, will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (
Figure 4-1
).
4.1
Bus Not Busy (A)
Both data and clock lines remain high.
4.2
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high, determines a Start condition. All
commands must be preceded by a Start condition.
4.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line, while the clock
(SCL) is high, determines a Stop condition. All
operations must end with a Stop condition.
4.4
Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device.
4.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an Acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this Acknowledge
bit.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable low during the high period of
the acknowledge related clock pulse. Of course, setup
and hold times must be taken into account. During
reads, a master must signal an end of data to the slave
by NOT generating an Acknowledge bit on the last byte
that has been clocked out of the slave. In this case, the
slave (24XX256) will leave the data line high to enable
the master to generate the Stop condition.
Note:
The 24XX256 does not generate any
Acknowledge bits if an internal
programming cycle is in progress.
1998-2018 Microchip Technology Inc.
DS20001203V-page 7
24AA256/24LC256/24FC256
FIGURE 4-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
FIGURE 4-2:
ACKNOWLEDGE TIMING
Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
Start
Condition
SCL
SDA
(A)
(B)
(D)
(D)
(C)
(A)
SCL
9
8
7
6
5
4
3
2
1
1
2
3
Transmitter must release the SDA line at this point,
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
Receiver must release the SDA line
at this point so the Transmitter can
continue sending data.
Data from transmitte
r
SDA
Acknowledge
Bit
Data from transmitte
r
24AA256/24LC256/24FC256
DS20001203V-page 8
1998-2018 Microchip Technology Inc.
5.0
DEVICE ADDRESSING
A control byte is the first byte received following the
Start condition from the master device (
Figure 5-1
).
The control byte consists of a 4-bit control code. For the
24XX256, this is set as ‘
1010’
binary for read and
write operations. The next three bits of the control byte
are the Chip Select bits (A2, A1, A0). The Chip Select
bits allow the use of up to eight 24XX256 devices on
the same bus and are used to select which device is
accessed. The Chip Select bits in the control byte must
correspond to the logic levels on the corresponding A2,
A1 and A0 pins for the device to respond. These bits
are, in effect, the three Most Significant bits of the word
address.
For the MSOP package, the A0 and A1 pins are not
connected. During device addressing, the A0 and A1
Chip Select bits (Figures 5-1 and 5-2) should be set to
‘0’. Only two 24XX256 MSOP packages can be
connected to the same bus.
The last bit of the control byte defines the operation to
be performed. When set to a one, a read operation is
selected. When set to a zero, a write operation is
selected. The next two bytes received define the
address of the first data byte (
Figure 5-2
). Because
only A14…A0 are used, the upper address bits are a
“don’t care.” The upper address bits are transferred
first, followed by the Less Significant bits.
Following the Start condition, the 24XX256 monitors
the SDA bus checking the device type identifier being
transmitted. Upon receiving a ‘
1010’
code and
appropriate device select bits, the slave device outputs
an Acknowledge signal on the SDA line. Depending on
the state of the R/W bit, the 24XX256 will select a read
or write operation.
FIGURE 5-1:
CONTROL BYTE
FORMAT
5.1
Contiguous Addressing Across
Multiple Devices
The Chip Select bits A2, A1 and A0 can be used to
expand the contiguous address space for up to 2 Mbit
by adding up to eight 24XX256 devices on the same
bus. In this case, software can use A0 of the control
byte as address bit A15; A1 as address bit A16; and A2
as address bit A17. It is not possible to sequentially
read across device boundaries.
For the MSOP package, up to two 24XX256 devices
can be added for up to 512 Kbit of address space. In
this case, software can use A2 of the control byte as
address bit A17. Bits A0 (A15) and A1 (A16) of the
control byte must always be set to a logic ‘0’ for the
MSOP.
FIGURE 5-2:
ADDRESS SEQUENCE BIT ASSIGNMENTS
1
0
1
0
A2
A1
A0
S
ACK
R/W
Control Code
Chip Select
Bits
Slave Address
Acknowledge Bit
Start Bit
Read/Write Bit
1
0
1
0
A
2
A
1
A
0 R/W
x
A
11
A
10
A
9
A
7
A
0
A
8
•
•
•
•
•
•
A
12
Control Byte
Address High Byte
Address Low Byte
Control
Code
Chip
Select
Bits
x = “don’t care” bit
A
13
A
14
1998-2018 Microchip Technology Inc.
DS20001203V-page 9
24AA256/24LC256/24FC256
6.0
WRITE OPERATIONS
6.1
Byte Write
Following the Start condition from the master, the
control code (four bits), the Chip Select (three bits) and
the R/W bit (which is a logic low) are clocked onto the
bus by the master transmitter. This indicates to the
addressed slave receiver that the address high byte will
follow after it has generated an Acknowledge bit during
the ninth clock cycle. Therefore, the next byte
transmitted by the master is the high-order byte of the
word address and will be written into the Address
Pointer of the 24XX256. The next byte is the Least
Significant Address Byte. After receiving another
Acknowledge signal from the 24XX256, the master
device will transmit the data word to be written into the
addressed memory location. The 24XX256 acknowl-
edges again and the master generates a Stop
condition. This initiates the internal write cycle and
during this time, the 24XX256 will not generate
Acknowledge signals (
Figure 6-1
). If an attempt is
made to write to the array with the WP pin held high, the
device will acknowledge the command but no write
cycle will occur, no data will be written, and the device
will immediately accept a new command. After a byte
Write command, the internal address counter will point
to the address location following the one that was just
written.
6.2
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24XX256 in much the same
way as in a byte write. The exception is that instead of
generating a Stop condition, the master transmits up to
63 additional bytes, which are temporarily stored in the
on-chip page buffer, and will be written into memory
once the master has transmitted a Stop condition.
Upon receipt of each word, the six lower Address
Pointer bits are internally incremented by one. If the
master should transmit more than 64 bytes prior to
generating the Stop condition, the address counter will
roll over and the previously received data will be over-
written. As with the byte write operation, once the Stop
condition is received, an internal write cycle will begin
(
Figure 6-2
). If an attempt is made to write to the array
with the WP pin held high, the device will acknowledge
the command, but no write cycle will occur, no data will
be written and the device will immediately accept a new
command.
6.3
Write Protection
The WP pin allows the user to write-protect the entire
array (0000-7FFF) when the pin is tied to V
CC
. If tied to
V
SS
the write protection is disabled. The WP pin is
sampled at the Stop bit for every Write command
(
Figure 1-1
). Toggling the WP pin after the Stop bit will
have no effect on the execution of the write cycle.
Note:
When doing a write of less than 64 bytes
the data in the rest of the page is
refreshed along with the data bytes being
written. This will force the entire page to
endure a write cycle, for this reason
endurance is specified per page.
Note:
Page write operations are limited to
writing bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size
(or ‘page size’) and end at addresses that
are integer multiples of [page size – 1]. If
a Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page, as might be
expected. It is, therefore, necessary for
the application software to prevent page
write operations that would attempt to
cross a page boundary.
24AA256/24LC256/24FC256
DS20001203V-page 10
1998-2018 Microchip Technology Inc.
FIGURE 6-1:
BYTE WRITE
FIGURE 6-2:
PAGE WRITE
x
Bus Activity
Master
SDA Line
Bus Activity
S
T
A
R
T
Control
Byte
Address
High Byte
Address
Low Byte
Data
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
x = “don’t care” bit
S 1 0 1 0
0
A
2
A
1
A
0
P
x
Bus Activity
Master
SDA Line
Bus Activity
S
T
A
R
T
Control
Byte
Address
High Byte
Address
Low Byte
Data Byte 0
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
Data Byte 63
A
C
K
x = “don’t care” bit
S 1 0 1 0
0
A
2
A
1
A
0
P