2005-2013 Microchip Technology Inc.
DS20001941L-page 1
24AA1025/24LC1025/24FC1025
Device Selection Table:
Features:
• Low-Power CMOS Technology:
- Read current 450
A, maximum
- Standby current 5
A, maximum
• 2-Wire Serial Interface, I
2
C™ Compatible
• Cascadable up to Four Devices
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• 1 MHz Clock for FC Versions
• Page Write Time 3 ms, typical
• Self-Timed Erase/Write Cycle
• 128-Byte Page Write Buffer
• Hardware Write-Protect
• ESD Protection >4000V
• More than 1 Million Erase/Write Cycles
• Data Retention >200 Years
• Factory Programming Available
• Packages include 8-lead PDIP, SOIJ and SOIC
• Pb-Free and RoHS Compliant
• Temperature Ranges:
- Industrial (I):
-40
C to +85C
- Automotive (E): -40
C to +125C
Description:
The Microchip Technology Inc. 24AA1025/24LC1025/
24FC1025 (24XX1025*) is a 128K x 8 (1024K bit)
Serial Electrically Erasable PROM, capable of
operation across a broad voltage range (1.7V to 5.5V).
It has been developed for advanced, low-power
applications such as personal communications or data
acquisition. This device has both byte write and page
write capability of up to 128 bytes of data.
This device is capable of both random and sequential
reads. Reads may be sequential within address
boundaries 0000h to FFFFh and 10000h to 1FFFFh.
Functional address lines allow up to four devices on the
same data bus. This allows for up to 4 Mbits total
system EEPROM memory. This device is available in
the standard 8-pin PDIP, SOIC and SOIJ packages.
Package Type
Block Diagram
*24XX1025 is used in this document as a generic part number
for the 24AA1025/24LC1025/24FC1025 devices.
Part
Number
V
CC
Range
Max. Clock
Frequency
Temp.
Ranges
24AA1025
1.7-5.5V
400 kHz
†
I
24LC1025
2.5-5.5V
400 kHz*
I, E
24FC1025
1.8-5.5V
1 MHz
‡
I
†
100 kHz for V
CC
< 2.5V
*100 kHz for V
CC
< 4.5V, E-temp
‡
400 kHz for V
CC
< 2.5V
A0
A1
A2*
V
SS
V
CC
WP
SCL
SDA
1
2
3
4
8
7
6
5
PDIP
SOIJ/SOIC
A0
A1
A2*
V
SS
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
*A2 must be tied to V
CC
.
HV Generator
EEPROM
Array
Page Latches
YDEC
XDEC
Sense AMP
R/W Control
Memory
Control
Logic
I/O
Control
Logic
I/O
A0 A1
SDA
SCL
V
CC
V
SS
WP
1024K I
2
C
™
Serial EEPROM
24AA1025/24LC1025/24FC1025
DS20001941L-page 2
2005-2013 Microchip Technology Inc.
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
V
CC
.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. V
SS
.......................................................................................................... -0.6V to V
CC
+1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-40°C to +125°C
ESD protection on all pins
4 kV
TABLE 1-1:
DC CHARACTERISTICS
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
DC CHARACTERISTICS
Industrial (I):
V
CC
= +1.7V to 5.5V T
A
= -40°C to +85°C
Automotive (E): V
CC
= +2.5V to 5.5V T
A
= -40°C to +125°C
Param.
No.
Sym.
Characteristic
Min.
Max.
Units
Conditions
—
A1, A2, SCL, SDA and
WP pins:
—
—
—
D1
V
IH
High-level input voltage
0.7 V
CC
—
V
D2
V
IL
Low-level input voltage
—
0.3 V
CC
0.2 V
CC
V
V
V
CC
2.5V
V
CC
< 2.5V
D3
V
HYS
Hysteresis of Schmitt
Trigger inputs
(SDA, SCL pins)
0.05 V
CC
—
V
V
CC
2.5V
(Note)
D4
V
OL
Low-level output voltage
—
0.40
V
I
OL
= 3.0 mA @ V
CC
= 4.5V
I
OL
= 2.1 mA @ V
CC
= 2.5V
D5
I
LI
Input leakage current
—
±1
A
V
IN
= V
SS
or V
CC
V
IN
= V
SS
or V
CC
D6
I
LO
Output leakage current
—
±1
A
V
OUT
= V
SS
or V
CC
D7
C
IN
,
C
OUT
Pin capacitance
(all inputs/outputs)
—
10
pF
V
CC
= 5.0V
(Note)
T
A
= 25°C, F
CLK
= 1 MHz
D8
I
CC
Read Operating current
—
450
A
V
CC
= 5.5V, SCL = 400 kHz
I
CC
Write
—
5
mA
V
CC
= 5.5V
D9
I
CCS
Standby current
—
5
A
SCL, SDA, V
CC
= 5.5V
A1, A2, WP = V
SS
Note:
This parameter is periodically sampled and not 100% tested.
2005-2013 Microchip Technology Inc.
DS20001941L-page 3
24AA1025/24LC1025/24FC1025
TABLE 1-2:
AC CHARACTERISTICS
AC CHARACTERISTICS
Industrial (I):
V
CC
= +1.7V to 5.5V T
A
= -40°C to +85°C
Automotive (E): Vcc = +2.5V to 5.5V T
A
= -40°C to +125°C
Param.
No.
Sym.
Characteristic
Min.
Max.
Units
Conditions
1
F
CLK
Clock frequency
—
—
—
—
—
100
100
400
400
1000
kHz
1.7V
V
CC
2.5V
2.5V
V
CC
4.5V, E-temp
2.5V
V
CC
5.5V
1.8V
V
CC
2.5V (24FC1025 only)
2.5V
V
CC
5.5V (24FC1025 only)
2
T
HIGH
Clock high time
4000
4000
600
600
500
—
—
—
—
—
ns
1.7V
V
CC
2.5V
2.5V
V
CC
4.5V, E-temp
2.5V
V
CC
5.5V
1.8V
V
CC
2.5V (24FC1025 only)
2.5V
V
CC
5.5V (24FC1025 only)
3
T
LOW
Clock low time
4700
4700
1300
1300
500
—
—
—
—
—
ns
1.7V
V
CC
2.5V
2.5V
V
CC
4.5V, E-temp
2.5V
V
CC
5.5V
1.8V
V
CC
2.5V (24FC1025 only)
2.5V
V
CC
5.5V (24FC1025 only)
4
T
R
SDA and SCL rise time
(
Note 1
)
—
—
—
—
—
1000
1000
300
300
300
ns
1.7V
V
CC
2.5V
2.5V
V
CC
4.5V, E-temp
2.5V
V
CC
5.5V
1.8V
V
CC
2.5V (24FC1025 only)
2.5V
V
CC
5.5V (24FC1025 only)
5
T
F
SDA and SCL fall time
(
Note 1
)
—
—
300
100
ns
All except 24FC1025
1.8V
V
CC
5.5V (24FC1025 only)
6
T
HD
:
STA
Start condition hold time
4000
4000
600
600
250
—
—
—
—
—
ns
1.7V
V
CC
2.5V
2.5V
V
CC
4.5V, E-temp
2.5V
V
CC
5.5V
1.8V
V
CC
2.5V (24FC1025 only)
2.5V
V
CC
5.5V (24FC1025 only)
7
T
SU
:
STA
Start condition setup time
4700
4700
600
600
250
—
—
—
—
—
ns
1.7V
V
CC
2.5V
2.5V
V
CC
4.5V, E-temp
2.5V
V
CC
5.5V
1.8V
V
CC
2.5V (24FC1025 only)
2.5V
V
CC
5.5V (24FC1025 only)
8
T
HD
:
DAT
Data input hold time
0
—
ns
(
Note 2
)
9
T
SU
:
DAT
Data input setup time
250
250
100
100
100
—
—
—
—
—
ns
1.7V
V
CC
2.5V
2.5V
V
CC
4.5V, E-temp
2.5V
V
CC
5.5V
1.8V
V
CC
2.5V (24FC1025 only)
2.5V
V
CC
5.5V (24FC1025 only)
10
T
SU
:
STO
Stop condition setup time
4000
4000
600
600
250
—
—
—
—
—
ns
1.7V
V
CC
2.5V
2.5V
V
CC
4.5V, E-temp
2.5V
V
CC
5.5V
1.8V
V
CC
2.5V (24FC1025 only)
2.5V
V
CC
5.5V (24FC1025 only)
Note 1: Not 100% tested. C
B
= total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined T
SP
and V
HYS
specifications are due to new Schmitt Trigger inputs which provide improved noise spike
suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but established by characterization. For endurance estimates in a specific application,
please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com.
24AA1025/24LC1025/24FC1025
DS20001941L-page 4
2005-2013 Microchip Technology Inc.
FIGURE 1-1:
BUS TIMING DATA
11
T
SU
:
WP
WP setup time
4000
4000
600
600
600
—
—
—
—
—
ns
1.7V
V
CC
2.5V
2.5V
V
CC
4.5V, E-temp
2.5V
V
CC
5.5V
1.8V
V
CC
2.5V (24FC1025 only)
2.5V
V
CC
5.5V (24FC1025 only)
12
T
HD
:
WP
WP hold time
4700
4700
1300
1300
1300
—
—
—
—
—
ns
1.7V
V
CC
2.5V
2.5V
V
CC
4.5V, E-temp
2.5V
V
CC
5.5V
1.8V
V
CC
2.5V (24FC1025 only)
2.5V
V
CC
5.5V (24FC1025 only)
13
T
AA
Output valid from clock
(
Note 2
)
—
—
—
—
—
3500
3500
900
900
400
ns
1.7V
V
CC
2.5V
2.5V
V
CC
4.5V, E-temp
2.5V
V
CC
5.5V
1.8V
V
CC
2.5V (24FC1025 only)
2.5V
V
CC
5.5V (24FC1025 only)
14
T
BUF
Bus free time: Time the bus
must be free before a new
transmission can start
4700
4700
1300
1300
500
—
—
—
—
—
ns
1.7V
V
CC
2.5V
2.5V
V
CC
4.5V, E-temp
2.5V
V
CC
5.5V
1.8V
V
CC
2.5V (24FC1025 only)
2.5V
V
CC
5.5V (24FC1025 only)
15
T
SP
Input filter spike suppression
(SDA and SCL pins)
—
50
ns
All except 24FC1025 (
Note 1
and
Note 3
)
16
T
WC
Write cycle time (byte or page)
—
5
ms
—
17
Endurance
1,000,000
—
cycles Page mode, 25°C, V
CC
= 5.5V (
Note 4
)
AC CHARACTERISTICS (Continued)
Industrial (I):
V
CC
= +1.7V to 5.5V T
A
= -40°C to +85°C
Automotive (E): Vcc = +2.5V to 5.5V T
A
= -40°C to +125°C
Param.
No.
Sym.
Characteristic
Min.
Max.
Units
Conditions
Note 1: Not 100% tested. C
B
= total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined T
SP
and V
HYS
specifications are due to new Schmitt Trigger inputs which provide improved noise spike
suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but established by characterization. For endurance estimates in a specific application,
please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com.
(unprotected)
(protected)
SCL
SDA
IN
SDA
OUT
WP
5
7
6
15
3
2
8
9
13
D3
4
10
11
12
14
2005-2013 Microchip Technology Inc.
DS20001941L-page 5
24AA1025/24LC1025/24FC1025
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in
Table 2-1
.
TABLE 2-1:
PIN FUNCTION TABLE
2.1
A0, A1 Chip Address Inputs
The A0 and A1 inputs are used by the 24XX1025 for
multiple device operations. The levels on these inputs
are compared with the corresponding bits in the slave
address. The chip is selected if the comparison is true.
Up to four devices may be connected to the same bus
by using different Chip Select bit combinations. In most
applications, the chip address inputs A0 and A1 are
hard-wired to logic ‘0’ or logic ‘1’. For applications in
which these pins are controlled by a microcontroller or
other programmable device, the chip address pins
must be driven to logic ‘0’ or logic ‘1’ before normal
device operation can proceed.
2.2
A2 Chip Address Input
The A2 input is non-configurable Chip Select. This pin
must be tied to V
CC
in order for this device to operate.
If left floating or tied to V
SS
, device operation will be
undefined.
2.3
Serial Data (SDA)
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open-
drain terminal, therefore, the SDA bus requires a pull-
up resistor to V
CC
(typical 10 k
for 100 kHz, 2 kfor
400 kHz and 1 MHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.4
Serial Clock (SCL)
This input is used to synchronize the data transfer from
and to the device.
2.5
Write-Protect (WP)
This pin must be connected to either V
SS
or V
CC
. If tied
to V
SS
, write operations are enabled. If tied to V
CC
,
write operations are inhibited, but read operations are
not affected.
Name
PDIP
SOIJ
SOIC
Function
A0
1
1
1
User Configurable Chip Select
A1
2
2
2
User Configurable Chip Select
A2
3
3
3
Non-Configurable Chip Select.
This pin must be hard-wired to logical 1 state (V
CC
). Operation will
be undefined with this pin left floating or held to logical 0 (V
SS
).
V
SS
4
4
4
Ground
SDA
5
5
5
Serial Data
SCL
6
6
6
Serial Clock
WP
7
7
7
Write-Protect Input
V
CC
8
8
8
+1.7 to 5.5V (24AA1025)
+2.5 to 5.5V (24LC1025)
+1.8 to 5.5V (24FC1025)
24AA1025/24LC1025/24FC1025
DS20001941L-page 6
2005-2013 Microchip Technology Inc.
3.0
FUNCTIONAL DESCRIPTION
The 24XX1025 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter and a device
receiving data as a receiver. The bus must be
controlled by a master device which generates the
Serial Clock (SCL), controls the bus access, and
generates the Start and Stop conditions while the
24XX1025 works as a slave. Both master and slave
can operate as a transmitter or receiver, but the master
device determines which mode is activated.
2005-2013 Microchip Technology Inc.
DS20001941L-page 7
24AA1025/24LC1025/24FC1025
4.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (
Figure 4-1
).
4.1
Bus Not Busy (A)
Both data and clock lines remain high.
4.2
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must end with a Stop condition.
4.4
Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device.
4.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an Acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this Acknowledge
bit.
A device that acknowledges must pull-down the SDA
line during the Acknowledge clock pulse in such a way
that the SDA line is stable low during the high period of
the acknowledge related clock pulse. Of course, setup
and hold times must be taken into account. During
reads, a master must signal an end of data to the slave
by NOT generating an Acknowledge bit on the last byte
that has been clocked out of the slave. In this case, the
slave (24XX1025) will leave the data line high to enable
the master to generate the Stop condition.
FIGURE 4-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
FIGURE 4-2:
ACKNOWLEDGE TIMING
Note:
The 24XX1025 does not generate any
Acknowledge bits if an internal program-
ming cycle is in progress, however, the
control byte that is being polled must
match the control byte used to initiate the
write cycle.
Address or
Acknowledge
Valid
Data
Allowed
To Change
Stop
Condition
Start
Condition
SCL
SDA
(A)
(B)
(D)
(D)
(C)
(A)
SCL
9
8
7
6
5
4
3
2
1
1
2
3
The transmitter must release the SDA line at this
point allowing the receiver to pull the SDA line low
to acknowledge the previous eight bits of data.
The receiver must release the SDA line at this
point so the transmitter can continue sending
data.
Data from transmitter
Data from transmitter
SDA
Acknowledge
Bit
24AA1025/24LC1025/24FC1025
DS20001941L-page 8
2005-2013 Microchip Technology Inc.
5.0
DEVICE ADDRESSING
A control byte is the first byte received following the
Start condition from the master device (
Figure 5-1
).
The control byte consists of a 4-bit control code; for the
24XX1025, this is set as ‘1010’ binary for read and
write operations. The next bit of the control byte is the
block select bit (B0). This bit acts as the A16 address
bit for accessing the entire array. The next two bits of
the control byte are the Chip Select bits (A1, A0). The
Chip Select bits allow the use of up to four 24XX1025
devices on the same bus and are used to select which
device is accessed. The Chip Select bits in the control
byte must correspond to the logic levels on the
corresponding A1 and A0 pins for the device to
respond. These bits are in effect the two Most
Significant bits (MSb) of the word address.
The last bit of the control byte defines the operation to
be performed. When set to a one, a read operation is
selected, and when set to a zero, a write operation is
selected. The next two bytes received define the
address of the first data byte (
Figure 5-2
). The upper
address bits are transferred first, followed by the Least
Significant bits (LSb).
Following the Start condition, the 24XX1025 monitors
the SDA bus checking the device type identifier being
transmitted. Upon receiving a ‘1010’ code and
appropriate device select bits, the slave device outputs
an Acknowledge signal on the SDA line. Depending on
the state of the R/W bit, the 24XX1025 will select a read
or write operation.
This device has an internal addressing boundary
limitation that is divided into two segments of 512K bits.
Block select bit ‘B0’ to control access to each segment.
FIGURE 5-1:
CONTROL BYTE
FORMAT
5.1
Contiguous Addressing Across
Multiple Devices
The Chip Select bits A1 and A0 can be used to expand
the contiguous address space for up to 4 Mbit by add-
ing up to four 24XX1025’s on the same bus. In this
case, software can use A0 of the control byte as
address bit A17 and A1 as address bit A18. It is not
possible to sequentially read across device boundar-
ies.
Each device has internal addressing boundary
limitations. This divides each part into two segments of
512K bits. The block select bit ‘B0’ controls access to
each “half”.
Sequential read operations are limited to 512K blocks.
To read through four devices on the same bus, eight
random Read commands must be given.
FIGURE 5-2:
ADDRESS SEQUENCE BIT ASSIGNMENTS
1
0
1
0
B0
A1
A0
S
ACK
R/W
Control Code
Chip
Bits
Slave Address
Acknowledge Bit
Start Bit
Read/Write Bit
Select
Block
Select
Bits
1
0
1
0
B
0
A
1
A
0 R/W
A
11
A
10
A
9
A
7
A
0
A
8
•
•
•
•
•
•
A
12
Control Byte
Address High Byte
Address Low Byte
Control
Code
Chip
Select
Bits
X = “don’t care” bit
A
13
A
14
Block
Select
Bit
A
15
2005-2013 Microchip Technology Inc.
DS20001941L-page 9
24AA1025/24LC1025/24FC1025
6.0
WRITE OPERATIONS
6.1
Byte Write
Following the Start condition from the master, the
control code (four bits), the block select (one bit), the
Chip Select (two bits), and the R/W bit (which is a logic
low) are clocked onto the bus by the master transmitter.
This indicates to the addressed slave receiver that the
address high byte will follow after it has generated an
Acknowledge bit during the ninth clock cycle.
Therefore, the next byte transmitted by the master is
the high-order byte of the word address and will be
written into the Address Pointer of the 24XX1025. The
next byte is the Least Significant Address Byte. After
receiving another Acknowledge signal from the
24XX1025, the master device will transmit the data
word to be written into the addressed memory location.
The 24XX1025 acknowledges again and the master
generates a Stop condition. This initiates the internal
write cycle and during this time, the 24XX1025 will not
generate Acknowledge signals as long as the control
byte being polled matches the control byte that was
used to initiate the write (
Figure 6-1
). If an attempt is
made to write to the array with the WP pin held high, the
device will acknowledge the command, but no write
cycle will occur, no data will be written and the device
will immediately accept a new command. After a byte
Write command, the internal address counter will point
to the address location following the one that was just
written.
6.2
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24XX1025 in the same way
as in a byte write. But instead of generating a Stop
condition, the master transmits up to 127 additional
bytes, which are temporarily stored in the on-chip page
buffer and will be written into memory after the master
has transmitted a Stop condition. After receipt of each
word, the seven lower Address Pointer bits are
internally incremented by one. If the master should
transmit more than 128 bytes prior to generating the
Stop condition, the address counter will roll over and
the previously received data will be overwritten. As with
the byte write operation, once the Stop condition is
received, an internal write cycle will begin (
Figure 6-2
).
If an attempt is made to write to the array with the WP
pin held high, the device will acknowledge the
command, but no write cycle will occur, no data will be
written and the device will immediately accept a new
command.
6.3
Write Protection
The WP pin allows the user to write-protect the entire
array (00000-1FFFF) when the pin is tied to V
CC
. If tied
to V
SS
the write protection is disabled. The WP pin is
sampled at the Stop bit for every Write command
(
Figure 1-1
). Toggling the WP pin after the Stop bit will
have no effect on the execution of the write cycle.
Note:
When doing a write of less than 128 bytes
the data in the rest of the page is
refreshed along with the data bytes being
written. This will force the entire page to
endure a write cycle, for this reason
endurance is specified per page.
Note:
Page write operations are limited to writ-
ing bytes within a single physical page,
regardless of the number of bytes actually
being written. Physical page boundaries
start at addresses that are integer
multiples of the page buffer size (or ‘page
size’) and end at addresses that are
integer multiples of [page size – 1]. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
24AA1025/24LC1025/24FC1025
DS20001941L-page 10
2005-2013 Microchip Technology Inc.
FIGURE 6-1:
BYTE WRITE
FIGURE 6-2:
PAGE WRITE
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
Control
Byte
Address
High Byte
Address
Low Byte
Data
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
X = “don’t care” bit
S 1 0 1 0
0
B
0
A
1
A
0
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
Control
Byte
Address
High Byte
Address
Low Byte
Data Byte 0
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
Data Byte 127
A
C
K
X = “don’t care” bit
S 1 0 1 0
0
B
0
A
1
A
0
P