© 2009 Microchip Technology Inc.
DS21210N-page 1
24AA024/24LC024/24AA025/24LC025
Device Selection Table
Features:
• Single Supply with Operation from 1.7V to 5.5V
for 24AA024/24AA025 Devices, 2.5V for
24LC024/24LC025 Devices
• Low-Power CMOS Technology:
- Read current 1 mA, typical
- Standby current 1
μA, typical
• 2-Wire Serial Interface, I
2
C™ Compatible
• Cascadable up to Eight Devices
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• Page Write Time 5 ms Maximum
• Self-timed Erase/Write Cycle
• 16-Byte Page Write Buffer
• Hardware Write-Protect on 24XX024 Devices
• ESD Protection >4,000V
• More than 1 Million Erase/Write Cycles
• Data Retention >200 years
• Factory Programming Available
• Packages include 8-lead PDIP, SOIC, TSSOP,
DFN, TDFN and MSOP
• 6-Lead SOT-23 Package, 24XX025 only
• Pb-Free and RoHS Compliant
• Temperature Ranges:
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
Description:
The Microchip Technology Inc. 24AA024/24LC024/
24AA025/24LC025 is a 2 Kbit Serial Electrically
Erasable PROM with a voltage range of 1.7V to 5.5V.
The device is organized as a single block of 256 x 8-bit
memory with a 2-wire serial interface. Low current
design permits operation with typical standby and
active currents of only 1
μA and 1 mA, respectively.
The device has a page write capability for up to 16
bytes of data. Functional address lines allow the
connection of up to eight 24AA024/24LC024/
24AA025/24LC025 devices on the same bus for up to
16K bits of contiguous EEPROM memory. The device
is available in the standard 8-pin PDIP, 8-pin SOIC
(3.90 mm), TSSOP, 2x3 DFN and TDFN and MSOP
packages. The 24AA025/24LC025 is also available in
the 6-lead SOT-23 package.
Package Types
Block Diagram
Part
Number
V
CC
Range
Max
Clock
Temp.
Range
Write
Protect
24AA024
1.7V-5.5V
400 kHz
(1)
I
Yes
24AA025
1.7V-5.5V
400 kHz
(1)
I
No
24LC024
2.5V-5.5V
400 kHz
I, E
Yes
24LC025
2.5V-5.5V
400 kHz
I, E
No
Note 1:
100 kHz for V
CC
< 2.5V
Note:
WP pin is not internally connected on the
24XX025
.
A0
A1
A2
V
SS
V
CC
WP
SCL
SDA
1
2
3
4
8
7
6
5
PDIP/SOIC/TSSOP/MSOP
A0
A1
A2
V
SS
WP
SCL
SDA
V
CC
8
7
6
5
1
2
3
4
SOT-23
V
CC
SCL
SDA
V
SS
A0
A1
DFN/TDFN
1
2
3
4
5
6
I/O
Control
Logic
Memory
Control
Logic
XDEC
HV Generator
EEPROM
Array
Write-Protect
Circuitry
YDEC
V
CC
V
SS
Sense Amp.
R/W Control
SDA SCL
A0 A1 A2
WP*
2K I
2
C
™
Serial EEPROM
24AA024/24LC024/24AA025/24LC025
DS21210N-page 2
© 2009 Microchip Technology Inc.
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
V
CC
.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. V
SS
......................................................................................................... -0.3V to V
CC
+1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ................................................................................................-40°C to +125°C
ESD protection on all pins
......................................................................................................................................................≥ 4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
TABLE 1-1:
DC SPECIFICATIONS
DC CHARACTERISTICS
Industrial (I):
T
A
= -40°C to +85°C, V
CC
= +1.7V to +5.5V
Automotive (E): T
A
= -40°C to +125°C, V
CC
= +2.5V to +5.5V
Param.
No.
Symbol
Characteristic
Min.
Typ.
Max.
Units
Conditions
—
A0, A1, A2, SCL, SDA
and WP pins
—
—
—
—
—
D1
V
IH
High-level input voltage
0.7 V
CC
—
—
V
—
D2
V
IL
Low-level input voltage
—
—
0.3 V
CC
V
0.2 V
CC
for V
CC
< 2.5V
D3
V
HYS
Hysteresis of Schmitt
Trigger inputs
0.05 V
CC
—
—
V
(Note)
D4
V
OL
Low-level output voltage
—
—
0.40
V
I
OL
= 3.0 mA, V
CC
= 2.5V
D5
I
LI
Input leakage current
—
—
±1
μA
V
IN
= V
SS
or V
CC
D6
I
LO
Output leakage current
—
—
±1
μA
V
OUT
= V
SS
or V
CC
D7
C
IN
,
C
OUT
Pin capacitance
(all inputs/outputs)
—
—
10
pF
V
CC
= 5.5V (Note)
T
A
= 25°C, F
CLK
= 1 MHz
D8
I
CC
write
Operating current
—
0.1
3
mA
V
CC
= 5.5V, SCL = 400 kHz
D9
I
CC
read
—
0.05
1
mA
—
D10
I
CCS
Standby current
—
—
0.01
—
1
5
μA
μA
Industrial
Automotive
SDA = SCL = V
CC
A0, A1, A2, WP = V
SS
Note:
This parameter is periodically sampled and not 100% tested.
© 2009 Microchip Technology Inc.
DS21210N-page 3
24AA024/24LC024/24AA025/24LC025
TABLE 1-2:
AC CHARACTERISTICS
AC CHARACTERISTICS
Industrial (I):
T
A
= -40°C to +85°C, V
CC
= +1.7V to +5.5V
Automotive (E): T
A
= -40°C to +125°C, V
CC
= +2.5V to +5.5V
Param.
No.
Symbol
Characteristic
Min.
Max.
Units
Conditions
1
F
CLK
Clock frequency
—
—
100
400
kHz
1.7V
≤ V
CC
< 1.8V
1.8V
≤ V
CC
≤ 5.5V
2
T
HIGH
Clock high time
4000
600
—
—
ns
1.7V
≤ V
CC
< 1.8V
1.8V
≤ V
CC
≤ 5.5V
3
T
LOW
Clock low time
4700
1300
—
—
ns
1.7V
≤ V
CC
< 1.8V
1.8V
≤ V
CC
≤ 5.5V
4
T
R
SDA and SCL rise time (Note 1)
—
—
1000
300
ns
1.7V
≤ V
CC
< 1.8V
1.8V
≤ V
CC
≤ 5.5V
5
T
F
SDA and SCL fall time (Note 1)
—
—
1000
300
ns
1.7V
≤ V
CC
< 1.8V
1.8V
≤ V
CC
≤ 5.5V
6
T
HD
:
STA
Start condition hold time
4000
600
—
—
ns
1.7V
≤ V
CC
< 1.8V
1.8V
≤ V
CC
≤ 5.5V
7
T
SU
:
STA
Start condition setup time
4700
600
—
—
ns
1.7V
≤ V
CC
< 1.8V
1.8V
≤ V
CC
≤ 5.5V
8
T
HD
:
DAT
Data input hold time
0
—
ns
(Note 2)
9
T
SU
:
DAT
Data input setup time
250
100
—
—
ns
1.7V
≤ V
CC
< 1.8V
1.8V
≤ V
CC
≤ 5.5V
10
T
SU
:
STO
Stop condition setup time
4000
600
—
—
ns
1.7V
≤ V
CC
< 1.8V
1.8V
≤ V
CC
≤ 5.5V
11
T
SU
:
WP
WP setup time
4000
600
—
—
ns
1.7V
≤ V
CC
< 1.8V
1.8V
≤ V
CC
≤ 5.5V
12
T
HD
:
WP
WP hold time
4700
600
—
—
ns
1.7V
≤ V
CC
< 1.8V
1.8V
≤ V
CC
≤ 5.5V
13
T
AA
Output valid from clock (Note 2)
—
—
3500
900
ns
1.7V
≤ V
CC
< 1.8V
1.8V
≤ V
CC
≤ 5.5V
14
T
BUF
Bus free time: Time the bus must
be free before a new transmission
can start
1300
4700
—
—
ns
1.7V
≤ V
CC
< 1.8V
1.8V
≤ V
CC
≤ 5.5V
16
T
SP
Input filter spike suppression
(SDA and SCL pins)
—
50
ns
(Note 1 and Note 3)
17
T
WC
Write cycle time (byte or page)
—
5
ms
—
18
—
Endurance
1M
—
cycles
25°C, V
CC
= 5.5V, Block mode
(Note 4)
Note
1: Not 100% tested. C
B
= total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined T
SP
and V
HYS
specifications are due to new Schmitt Trigger inputs, which provide improved noise spike
suppression. This eliminates the need for a T
I
specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please
consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com.
24AA024/24LC024/24AA025/24LC025
DS21210N-page 4
© 2009 Microchip Technology Inc.
FIGURE 1-1:
BUS TIMING DATA
(unprotected)
(protected)
SCL
SDA
In
SDA
Out
WP
5
7
6
16
3
2
8
9
13
D4
4
10
11
12
14
© 2009 Microchip Technology Inc.
DS21210N-page 5
24AA024/24LC024/24AA025/24LC025
2.0
PIN DESCRIPTIONS
Pin Function Table
2.1
SDA Serial Data
SDA is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open-drain
terminal; therefore, the SDA bus requires a pull-up
resistor to V
CC
(typical 10 k
Ω for 100 kHz, 2 kΩ for
400 kHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.2
SCL Serial Clock
The SCL input is used to synchronize the data transfer
from and to the device.
2.3
A0, A1, A2
The levels on the A0, A1 and A2 inputs are compared
with the corresponding bits in the slave address. The
chip is selected if the compare is true. For the SOT-23
package only, pin A2 is not connected.
Up to eight 24AA024/24LC024/24AA025/24LC025
devices (four for the SOT-23 package) may be con-
nected to the same bus by using different Chip Select
bit combinations. These inputs must be connected to
either V
CC
or V
SS
.
2.4
WP (24XX024 Only)
WP is the hardware write-protect pin. It must be tied to
V
CC
or V
SS
. If tied to Vcc, hardware write protection is
enabled. If WP is tied to Vss, the hardware write
protection is disabled. Note that the WP pin is available
only on the 24XX024. This pin is not internally
connected on the 24LC025.
2.5
Noise Protection
The 24AA024/24LC024/24AA025/24LC025 employs a
V
CC
threshold detector circuit which disables the
internal erase/write logic if the V
CC
is below 1.5V at
nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation, even on a noisy bus.
3.0
FUNCTIONAL DESCRIPTION
The 24AA024/24LC024/24AA025/24LC025 supports
a bidirectional, 2-wire bus and data transmission
protocol. A device that sends data onto the bus is
defined as transmitter, while a device receiving data
is defined as receiver. The bus has to be controlled
by a master device that generates the Serial Clock
(SCL), controls the bus access and generates the
Start and Stop conditions, while the 24AA024/
24LC024/24AA025/24LC025 works as slave. Both
master and slave can operate as transmitter or
receiver, but the master device determines which
mode is activated.
Name
PDIP
SOIC
TSSOP
DFN/TDFN
MSOP
SOT-23
Description
A0
1
1
1
1
1
5
Address Pin AO
A1
2
2
2
2
2
4
Address Pin A1
A2
3
3
3
3
3
—
Address Pin A2
V
SS
4
4
4
4
4
2
Ground
SDA
5
5
5
5
5
3
Serial Address/Data I/O
SCL
6
6
6
6
6
1
Serial Clock
WP
7
7
7
7
7
—
Write-Protect Input
V
CC
8
8
8
8
8
6
+1.7 to 5.5V Power Supply
24AA024/24LC024/24AA025/24LC025
DS21210N-page 6
© 2009 Microchip Technology Inc.
4.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1
Bus Not Busy (A)
Both data and clock lines remain high.
4.2
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
4.4
Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is,
theoretically, unlimited (though only the last sixteen will
be stored when performing a write operation). When an
overwrite does occur, it will replace data in a first-in
first-out fashion.
4.5
Acknowledge
Each receiving device, when addressed, is required to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse, which is associated with this Acknowledge bit.
The device that acknowledges has to pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable low during the high period of
the acknowledge-related clock pulse. Of course, setup
and hold times must be taken into account. A master
must signal an end of data to the slave by not generating
an Acknowledge bit on the last byte that has been
clocked out of the slave. In this case, the slave must
leave the data line high to enable the master to generate
the Stop condition (Figure 4-2).
FIGURE 4-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS
FIGURE 4-2:
ACKNOWLEDGE TIMING
Note:
The 24AA024/24LC024/24AA025/24LC025
does not generate any Acknowledge bits if
an internal programming cycle is in prog-
ress.
(A)
(B)
(C)
(D)
(A)
(C)
SCL
SDA
Start
Condition
Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
SCL
9
8
7
6
5
4
3
2
1
1
2
3
Transmitter must release the SDA line at this point allowing
the Receiver to pull the SDA line low to acknowledge the
previous eight bits of data.
Receiver must release the SDA line at this
point so the Transmitter can continue
sending data.
SDA
Acknowledge
Bit
Data from transmitter
Data from transmitter
© 2009 Microchip Technology Inc.
DS21210N-page 7
24AA024/24LC024/24AA025/24LC025
5.0
DEVICE ADDRESSING
A control byte is the first byte received following the
Start condition from the master device (Figure 5-1).
The control byte consists of a four-bit control code. For
the 24AA024/24LC024/24AA025/24LC025, this is set
as ‘1010’ binary for read and write operations. The next
three bits of the control byte are the Chip Select bits
(A2, A1, A0). The Chip Select bits allow the use of up
to eight 24AA024/24LC024/24AA025/24LC025
devices on the same bus and are used to select which
device is accessed. The Chip Select bits in the control
byte must correspond to the logic levels on the corre-
sponding A2, A1 and A0 pins for the device to respond.
These bits are in effect the three Most Significant bits of
the word address.
For the SOT-23 package, the A2 address pin is not
available. During device addressing, the A2 Chip
Select bit should be set to ‘0’.
The last bit of the control byte defines the operation to
be performed. When set to a one, a read operation is
selected. When set to a zero, a write operation is
selected. Following the Start condition, the 24AA024/
24LC024/24AA025/24LC025 monitors the SDA bus
checking the control byte being transmitted. Upon
receiving a ‘1010’ code and appropriate Chip Select
bits, the slave device outputs an Acknowledge signal
on the SDA line. Depending on the state of the R/W bit,
the 24AA024/24LC024/24AA025/24LC025 will select a
read or write operation.
FIGURE 5-1:
CONTROL BYTE FORMAT
5.1
Contiguous Addressing Across
Multiple Devices
The Chip Select bits A2, A1 and A0 can be used to
expand the contiguous address space for up to 16K bits
by adding up to eight 24AA024/24LC024/24AA025/
24LC025 devices on the same bus. In this case, soft-
ware can use A0 of the control byte as address bit A8,
A1 as address bit A9 and A2 as address bit A10. It is
not possible to sequentially read across device
boundaries.
For the SOT-23 package, up to four 24AA025/24LC025
devices can be added for up to 8K bits of address
space. In this case, software can use A0 of the control
byte as address bit A8, and A1 as address bit A9. It is
not possible to sequentially read across device bound-
aries.
1
0
1
0
A2
A1
A0
S
ACK
R/W
Control Code
Chip Select
Bits
Slave Address
Acknowledge Bit
Start Bit
Read/Write Bit
24AA024/24LC024/24AA025/24LC025
DS21210N-page 8
© 2009 Microchip Technology Inc.
6.0
WRITE OPERATIONS
6.1
Byte Write
Following the Start signal from the master, the device
code(4 bits), the Chip Select bits (3 bits) and the R/W
bit (which is a logic-low) is placed onto the bus by the
master transmitter. The device will acknowledge this
control byte during the ninth clock pulse. The next byte
transmitted by the master is the word address and will
be written into the Address Pointer of the 24AA024/
24LC024/24AA025/24LC025. After receiving another
Acknowledge signal from the 24AA024/24LC024/
24AA025/24LC025, the master device will transmit the
data word to be written into the addressed memory
location. The 24AA024/24LC024/24AA025/24LC025
acknowledges again and the master generates a Stop
condition. This initiates the internal write cycle and, dur-
ing this time, the 24AA024/24LC024/24AA025/
24LC025 will not generate Acknowledge signals
(Figure 6-1). If an attempt is made to write to the
protected portion of the array when the hardware write
protection (24XX024 only) has been enabled, the
device will acknowledge the command, but no data will
be written. The write cycle time must be observed even
if write protection is enabled.
6.2
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24AA024/24LC024/
24AA025/24LC025 in the same way as in a byte write.
However, instead of generating a Stop condition, the
master transmits up to 15 additional data bytes to the
24AA024/24LC024/24AA025/24LC025, which are
temporarily stored in the on-chip page buffer and will be
written into the memory once the master has transmit-
ted a Stop condition. Upon receipt of each word, the
four lower-order Address Pointer bits are internally
incremented by one.
The higher-order four bits of the word address remain
constant. If the master should transmit more than 16
bytes prior to generating the Stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte-write
operation, once the Stop condition is received, an
internal write cycle will begin (Figure 6-2). If an attempt
is made to write to the protected portion of the array
when the hardware write protection has been enabled,
the device will acknowledge the command, but no data
will be written. The write cycle time must be observed
even if write protection is enabled.
6.3
Write Protection
The WP pin (available on 24XX024 only) must be tied
to V
CC
or V
SS
. If tied to V
CC
, the entire array will be
write-protected. If the WP pin is tied to V
SS
, write
operations to all address locations are allowed.
The WP pin is not available on the SOT-23 package.
FIGURE 6-1:
BYTE WRITE
FIGURE 6-2:
PAGE WRITE
Note:
Page write operations are limited to writing
bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size (or
‘page size’) and end at addresses that are
integer multiples of [page size – 1]. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page, as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
S
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
S
T
O
P
Control
Byte
Word
Address
Data
A
C
K
A
C
K
A
C
K
S
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
Control
Byte
Word
Address
(n)
Data (n)
Data (n + 15)
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Data (n +1)
© 2009 Microchip Technology Inc.
DS21210N-page 9
24AA024/24LC024/24AA025/24LC025
7.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally-timed write cycle, with ACK
polling being initiated immediately. This involves the
master sending a Start condition followed by the control
byte for a Write command (R/W = 0). If the device is still
busy with the write cycle, no ACK will be returned. If no
ACK is returned, the Start bit and control byte must be
re-sent. If the cycle is complete, the device will return
the ACK and the master can then proceed with the next
Read or Write command. See Figure 7-1 for a flow
diagram of this operation.
FIGURE 7-1:
ACKNOWLEDGE POLLING
FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
Next
Operation
No
Yes
24AA024/24LC024/24AA025/24LC025
DS21210N-page 10
© 2009 Microchip Technology Inc.
8.0
READ OPERATIONS
Read operations are initiated in the same way as write
operations, with the exception that the R/W bit of the
slave address is set to ‘1’. There are three basic types
of read operations: current address read, random read
and sequential read.
8.1
Current Address Read
The 24AA024/24LC024/24AA025/24LC025 contains
an address counter that maintains the address of the
last word accessed, internally incremented by one.
Therefore, if the previous read access was to address
n, the next current address read operation would
access data from address n + 1. Upon receipt of the
slave address with the R/W bit set to ‘1’, the 24AA024/
24LC024/24AA025/24LC025 issues an acknowledge
and transmits the 8-bit data word. The master will not
acknowledge the transfer, but does generate a Stop
condition and the 24AA024/24LC024/24AA025/
24LC025 discontinues transmission (Figure 8-1).
8.2
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is accomplished by sending the word
address to the 24AA024/24LC024/24AA025/24LC025
as part of a write operation. Once the word address is
sent, the master generates a Start condition following
the acknowledge. This terminates the write operation,
but not before the internal Address Pointer is set. The
master then issues the control byte again, but with the
R/W bit set to a ‘1’. The 24AA024/24LC024/24AA025/
24LC025 will then issue an acknowledge and transmits
the eight bit data word. The master will not acknowl-
edge the transfer but does generate a Stop condition
and the 24AA024/24LC024/24AA025/24LC025
discontinues transmission (Figure 8-2). After this
command, the internal address counter will point to the
address location following the one that was just read.
8.3
Sequential Read
Sequential reads are initiated in the same way as a
random read except that after the 24AA024/24LC024/
24AA025/24LC025 transmits the first data byte, the
master issues an acknowledge (as opposed to a Stop
condition in a random read). This directs the 24AA024/
24LC024/24AA025/24LC025 to transmit the next
sequentially-addressed 8-bit word (Figure 8-3).
To provide sequential reads, the 24AA024/24LC024/
24AA025/24LC025 contains an internal Address
Pointer that is incremented by one upon completion of
each operation. This Address Pointer allows the entire
memory contents to be serially read during one
operation. The internal Address Pointer will
automatically roll over from address 0FFh to address
000h.
FIGURE 8-1:
CURRENT ADDRESS
READ
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
P
S
S
T
O
P
Control
Byte
S
T
A
R
T
Data
A
C
K
N
O
A
C
K