2009-2018 Microchip Technology Inc.
DS20001711K-page 1
24AA01/24LC01B/24FC01
Device Selection Table
Features
• Single Supply with Operation down to 1.7V for
24AAXX and 24FCXX Devices, 2.5V for 24LCXX
Devices
• Low-Power CMOS Technology:
- Read current 1 mA, maximum
- Standby current 1 µA, maximum (I-temp.)
• 2-Wire Serial Interface, I
2
C Compatible
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz, 400 kHz and 1 MHz Compatibility
• Page Write Time: 5 ms, Maximum
• Self-Timed Erase/Write Cycle
• 8-Byte Page Write Buffer
• Hardware Write-Protect
• ESD Protection >4,000V
• More than 1 Million Erase/Write Cycles
• Data Retention >200 Years
• Factory Programming Available
• RoHS Compliant
• Temperature Ranges:
- Industrial (I): -40°C to +85°C
- Extended (E): -40°C to +125°C
• Automotive AEC-Q100 Qualified
Packages:
• 8-Lead DFN, 8-Lead MSOP, 8-Lead PDIP, 8-Lead
SOIC, 8-Lead TDFN, 8-Lead TSSOP, 8-Lead
UDFN, 5-Lead SOT-23 and 5-Lead SC-70
Description
The Microchip Technology Inc. 24XX01
(
1
)
is a 1 Kbit
Electrically Erasable PROM. The device is organized
as one block of 128 x 8-bit memory with a 2-wire serial
interface. Its low-voltage design permits operation
down to 1.7V with standby and active currents of only
1 µA and 1 mA, respectively. The 24XX01 also has a
page write capability for up to 8 bytes of data.
Package Types
Part Number
V
CC
Range
Max. Clock Frequency
Temp. Ranges
Available Packages
24AA01
1.7V-5.5V
400 kHz
(
1
)
I
P, SN, MS, ST, MC, LT, MNY, OT
24LC01B
2.5V-5.5V
400 kHz
I, E
P, SN, MS, ST, MC, LT, MNY, OT
24FC01
1.7V-5.5V
1 MHz
I, E
P, SN, MS, ST, MUY, OT
Note 1: 100 kHz for V
CC
< 2.5V
Note 1: 24XX01 is used in this document as a
generic part number for the
24AA01/24LC01B/24FC01 devices.
SOIC, TSSOP
A0
A1
A2
V
SS
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
DFN/TDFN/UDFN
A0
A1
A2
V
SS
WP
SCL
SDA
V
CC
SOT-23/SC-70
SCL
Vss
SDA
WP
Vcc
Note 1: Pins A0, A1 and A2 are not used by the
24XX01 (no internal connections).
(Top View)
(Top View)
1
2
3
4
8
7
6
5
(Top View)
A0
A1
A2
V
SS
V
CC
WP
SCL
SDA
1
2
3
4
8
7
6
5
PDIP, MSOP
(Top View)
1
5
4
3
2
(
1
)
(
1
)
(
1
)
(
1
)
(
1
)
(
1
)
(
1
)
(
1
)
(
1
)
1K I
2
C Serial EEPROM
24AA01/24LC01B/24FC01
DS20001711K-page 2
2009-2018 Microchip Technology Inc.
Block Diagram
HV Generator
EEPROM
Array
Page Latches
YDEC
XDEC
Sense Amp.
Memory
Control
Logic
I/O
Control
Logic
I/O
WP
SDA
SCL
V
CC
V
SS
R/W Control
2009-2018 Microchip Technology Inc.
DS20001711K-page 3
24AA01/24LC01B/24FC01
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
V
CC
.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. V
SS
..........................................................................................................-0.3V to V
CC
+1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-40°C to +125°C
ESD protection on all pins
4 kV
TABLE 1-1:
DC CHARACTERISTICS
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
DC CHARACTERISTICS
Industrial (I):
T
A
= -40°C to +85°C, V
CC
= +1.7V to +5.5V
Extended (E): T
A
= -40°C to +125°C, V
CC
= +2.5V to +5.5V (24LC01B)
Extended (E): T
A
= -40°C to +125°C, V
CC
= +1.7V to +5.5V (24FC01)
Param.
No.
Symbol
Characteristic
Min.
Typ.
Max.
Units
Conditions
D1
V
IH
High-Level Input Voltage
0.7 V
CC
—
—
V
D2
V
IL
Low-Level Input Voltage
—
—
0.3 V
CC
V
D3
V
HYS
Hysteresis of Schmitt
Trigger Inputs
0.05 V
CC
—
—
V
(
Note
)
D4
V
OL
Low-Level Output
Voltage
—
—
0.40
V
I
OL
= 3.0 mA, V
CC
= 2.5V
D5
I
LI
Input Leakage Current
—
—
±1
µA
V
IN
= V
SS
or V
CC
D6
I
LO
Output Leakage Current
—
—
±1
µA
V
OUT
= V
SS
or V
CC
D7
C
IN
,
C
OUT
Pin Capacitance
(all inputs/outputs)
—
—
10
pF
V
CC
= 5.0V (
Note
)
T
A
= 25°C, F
CLK
= 1 MHz
D8
I
CCWRITE
Operating Current
—
—
3
mA
V
CC
= 5.5V, SCL = 400 kHz
D9
I
CCREAD
—
—
1
mA
V
CC
= 5.5V, SCL = 400 kHz
D10
I
CCS
Standby Current
—
—
1
µA
SDA = SCL = V
CC
WP = V
SS
, I-Temp.
—
—
3
µA
SDA = SCL = V
DD
WP = V
SS
, E-Temp. (24FC01)
—
—
5
µA
SDA = SCL = V
CC
WP = V
SS
, E-Temp. (24LC01B)
Note:
This parameter is periodically sampled and not 100% tested.
24AA01/24LC01B/24FC01
DS20001711K-page 4
2009-2018 Microchip Technology Inc.
TABLE 1-2
AC CHARACTERISTICS
AC CHARACTERISTICS
Industrial (I): T
A
= -40°C to +85°C, V
CC
= +1.7V to +5.5V
Extended (E): T
A
= -40°C to +125°C, V
CC
= +2.5V to +5.5V (24LC01B)
Extended (E): T
A
= -40°C to +125°C, V
CC
= +1.7V to +5.5V (24FC01)
Param.
No.
Symbol
Characteristic
Min.
Typ.
Max.
Units
Conditions
1
F
CLK
Clock Frequency
—
—
400
kHz
2.5V ≤ V
CC
≤ 5.5V
—
—
100
kHz
1.7V ≤ V
CC
< 2.5V (24AA01)
—
—
1000
kHz
1.7V ≤ V
CC
≤ 5.5V (24FC01)
2
T
HIGH
Clock High Time
600
—
—
ns
2.5V ≤ V
CC
≤ 5.5V
4000
—
—
ns
1.7V ≤ V
CC
< 2.5V (24AA01)
260
—
—
ns
1.7V ≤ V
CC
≤ 5.5V (24FC01)
3
T
LOW
Clock Low Time
1300
—
—
ns
2.5V ≤ V
CC
≤ 5.5V
4700
—
—
ns
1.7V ≤ V
CC
< 2.5V (24AA01)
500
—
—
ns
1.7V ≤ V
CC
≤ 5.5V (24FC01)
4
T
R
SDA and SCL Rise Time
—
—
300
ns
2.5V ≤ V
CC
≤ 5.5V (
Note 1
)
—
—
1000
ns
1.7V ≤ V
CC
< 2.5V (24AA01)
(
Note 1
)
—
—
1000
ns
1.7V ≤ V
CC
≤ 5.5V (24FC01)
(
Note 1
)
5
T
F
SDA and SCL Fall Time
—
—
300
ns
(
Note 1
)
6
T
HD
:
STA
Start Condition Hold Time
600
—
—
ns
2.5V ≤ V
CC
≤ 5.5V
4000
—
—
ns
1.7V ≤ V
CC
< 2.5V (24AA01)
250
—
—
ns
1.7V ≤ V
CC
≤ 5.5V (24FC01)
7
T
SU
:
STA
Start Condition Setup
Time
600
—
—
ns
2.5V ≤ V
CC
≤ 5.5V
4700
—
—
ns
1.7V ≤ V
CC
< 2.5V (24AA01)
250
—
—
ns
1.7V ≤ V
CC
≤ 5.5V (24FC01)
8
T
HD
:
DAT
Data Input Hold Time
0
—
—
ns
(
Note 2
)
9
T
SU
:
DAT
Data Input Setup Time
100
—
—
ns
2.5V ≤ V
CC
≤ 5.5V
250
—
—
ns
1.7V ≤ V
CC
< 2.5V (24AA01)
50
—
—
ns
1.7V ≤ V
CC
≤ 5.5V (24FC01)
10
T
SU
:
STO
Stop Condition Setup
Time
600
—
—
ns
2.5V ≤ V
CC
≤ 5.5V
4000
—
—
ns
1.7V ≤ V
CC
< 2.5V (24AA01)
250
—
—
ns
1.7V ≤ V
CC
≤ 5.5V (24FC01)
11
T
SU
:
WP
WP Setup Time
0
—
—
ns
1.7V ≤ V
CC
≤ 5.5V (24FC01)
12
T
HD
:
WP
WP Hold Time
1000
—
—
ns
1.7V ≤ V
CC
≤ 5.5V (24FC01)
13
T
AA
Output Valid from Clock
—
—
900
ns
2.5V ≤ V
CC
≤ 5.5V (
Note 2
)
—
—
3500
ns
1.7V ≤ V
CC
< 2.5V (24AA01)
(
Note 2
)
—
—
450
ns
1.7V ≤ V
CC
≤ 5.5V (24FC01)
(
Note 2
)
Note 1: Characterized but not 100% tested.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: C
B
= total capacitance of one bus line in pF.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s website at
www.microchip.com.
2009-2018 Microchip Technology Inc.
DS20001711K-page 5
24AA01/24LC01B/24FC01
FIGURE 1-1:
BUS TIMING DATA
14
T
BUF
Bus Free Time: The time
the bus must be free
before a new transmis-
sion can start
1300
—
—
ns
2.5V ≤ V
CC
≤ 5.5V
4700
—
—
ns
1.7V ≤ V
CC
< 2.5V (24AA01)
500
—
—
ns
1.7V ≤ V
CC
≤ 5.5V (24FC01)
15
T
OF
Output Fall Time from V
IH
Minimum to V
IL
Maximum
20+0.1C
B
—
250
ns
2.5V ≤ V
CC
≤ 5.5V (24LC01B)
(
Notes 1
and
3
)
—
—
250
ns
1.7V ≤ V
CC
< 2.5V (24AA01)
(
Note 1
)
16
T
SP
Input Filter Spike
Suppression
(SDA and SCL pins)
—
—
50
ns
(
Note 1
)
17
T
WC
Write Cycle Time
(byte or page)
—
—
5
ms
18
Endurance
1,000,000
—
—
cycles 25°C, 5.5V, Page Mode (
Note 4
)
Note 1: Characterized but not 100% tested.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: C
B
= total capacitance of one bus line in pF.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s website at
www.microchip.com.
TABLE 1-2
AC CHARACTERISTICS (CONTINUED)
AC CHARACTERISTICS (Continued)
Industrial (I): T
A
= -40°C to +85°C, V
CC
= +1.7V to +5.5V
Extended (E): T
A
= -40°C to +125°C, V
CC
= +2.5V to +5.5V (24LC01B)
Extended (E): T
A
= -40°C to +125°C, V
CC
= +1.7V to +5.5V (24FC01)
Param.
No.
Symbol
Characteristic
Min.
Typ.
Max.
Units
Conditions
(unprotected)
(protected)
SCL
SDA
IN
SDA
OUT
WP
5
7
6
16
3
2
8
9
13
D3
4
10
11
12
14
24AA01/24LC01B/24FC01
DS20001711K-page 6
2009-2018 Microchip Technology Inc.
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in
Table 2-1
.
TABLE 2-1:
PIN FUNCTION TABLE
2.1
A0, A1, A2
The A0, A1 and A2 pins are not used by the 24XX01.
They may be left floating or tied to either V
SS
or V
CC
.
2.2
Serial Address/Data Input/Output
(SDA)
The SDA input is a bidirectional pin used to transfer
addresses and data into and out of the device. Since
it is an open-drain terminal, the SDA bus requires a
pull-up resistor to V
CC
(typical 10 kΩ for 100 kHz,
2 kΩ for 400 kHz and 1 MHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating Start and Stop conditions.
2.3
Serial Clock (SCL)
The SCL input is used to synchronize the data transfer
to and from the device.
2.4
Write-Protect (WP)
This pin must be connected to either V
SS
or V
CC
.
If tied to V
SS
, normal memory operation is enabled
(read/write the entire memory 00-7F).
If tied to V
CC
, write operations are inhibited. The entire
memory will be write-protected. Read operations are
not affected.
Name
DFN MSOP PDIP
SC-70 SOIC SOT-23 TDFN TSSOP UDFN
Description
A0
1
1
1
—
1
—
1
1
1
Not Connected
A1
2
2
2
—
2
—
2
2
2
Not Connected
A2
3
3
3
—
3
—
3
3
3
Not Connected
V
SS
4
4
4
2
4
2
4
4
4
Ground
SDA
5
5
5
3
5
3
5
5
5
Serial Address/Data I/O
SCL
6
6
6
1
6
1
6
6
6
Serial Clock
WP
7
7
7
5
7
5
7
7
7
Write-Protect Input
V
CC
8
8
8
4
8
4
8
8
8
Power Supply
2009-2018 Microchip Technology Inc.
DS20001711K-page 7
24AA01/24LC01B/24FC01
3.0
FUNCTIONAL DESCRIPTION
The 24XX01 supports a bidirectional, 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, while defining a
device receiving data as a receiver. The bus has to be
controlled by a master device which generates the
Serial Clock (SCL), controls the bus access and
generates the Start and Stop conditions, while the
24XX01 works as slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is activated.
4.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (
Figure 4-1
).
4.1
Bus Not Busy (A)
Both data and clock lines remain high.
4.2
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
4.4
Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of data
bytes transferred between the Start and Stop
conditions is determined by the master device and is,
theoretically, unlimited (although only the last eight will
be stored when doing a write operation). When an
overwrite does occur, it will replace data based on the
first-in first-out (FIFO) principle.
4.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable-low during the high
period of the acknowledge-related clock pulse.
Moreover, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the slave by not generating an Acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (24XX01) will leave the data line
high to enable the master to generate the Stop
condition.
FIGURE 4-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
Note:
The 24XX01 does not generate any
Acknowledge bits if an internal
programming cycle is in progress.
SCL
SDA
(A)
(B)
(D)
(D)
(A)
(C)
Start
Condition
Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
24AA01/24LC01B/24FC01
DS20001711K-page 8
2009-2018 Microchip Technology Inc.
5.0
DEVICE ADDRESSING
A control byte is the first byte received following the
Start condition from the master device. The control byte
consists of a four-bit control code. For the 24XX01, this
is set as ‘
1010
’ binary for read and write operations.
The next three bits of the control byte are “don’t cares”
for the 24XX01. The combination of the 4-bit control
code and the next three bits are called the slave
address.
The last bit of the control byte is the Read/Write (R/W)
bit and it defines the operation to be performed. When
set to ‘
1
’, a read operation is selected. When set to ‘
0
’,
a write operation is selected. Following the Start
condition, the 24XX01 monitors the SDA bus, checking
the device type identifier being transmitted. Upon
receiving a valid slave address and the R/W bit, the
slave device outputs an Acknowledge signal on the
SDA line. Depending on the state of the R/W bit, the
24XX01 will select a read or write operation.
The next byte received defines the address of the first
data byte within the selected block (
Figure 5-2
).
Because only A6…A0 are used, the upper address bit
is a “don’t care”.
FIGURE 5-1:
CONTROL BYTE
ALLOCATION
FIGURE 5-2:
ADDRESS SEQUENCE BIT ASSIGNMENTS
Operation
Control
Code
Block Select
R/W
Read
1010
Block Address
1
Write
1010
Block Address
0
1
0
1
0
x
x
x
R/W ACK
Start Bit
Read/Write Bit
x = “don’t care”
S
Slave Address
Acknowledge Bit
Control Code
Block
Select
Bits
1
0
1
0
x
x
R/W
A
6
A
0
•
•
•
•
•
Control Byte
Word Address Byte
Control
Code
Block
Select
bits
x = “don’t care”
x
x
2009-2018 Microchip Technology Inc.
DS20001711K-page 9
24AA01/24LC01B/24FC01
6.0
WRITE OPERATION
6.1
Byte Write
Following the Start condition from the master, the
device code (4 bits), the block address (3 bits, “don’t
cares”) and the R/W bit, which is a logic-low, is placed
onto the bus by the master transmitter. This indicates to
the addressed slave receiver that a byte with a word
address will follow after it has generated an
Acknowledge bit during the ninth clock cycle.
Therefore, the next byte transmitted by the master is
the word address and will be written into the Address
Pointer of the 24XX01. After receiving another
Acknowledge signal from the 24XX01, the master
device will transmit the data word to be written into the
addressed memory location. The 24XX01
acknowledges again and the master generates a Stop
condition. This initiates the internal write cycle, and,
during this time, the 24XX01 will not generate
Acknowledge signals (
Figure 6-1
).
6.2
Page Write
The write control byte, word address and first data byte
are transmitted to the 24XX01 in the same way as in a
byte write. However, instead of generating a Stop
condition, the master transmits up to 8 data bytes to the
24XX01, which are temporarily stored in the on-chip
page buffer and will be written into the memory once
the master has transmitted a Stop condition. Upon
receipt of each word, the three lower-order Address
Pointer bits, which form the byte counter, are internally
incremented by one. The higher-order five bits of the
word address remain constant. If the master should
transmit more than eight words prior to generating the
Stop condition, the Address Pointer will roll over and
the previously received data will be overwritten. As with
the byte write operation, once the Stop condition is
received, an internal write cycle will begin (
Figure 6-2
).
6.3
Write Protection
The WP pin allows the user to write-protect the entire
array (00-7F) when the pin is tied to V
CC
. If tied to V
SS
,
the write protection is disabled.
FIGURE 6-1:
BYTE WRITE
Note:
Page write operations are limited to writ-
ing bytes within a single physical page
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size
(or ‘page size’) and end at addresses that
are integer multiples of page size – 1. If a
page write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page, as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
S
P
Bus Activity
Master
SDA Line
Bus Activity
S
T
A
R
T
S
T
O
P
Control
Byte
Word
Address
Data
A
C
K
A
C
K
A
C
K
1 0
1 0 x x x 0
x = “don’t care”
Block
Select
Bits
24AA01/24LC01B/24FC01
DS20001711K-page 10
2009-2018 Microchip Technology Inc.
FIGURE 6-2:
PAGE WRITE
S
P
Bus Activity
Master
SDA Line
Bus Activity
S
T
A
R
T
Control
Byte
Word
Address (n)
Data (n)
Data (n + 7)
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Data (n + 1)
x = “don’t care”
1 0 1 0 x x x 0
Block
Select
Bits