2008-2011 Microchip Technology Inc.
DS22100F-page 1
23A256/23K256
Device Selection Table
Features:
• Max. Clock 20 MHz
• Low-Power CMOS Technology:
- Read Current: 3 mA at 1 MHz
- Standby Current: 4
A Max. at +85°C
• 32,768 x 8-bit Organization
• 32-Byte Page
• HOLD pin
• Flexible Operating modes:
- Byte read and write
- Page mode (32 Byte Page)
- Sequential mode
• Sequential Read/Write
• High Reliability
• Temperature Ranges Supported:
• Pb-Free and RoHS Compliant, Halogen Free
Pin Function Table
Description:
The Microchip Technology Inc. 23X256 are 256 Kbit
Serial SRAM devices. The memory is accessed via a
simple Serial Peripheral Interface (SPI) compatible
serial bus. The bus signals required are a clock input
(SCK) plus separate data in (SI) and data out (SO)
lines. Access to the device is controlled through a Chip
Select (CS) input.
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused,
transitions on its inputs will be ignored, with the
exception of Chip Select, allowing the host to service
higher priority interrupts.
The 23X256 is available in standard packages
including 8-lead PDIP and SOIC, and advanced
packaging including 8-lead TSSOP.
Package Types (not to scale)
Part Number
V
CC
Range
Page Size
Temp. Ranges
Packages
23K256
2.7-3.6V
32 Byte
I, E
P, SN, ST
23A256
1.5-1.95V
32 Byte
I
P, SN, ST
- Industrial (I):
- Automotive (E):
-40
C
-40
C
to
to
+85
C
+125
C
Name
Function
CS
Chip Select Input
SO
Serial Data Output
V
SS
Ground
SI
Serial Data Input
SCK
Serial Clock Input
HOLD
Hold Input
V
CC
Supply Voltage
CS
SO
NC
V
SS
1
2
3
4
8
7
6
5
V
CC
HOLD
SCK
SI
PDIP/SOIC/TSSOP
(P, SN, ST)
256K SPI Bus Low-Power Serial SRAM
23A256/23K256
DS22100F-page 2
2008-2011 Microchip Technology Inc.
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
V
CC
.............................................................................................................................................................................4.5V
All inputs and outputs w.r.t. V
SS
......................................................................................................... -0.3V to V
CC
+0.3V
Storage temperature .................................................................................................................................-65°C to 150°C
Ambient temperature under bias ...............................................................................................................-40°C to 125°C
ESD protection on all pins ...........................................................................................................................................2kV
TABLE 1-1:
DC CHARACTERISTICS
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability.
DC CHARACTERISTICS
Industrial (I):
T
A
= -40°C to +85°C
Automotive (E): T
A
= -40°C to +125°C
Param.
No.
Sym.
Characteristic
Min.
Typ
(1)
Max.
Units
Test Conditions
D001
V
CC
Supply voltage
1.5
—
1.95
V
23A256 (I-Temp)
D001
V
CC
Supply voltage
2.7
—
3.6
V
23K256 (I,E-Temp)
D002
V
IH
High-level input
voltage
.7 V
CC
—
V
CC
+0.3
V
D003
V
IL
Low-level input
voltage
-0.3
—
0.2xV
CC
0.15xV
CC
V
V
23K256 (E-Temp)
D004
V
OL
Low-level output
voltage
—
—
0.2
V
I
OL
= 1 mA
D005
V
OH
High-level output
voltage
V
CC
-0.5
—
—
V
I
OH
= -400
A
D006
I
LI
Input leakage
current
—
—
±0.5
A
CS = V
CC
, V
IN
= V
SS
OR
V
CC
D007
I
LO
Output leakage
current
—
—
±0.5
A
CS = V
CC
, V
OUT
= V
SS
OR
V
CC
D008
I
CC
Read
Operating current
—
—
—
—
—
—
3
6
10
mA
mA
mA
F
CLK
= 1 MHz; SO = O
F
CLK
= 10 MHz; SO = O
F
CLK
= 20 MHz; SO = O
D009
I
CCS
Standby current
—
—
—
0.2
1
5
1
4
10
A
A
A
CS = V
CC
= 1.8V, Inputs tied to V
CC
or V
SS
CS = V
CC
= 3.6V, Inputs tied to V
CC
or V
SS
CS = V
CC
= 3.6V, Inputs tied to V
CC
or V
SS
@ 125°C
D010
C
INT
Input capacitance
7
pF
V
CC
= 0V, f = 1 MHz, Ta = 25°C
(
Note 1
)
D011
V
DR
RAM data retention
voltage
(2)
—
1.2
—
V
Note 1:
This parameter is periodically sampled and not 100% tested. Typical measurements taken at room
temperature (25°C).
2:
This is the limit to which V
DD
can be lowered without losing RAM data. This parameter is periodically
sampled and not 100% tested.
2008-2011 Microchip Technology Inc.
DS22100F-page 3
23A256/23K256
TABLE 1-2:
AC CHARACTERISTICS
AC CHARACTERISTICS
Industrial (I):
T
A
= -40°C to +85°C
Automotive (E): T
A
= -40°C to +125°C
Param.
No.
Sym.
Characteristic
Min.
Max.
Units
Test Conditions
1
F
CLK
Clock frequency
—
—
—
—
10
16
16
20
MHz
MHz
MHz
MHz
V
CC
1.5V (I-Temp)
V
CC
1.8V (I-Temp)
V
CC
3.0V (E-Temp)
V
CC
3.0V (I-Temp)
2
T
CSS
CS setup time
50
32
32
25
—
—
—
—
ns
ns
ns
ns
V
CC
1.5V (I-Temp)
V
CC
1.8V (I-Temp)
V
CC
3.0V (E-Temp)
V
CC
3.0V (I-Temp)
3
T
CSH
CS hold time
50
50
50
50
—
—
—
—
ns
ns
ns
ns
V
CC
1.5V (I-Temp)
V
CC
1.8V (I-Temp)
V
CC
3.0V (E-Temp)
V
CC
3.0V (I-Temp)
4
T
CSD
CS disable time
50
32
32
25
—
—
—
—
ns
ns
ns
ns
V
CC
1.5V (I-Temp)
V
CC
1.8V (I-Temp)
V
CC
3.0V (E-Temp)
V
CC
3.0V (I-Temp)
5
Tsu
Data setup time
10
10
10
10
—
—
—
—
ns
ns
ns
ns
V
CC
1.5V (I-Temp)
V
CC
1.8V (I-Temp)
V
CC
3.0V (E-Temp)
V
CC
3.0V (I-Temp)
6
T
HD
Data hold time
10
10
10
10
—
—
—
—
ns
ns
ns
ns
V
CC
1.5V (I-Temp)
V
CC
1.8V (I-Temp)
V
CC
3.0V (E-Temp)
V
CC
3.0V (I-Temp)
7
T
R
CLK rise time
—
2
us
Note 1
8
T
F
CLK fall time
—
2
us
Note 1
9
T
HI
Clock high time
50
32
32
25
—
—
—
—
ns
ns
ns
ns
V
CC
1.5V (I-Temp)
V
CC
1.8V (I-Temp)
V
CC
3.0V (E-Temp)
V
CC
3.0V (I-Temp)
10
T
LO
Clock low time
50
32
32
25
—
—
—
—
ns
ns
ns
ns
V
CC
1.5V (I-Temp)
V
CC
1.8V (I-Temp)
V
CC
3.0V (E-Temp)
V
CC
3.0V (I-Temp)
11
T
CLD
Clock delay time
50
32
32
25
—
—
—
—
ns
ns
ns
ns
V
CC
1.5V (I-Temp)
V
CC
1.8V (I-Temp)
V
CC
3.0V (E-Temp)
V
CC
3.0V (I-Temp)
12
T
V
Output valid from clock low
—
—
—
—
50
32
32
25
ns
ns
ns
ns
V
CC
1.5V (I-Temp)
V
CC
1.8V (I-Temp)
V
CC
3.0V (E-Temp)
V
CC
3.0V (I-Temp)
13
T
HO
Output hold time
0
—
ns
Note 1
Note 1:
This parameter is periodically sampled and not 100% tested.
23A256/23K256
DS22100F-page 4
2008-2011 Microchip Technology Inc.
TABLE 1-3:
AC TEST CONDITIONS
14
T
DIS
Output disable time
—
—
—
—
20
20
20
20
ns
ns
ns
ns
V
CC
1.5V (I-Temp)
V
CC
1.8V (I-Temp)
V
CC
3.0V (E-Temp)
V
CC
3.0V (I-Temp)
15
T
HS
HOLD setup time
10
—
ns
—
16
T
HH
HOLD hold time
10
—
ns
—
17
T
HZ
HOLD low to output High-Z
10
—
ns
—
18
T
HV
HOLD high to output valid
—
50
ns
—
TABLE 1-2:
AC CHARACTERISTICS (CONTINUED)
AC CHARACTERISTICS
Industrial (I):
T
A
= -40°C to +85°C
Automotive (E): T
A
= -40°C to +125°C
Param.
No.
Sym.
Characteristic
Min.
Max.
Units
Test Conditions
Note 1:
This parameter is periodically sampled and not 100% tested.
AC Waveform:
Input pulse level
0.1 V
CC
to 0.9 V
CC
Input rise/fall time
5 ns
Operating temperature
-40°C to +125°C
C
L
= 100 pF
—
Timing Measurement Reference Level:
Input
0.5 V
CC
Output
0.5 V
CC
2008-2011 Microchip Technology Inc.
DS22100F-page 5
23A256/23K256
FIGURE 1-1:
HOLD TIMING
FIGURE 1-2:
SERIAL INPUT TIMING
FIGURE 1-3:
SERIAL OUTPUT TIMING
CS
SCK
SO
SI
HOLD
16
15
15
16
17
17
Don’t Care
5
High-Impedance
n + 2
n + 1
n
n - 1
n
n + 2
n + 1
n
n
n - 1
CS
SCK
SI
SO
6
5
8
7
11
3
LSB in
MSB in
High-Impedance
2
4
CS
SCK
SO
10
9
12
MSB out
LSB out
3
14
Don’t Care
SI
13
23A256/23K256
DS22100F-page 6
2008-2011 Microchip Technology Inc.
2.0
FUNCTIONAL DESCRIPTION
2.1
Principles of Operation
The 23X256 is a 32,768-byte Serial SRAM designed to
interface directly with the Serial Peripheral Interface
(SPI) port of many of today’s popular microcontroller
families, including Microchip’s PIC
®
microcontrollers. It
may also interface with microcontrollers that do not
have a built-in SPI port by using discrete I/O lines
programmed properly in firmware to match the SPI
protocol.
The 23X256 contains an 8-bit instruction register. The
device is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. The CS pin must
be low and the HOLD pin must be high for the entire
operation.
Table 2-1
contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses and data are transferred MSB first, LSB last.
Data (SI) is sampled on the first rising edge of SCK
after CS goes low. If the clock line is shared with other
peripheral devices on the SPI bus, the user can assert
the HOLD input and place the 23X256 in ‘HOLD’ mode.
After releasing the HOLD pin, operation will resume
from the point when the HOLD was asserted.
2.2
Modes of Operation
The 23A256/23K256 has three modes of operation that
are selected by setting bits 7 and 6 in the STATUS
register. The modes of operation are Byte, Page and
Burst.
Byte Operation – is selected when bits 7 and 6 in the
STATUS register are set to 00. In this mode, the read/
write operations are limited to only one byte. The
Command followed by the 16-bit address is clocked into
the device and the data to/from the device is transferred
on the next 8 clocks (
Figure 2-1
,
Figure 2-2
).
Page Operation – is selected when bits 7 and 6 in the
STATUS register are set to 10. The 23A256/23K256 has
1024 pages of 32 Bytes. In this mode, the read and write
operations are limited to within the addressed page (the
address is automatically incremented internally). If the
data being read or written reaches the page boundary,
then the internal address counter will increment to the
start of the page (
Figure 2-3
,
Figure 2-4
).
Sequential Operation – is selected when bits 7 and 6
in the STATUS register are set to 01. Sequential opera-
tion allows the entire array to be written to and read
from. The internal address counter is automatically
incremented and page boundaries are ignored. When
the internal address counter reaches the end of the
array, the address counter will roll over to 0x0000
(
Figure 2-5
,
Figure 2-6
).
2.3
Read Sequence
The device is selected by pulling CS low. The 8-bit
READ instruction is transmitted to the 23X256 followed
by the 16-bit address, with the first MSB of the address
being a “don’t care” bit. After the correct READ
instruction and address are sent, the data stored in the
memory at the selected address is shifted out on the
SO pin.
If operating in Page mode, after the first byte of data is
shifted out, the next memory location on the page can
be read out by continuing to provide clock pulses. This
allows for 32 consecutive address reads. After the
32nd address read the internal address counter wraps
back to the byte 0 address in that page.
If operating in Sequential mode, the data stored in the
memory at the next address can be read sequentially
by continuing to provide clock pulses. The internal
Address Pointer is automatically incremented to the
next higher address after each byte of data is shifted
out. When the highest address is reached (7FFFh),
the address counter rolls over to address 0000h,
allowing the read cycle to be continued indefinitely.
The read operation is terminated by raising the CS pin
(
Figure 2-1
).
2.4
Write Sequence
Prior to any attempt to write data to the 23X256, the
device must be selected by bringing CS low.
Once the device is selected, the Write command can
be started by issuing a WRITE instruction, followed by
the 16-bit address, with the first MSB of the address
being a “don’t care” bit, and then the data to be written.
A write is terminated by the CS being brought high.
If operating in Page mode, after the initial data byte is
shifted in, additional bytes can be shifted into the
device. The Address Pointer is automatically
incremented. This operation can continue for the entire
page (32 Bytes) before data will start to be overwritten.
If operating in Sequential mode, after the initial data
byte is shifted in, additional bytes can be clocked into
the device. The internal Address Pointer is automati-
cally incremented. When the Address Pointer reaches
the highest address (7FFFh), the address counter rolls
over to (0000h). This allows the operation to continue
indefinitely, however, previous data will be overwritten.
2008-2011 Microchip Technology Inc.
DS22100F-page 7
23A256/23K256
FIGURE 2-1:
BYTE READ SEQUENCE
FIGURE 2-2:
BYTE WRITE SEQUENCE
TABLE 2-1:
INSTRUCTION SET
Instruction Name
Instruction Format
Description
READ
0000 0011
Read data from memory array beginning at selected address
WRITE
0000 0010
Write data to memory array beginning at selected address
RDSR
0000 0101
Read STATUS register
WRSR
0000 0001
Write STATUS register
SO
SI
SCK
CS
0
2
3
4
5
6
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
1
0
1
0
0
0
0
0
1
15 14 13 12
2
1
0
7
6
5
4
3
2
1
0
Instruction
16-bit Address
Data Out
High-Impedance
SO
SI
CS
9 10 11
21 22 23 24 25 26 27 28 29 30 31
0
0
0
0
0
0
0
1
15 14 13 12
2
1
0 7
6
5
4
3
2
1
0
Instruction
16-bit Address
Data Byte
High-Impedance
SCK
0
2
3
4
5
6
7
1
8
23A256/23K256
DS22100F-page 8
2008-2011 Microchip Technology Inc.
FIGURE 2-3:
PAGE READ SEQUENCE
FIGURE 2-4:
PAGE WRITE SEQUENCE
7
6
5
4
3
2
1
0
Page X, Word Y
SI
CS
9 10 11
21 22 23 24 25 26 27 28 29 30 31
15 14 13 12
2
1
0
16-bit Address
SCK
0
2
3
4
5
6
7
1
8
SO
CS
7
6
5
4
3
2
1
0
Page X, Word 0
SCK
32
34 35 36 37 38 39
33
7
6
5
4
3
2
1
0
Page X, Word 31
7
6
5
4
3
2
1
0
Page X, Word Y+1
Page X, Word Y
SO
High Impedance
SI
0
1
0
0
0
0
0
1
Instruction
SI
CS
9 10 11
21 22 23 24 25 26 27 28 29 30 31
15 14 13 12
2
1
0
7
6
5
4
3
2
1
0
16-bit Address
SCK
0
2
3
4
5
6
7
1
8
CS
SI
7
6
5
4
3
2
1
0
Page X, Word 0
7
6
5
4
3
2
1
0
Page X, Word 31
7
6
5
4
3
2
1
0
Page X, Word Y+1
Page X, Word Y
Page X, Word Y
SCK
32
34 35 36 37 38 39
33
0
0
0
0
0
0
0
1
Instruction
2008-2011 Microchip Technology Inc.
DS22100F-page 9
23A256/23K256
FIGURE 2-5:
SEQUENTIAL READ SEQUENCE
SI
CS
9 10 11
21 22 23 24 25 26 27 28 29 30 31
15 14 13 12
2
1
0
7
6
5
4
3
2
1
0
Instruction
16-bit Address
Page X, Word Y
SCK
0
2
3
4
5
6
7
1
8
SO
CS
7
6
5
4
3
2
1
0
Page X+1, Word 1
SCK
7
6
5
4
3
2
1
0
Page X+1, Word 0
7
6
5
4
3
2
1
0
Page X, Word 31
SO
CS
7
6
5
4
3
2
1
0
Page X+n, Word 31
SCK
7
6
5
4
3
2
1
0
Page X+n, Word 1
7
6
5
4
3
2
1
0
Page X+1, Word 31
SO
SI
SI
0
1
0
0
0
0
0
1
23A256/23K256
DS22100F-page 10
2008-2011 Microchip Technology Inc.
FIGURE 2-6:
SEQUENTIAL WRITE SEQUENCE
SI
CS
9 10 11
21 22 23 24 25 26 27 28 29 30 31
0
0
0
0
0
0
0
1
15 14 13 12
2
1
0
7
6
5
4
3
2
1
0
Instruction
16-bit Address
Data Byte 1
SCK
0
2
3
4
5
6
7
1
8
SI
CS
41 42 43
46 47
7
6
5
4
3
2
1
0
Data Byte n
SCK
32
34 35 36 37 38 39
33
40
7
6
5
4
3
2
1
0
Data Byte 3
7
6
5
4
3
2
1
0
Data Byte 2
44 45