© 2008 Microchip Technology Inc.
DS22105A-page 1
24AA02H/24LC02BH
Device Selection Table
Features:
• Single Supply with Operation down to 1.7V for
24AA02H Devices, 2.5V for 24LC02BH Devices
• Low-Power CMOS Technology:
- Read current 1 mA, max.
- Standby current 1
μA, max. (I-temp)
• 2-Wire Serial Interface, I
2
C™ Compatible
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• Page Write Time 3 ms, typical
• Self-Timed Erase/Write Cycle
• 8-Byte Page Write Buffer
• Hardware Write-Protect for Half-Array (80h-FFh)
• ESD Protection >4,000V
• More than 1 Million Erase/Write Cycles
• Data Retention >200 Years
• Factory Programming Available
• Packages include 8-lead PDIP, SOIC, TSSOP,
TDFN, MSOP, 5-lead SOT-23 and SC-70
• Pb-Free and RoHS Compliant
• Temperature Ranges:
- Industrial (I):
-40°C to +85°C
- Automotive (E): -40°C to +125°C
Description:
The Microchip Technology Inc. 24AA02H/24LC02BH
(24XX02H*) is a 2 Kbit Electrically Erasable PROM.
The device is organized as one block of 256 x 8-bit
memory with a 2-wire serial interface. Low-voltage
design permits operation down to 1.7V, with standby
and active currents of only 1
μA and 1 mA, respec-
tively. The 24XX02H also has a page write capability for
up to 8 bytes of data. The 24XX02H is available in the
standard 8-pin PDIP, surface mount SOIC, TSSOP, 2x3
TDFN and MSOP packages, and is also available in
the 5-lead SOT-23 and SC-70 packages.
Package Types
Block Diagram
Part
Number
V
CC
Range
Max. Clock
Frequency
Temp.
Ranges
24AA02H
1.7-5.5
400 kHz
(1)
I
24LC02BH
2.5-5.5
400 kHz
I, E
Note 1:
100 kHz for V
CC
<2.5V
A0
A1
A2
V
SS
V
CC
WP
SCL
SDA
1
2
3
4
8
7
6
5
PDIP, MSOP
SOIC, TSSOP
A0
A1
A2
V
SS
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
TDFN
A0
A1
A2
V
SS
WP
SCL
SDA
V
CC
SOT-23/SC-70
1
5
4
3
SCL
Vss
SDA
WP
Vcc
2
Note:
Pins A0, A1 and A2 are not used by the 24XX02H
(no internal connections).
8
7
6
5
1
2
3
4
HV
EEPROM
Array
Page
YDEC
XDEC
Sense Amp.
Memory
Control
Logic
I/O
Control
Logic
I/O
WP
SDA
SCL
V
CC
V
SS
R/W Control
Latches
Generator
2K I
2
C
™
Serial EEPROM with Half-Array Write-Protect
24AA02H/24LC02BH
DS22105A-page 2
© 2008 Microchip Technology Inc.
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
V
CC
.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. V
SS
......................................................................................................... -0.6V to V
CC
+1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ................................................................................................-40°C to +125°C
ESD protection on all pins
......................................................................................................................................................≥ 4 kV
TABLE 1-1:
DC CHARACTERISTICS
†
NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
DC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
V
CC
= +1.7V to 5.5V
T
A
= -40°C to +85°C
Automotive (E):
V
CC
= +2.5V to 5.5V
T
A
= -40°C to +125°C
Param.
No.
Sym.
Characteristic
Min.
Max.
Units
Conditions
D1
—
A0, A1, A2, SCL, SDA
and WP pins:
—
—
—
—
D2
V
IH
High-level input voltage
0.7 V
CC
—
V
—
D3
V
IL
Low-level input voltage
—
0.3 V
CC
V
—
D4
V
HYS
Hysteresis of Schmitt
Trigger inputs
(SDA, SCL pins)
0.05 V
CC
—
V
(Note)
D5
V
OL
Low-level output voltage
—
0.40
V
I
OL
= 3.0 ma @ V
CC
= 4.5V
I
OL
= 2.1 ma @ V
CC
= 2.5V
D6
I
LI
Input leakage current
—
±1
μA
V
IN
= V
SS
or V
CC
, WP = V
SS
D7
I
LO
Output leakage current
—
±1
μA
V
OUT
= V
SS
or V
CC
D8
C
IN
,
C
OUT
Pin capacitance
(all inputs/outputs)
—
10
pF
V
CC
= 5.0V (Note)
T
A
= 25°C, f = 1 MHz
D9
I
CC
Read Operating current
—
1
mA
V
CC
= 5.5V, SCL = 400 kHz
I
CC
Write
—
3
mA
V
CC
= 5.5V
D10
I
CCS
Standby current
—
1
μA
V
CC
= 5.5V, SCL = SDA = V
CC
WP = V
SS
, A0, A1, A2 = V
SS
Note:
This parameter is periodically sampled and not 100% tested.
© 2008 Microchip Technology Inc.
DS22105A-page 3
24AA02H/24LC02BH
TABLE 1-2:
AC CHARACTERISTICS
AC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
V
CC
= +1.7V to 5.5V
T
A
= -40°C to +85°C
Automotive (E):
V
CC
= +2.5V to 5.5V
T
A
= -40°C to +125°C
Param.
No.
Symbol
Characteristic
Min.
Max.
Units
Conditions
1
F
CLK
Clock frequency
—
—
100
400
kHz
1.7V
≤ V
CC
< 2.5V
2.5V
≤ V
CC
≤ 5.5V
2
T
HIGH
Clock high time
4000
600
—
—
ns
1.7V
≤ V
CC
< 2.5V
2.5V
≤ V
CC
≤ 5.5V
3
T
LOW
Clock low time
4700
1300
—
—
ns
1.7V
≤ V
CC
< 2.5V
2.5V
≤ V
CC
≤ 5.5V
4
T
R
SDA and SCL rise time
(Note 1)
—
—
1000
300
ns
1.7V
≤ V
CC
< 2.5V
2.5V
≤ V
CC
≤ 5.5V
5
T
F
SDA and SCL fall time
(Note 1)
—
—
1000
300
ns
1.7V
≤ V
CC
< 2.5V
2.5V
≤ V
CC
≤ 5.5V
6
T
HD
:
STA
Start condition hold time
4000
600
—
—
ns
1.7V
≤ V
CC
< 2.5V
2.5V
≤ V
CC
≤ 5.5V
7
T
SU
:
STA
Start condition setup time
4700
600
—
—
ns
1.7V
≤ V
CC
< 2.5V
2.5V
≤ V
CC
≤ 5.5V
8
T
HD
:
DAT
Data input hold time
0
—
ns
(Note 2)
9
T
SU
:
DAT
Data input setup time
250
100
—
—
ns
1.7V
≤ V
CC
< 2.5V
2.5V
≤ V
CC
≤ 5.5V
10
T
SU
:
STO
Stop condition setup time
4000
600
—
—
ns
1.7V
≤ V
CC
< 2.5V
2.5V
≤ V
CC
≤ 5.5V
11
T
SU
:
WP
WP setup time
4000
600
—
—
ns
1.7V
≤ V
CC
< 2.5V
2.5V
≤ V
CC
≤ 5.5V
12
T
HD
:
WP
WP hold time
4700
600
—
—
ns
1.7V
≤ V
CC
< 2.5V
2.5V
≤ V
CC
≤ 5.5V
13
T
AA
Output valid from clock
(Note 2)
—
—
3500
900
ns
1.7V
≤ V
CC
< 2.5V
2.5V
≤ V
CC
≤ 5.5V
14
T
BUF
Bus free time: Time the bus
must be free before a new
transmission can start
1300
4700
—
—
ns
1.7V
≤ V
CC
< 2.5V
2.5V
≤ V
CC
≤ 5.5V
16
T
SP
Input filter spike suppression
(SDA and SCL pins)
—
50
ns
(Note 1 and Note 3)
17
T
WC
Write cycle time (byte or
page)
—
5
ms
—
18
—
Endurance
1M
—
cycles
25°C, V
CC
= 5.5V, Block mode
(Note 4)
Note 1: Not 100% tested. C
B
= total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined T
SP
and V
HYS
specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a T
I
specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site
at www.microchip.com.
24AA02H/24LC02BH
DS22105A-page 4
© 2008 Microchip Technology Inc.
FIGURE 1-1:
BUS TIMING DATA
(unprotected)
(protected)
SCL
SDA
In
SDA
Out
WP
5
7
6
16
3
2
8
9
13
D4
4
10
11
12
14
© 2008 Microchip Technology Inc.
DS22105A-page 5
24AA02H/24LC02BH
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
PIN FUNCTION TABLE
2.1
A0, A1, A2
The A0, A1 and A2 pins are not used by the 24XX02H.
They may be left floating or tied to either V
SS
or V
CC
.
2.2
Serial Address/Data Input/Output
(SDA)
SDA is a bidirectional pin used to transfer addresses
and data into and out of the device. Since it is an open-
drain terminal, the SDA bus requires a pull-up resistor
to V
CC
(typical 10 k
Ω for 100 kHz, 2 kΩ for 400 kHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating Start and Stop conditions.
2.3
Serial Clock (SCL)
The SCL input is used to synchronize the data transfer
to and from the device.
2.4
Write-Protect (WP)
The WP pin must be connected to either V
SS
or V
CC
.
If tied to V
SS
, normal memory operation is enabled
(read/write the entire memory
00-FF
).
If tied to V
CC
, write operations are inhibited. Half of the
memory will be write-protected (80h-FFh). Read
operations are not affected.
Name
PDIP
SOIC
TSSOP
DFN
MSOP
SOT23
SC-70
Description
A0
1
1
1
1
1
—
—
Not Connected
A1
2
2
2
2
2
—
—
Not Connected
A2
3
3
3
3
3
—
—
Not Connected
V
SS
4
4
4
4
4
2
2
Ground
SDA
5
5
5
5
5
3
3
Serial Address/Data I/O
SCL
6
6
6
6
6
1
1
Serial Clock
WP
7
7
7
7
7
5
5
Write-Protect Input
V
CC
8
8
8
8
8
4
4
+1.7V to 5.5V Power
Supply
24AA02H/24LC02BH
DS22105A-page 6
© 2008 Microchip Technology Inc.
3.0
FUNCTIONAL DESCRIPTION
The 24XX02H supports a bidirectional, 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, while a device
receiving data is defined as a receiver. The bus has to
be controlled by a master device which generates the
Serial Clock (SCL), controls the bus access and gener-
ates the Start and Stop conditions, while the 24XX02H
works as slave. Both master and slave can operate as
transmitter or receiver, but the master device
determines which mode is activated.
4.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1
Bus Not Busy (A)
Both data and clock lines remain high.
4.2
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
4.4
Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of data
bytes transferred between Start and Stop conditions is
determined by the master device and is, theoretically,
unlimited (although only the last sixteen will be stored
when doing a write operation). When an overwrite does
occur, it will replace data in a first-in first-out (FIFO)
fashion.
4.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the slave by not generating an Acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (24XX02H) will leave the data
line high to enable the master to generate the Stop
condition.
FIGURE 4-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
Note:
The 24XX02H does not generate any
Acknowledge bits if an internal
programming cycle is in progress.
SCL
SDA
(A)
(B)
(D)
(D)
(A)
(C)
Start
Condition
Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
© 2008 Microchip Technology Inc.
DS22105A-page 7
24AA02H/24LC02BH
4.6
Device Addressing
A control byte is the first byte received following the
Start condition from the master device. The control byte
consists of a four-bit control code. For the 24XX02H,
this is set as ‘
1010
’
binary for read and write opera-
tions. The next three bits of the control byte are “don’t
cares” for the 24XX02H.
The last bit of the control byte defines the operation to
be performed. When set to ‘
1
’, a read operation is
selected. When set to ‘
0
’, a write operation is selected.
Following the Start condition, the 24XX02H monitors
the SDA bus, checking the device type identifier being
transmitted and, upon a
‘1010’
code, the slave device
outputs an Acknowledge signal on the SDA line.
Depending on the state of the R/W bit, the 24XX02H
will select a read or write operation.
FIGURE 4-2:
CONTROL BYTE
ALLOCATION
Operation
Control
Code
Block Select
R/W
Read
1010
Block Address
1
Write
1010
Block Address
0
1
0
1
0
x
x
x
R/W ACK
Start Bit
Read/Write Bit
x = “don’t care”
S
Slave Address
Acknowledge Bit
Control Code
Block
Select
Bits
24AA02H/24LC02BH
DS22105A-page 8
© 2008 Microchip Technology Inc.
5.0
WRITE OPERATION
5.1
Byte Write
Following the Start condition from the master, the
device code (4 bits), the block address (3 bits, “don’t
cares”) and the R/W bit which is a logic low, is placed
onto the bus by the master transmitter. This indicates to
the addressed slave receiver that a byte with a word
address will follow once it has generated an Acknowl-
edge bit during the ninth clock cycle. Therefore, the
next byte transmitted by the master is the word address
and will be written into the Address Pointer of the
24XX02H. After receiving another Acknowledge signal
from the 24XX02H, the master device will transmit the
data word to be written into the addressed memory
location. The 24XX02H acknowledges again and the
master generates a Stop condition. This initiates the
internal write cycle and, during this time, the 24XX02H
will not generate Acknowledge signals (Figure 5-1).
5.2
Page Write
The write-control byte, word address and the first data
byte are transmitted to the 24XX02H in the same way
as in a byte write. However, instead of generating a Stop
condition, the master transmits up to 8 data bytes to the
24XX02H, which are temporarily stored in the on-chip
page buffer and will be written into memory once the
master has transmitted a Stop condition. Upon receipt
of each word, the four lower-order Address Pointer bits
are internally incremented by ‘
1
’. The higher-order 7
bits of the word address remain constant. If the master
should transmit more than 8 words prior to generating
the Stop condition, the address counter will roll over and
the previously received data will be overwritten. As with
the byte write operation, once the Stop condition is
received an internal write cycle will begin (Figure 5-2).
FIGURE 5-1:
BYTE WRITE
FIGURE 5-2:
PAGE WRITE
Note:
Page write operations are limited to writing
bytes within a single physical page
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size (or
‘page size’) and end at addresses that are
integer multiples of [page size – 1]. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page, as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
S
P
Bus Activity
Master
SDA Line
Bus Activity
S
T
A
R
T
S
T
O
P
Control
Byte
Word
Address
Data
A
C
K
A
C
K
A
C
K
x
= “don’t care”
1
0
1
0
x
x
x
0
Block
Select
Bits
S
P
Bus Activity
Master
SDA Line
Bus Activity
S
T
A
R
T
Control
Byte
Word
Address (n)
Data (n)
Data (n + 7)
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Data (n + 1)
x
= don’t care
Block
Select
Bits
1 0 1 0 x x x 0
© 2008 Microchip Technology Inc.
DS22105A-page 9
24AA02H/24LC02BH
6.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally-timed write cycle and ACK polling
can then be initiated immediately. This involves the
master sending a Start condition followed by the control
byte for a Write command (R/W =
0
). If the device is still
busy with the write cycle, no ACK will be returned. If the
cycle is complete, the device will return the ACK and
the master can then proceed with the next Read or
Write command. See Figure 6-1 for a flow diagram of
this operation.
FIGURE 6-1:
ACKNOWLEDGE
POLLING FLOW
7.0
WRITE PROTECTION
The WP pin allows the user to write-protect half of the
array (80h-FFh) when the pin is tied to V
CC
. If tied to
V
SS
, the write protection is disabled.
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
Next
Operation
No
Yes
24AA02H/24LC02BH
DS22105A-page 10
© 2008 Microchip Technology Inc.
8.0
READ OPERATION
Read operations are initiated in the same way as write
operations, with the exception that the R/W bit of the
slave address is set to ‘
1
’. There are three basic types
of read operations: current address read, random read
and sequential read.
8.1
Current Address Read
The 24XX02H contains an address counter that main-
tains the address of the last word accessed, internally
incremented by ‘
1
’. Therefore, if the previous access
(either a read or write operation) was to address
n
, the
next current address read operation would access data
from address
n + 1
. Upon receipt of the slave address
with R/W bit set to ‘
1
’, the 24XX02H issues an acknowl-
edge and transmits the 8-bit data word. The master will
not acknowledge the transfer, but does generate a Stop
condition, and the 24XX02H discontinues transmission
(Figure 8-1).
8.2
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is accomplished by sending the word
address to the 24XX02H as part of a write operation.
Once the word address is sent, the master generates
a Start condition following the acknowledge. This
terminates the write operation, but not before the
internal Address Pointer is set. The master then
issues the control byte again, but with the R/W bit set
to a ‘
1
’. The 24XX02H will then issue an acknowledge
and transmit the 8-bit data word. The master will not
acknowledge the transfer, but does generate a Stop
condition, and the 24XX02H will discontinue
transmission (Figure 8-2).
8.3
Sequential Read
Sequential reads are initiated in the same way as a
random read, except that once the 24XX02H transmits
the first data byte, the master issues an acknowledge
as opposed to a Stop condition in a random read. This
directs the 24XX02H to transmit the next sequentially-
addressed 8-bit word (Figure 8-3).
To provide sequential reads, the 24XX02H contains an
internal Address Pointer that is incremented by one
upon completion of each operation. This Address
Pointer allows the entire memory contents to be serially
read during one operation.
8.4
Noise Protection
The 24XX02H employs a V
CC
threshold detector circuit
which disables the internal erase/write logic if the V
CC
is below 1.5V at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation, even on a noisy bus.
FIGURE 8-1:
CURRENT ADDRESS READ
S
P
Bus Activity
Master
SDA Line
Bus Activity
S
T
O
P
Control
Byte
Data (n)
A
C
K
N
o
A
C
K
S
T
A
R
T
1
0
1
0
x
x
x
1
Block
Select
Bits
x
= “don’t care”