©
2006 Microchip Technology Inc.
DS21204E-page 1
25AA040/25LC040/25C040
Device Selection Table
Features:
• Low-power CMOS technology:
- Write current: 3 mA, typical
- Read current: 500
μ
A, typical
- Standby current: 500 nA, typical
• 512 x 8-bit organization
• 16 byte page
• Write cycle time: 5 ms max.
• Self-timed Erase and Write cycles
• Block write protection:
- Protect none, 1/4, 1/2 or all of array
• Built-in write protection:
- Power on/off data protection circuitry
- Write enable latch
- Write-protect pin
• Sequential read
• High reliability:
- Endurance: 1M cycles
- Data retention: > 200 years
- ESD protection: > 4000V
• 8-pin PDIP, SOIC and TSSOP packages
• Temperature ranges supported:
Description:
The Microchip Technology Inc. 25AA040/25LC040/
25C040 (25XX040
*
) is a 4 Kbit serial Electrically
Erasable PROM. The memory is accessed via a simple
Serial Peripheral Interface (SPI) compatible serial bus.
The bus signals required are a clock input (SCK) plus
separate data in (SI) and data out (SO) lines. Access to
the device is controlled through a Chip Select (CS)
input.
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused, transi-
tions on its inputs will be ignored, with the exception of
Chip Select, allowing the host to service higher priority
interrupts. Also, write operations to the device can be
disabled via the write-protect pin (WP).
Package Types
Block Diagram
Part
Number
V
CC
Range
Max. Clock
Frequency
Temp.
Ranges
25AA040
1.8-5.5V
1 MHz
I
25LC040
2.5-5.5V
2 MHz
I
25C040
4.5-5.5V
3 MHz
I,E
- Industrial (I):
-40
°
C to +85
°
C
- Automotive (E) (25C040):
-40°C to +125°C
CS
SO
WP
V
SS
V
CC
HOLD
SCK
SI
1
2
3
4
8
7
6
5
25
X
X
0
40
CS
SO
WP
V
SS
V
CC
HOLD
SCK
SI
1
2
3
4
8
7
6
5
25
XX040
HOLD
V
CC
CS
SO
1
2
3
4
8
7
6
5
SCK
SI
V
SS
WP
25
X
X
0
40
PDIP
SOIC
TSSOP
SI
SO
SCK
CS
HOLD
WP
STATUS
Register
I/O Control
Memory
Control
Logic
HV Generator
EEPROM
Array
Page
Y Decoder
Sense Amp.
R/W Control
Logic
V
CC
V
SS
XDEC
Latches
4K SPI Bus Serial EEPROM
*25XX040 is used in this document as a generic part number
for the 25AA040/25LC040/25C040 devices.
Not recommended for new designs –
Please use 25AA040A or 25LC040A.
25AA040/25LC040/25C040
DS21204E-page 2
©
2006 Microchip Technology Inc.
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
V
CC
.............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. V
SS
.......................................................................................................... -0.6V to V
CC
+1.0V
Storage temperature .................................................................................................................................-65°C to 150°C
Ambient temperature under bias ...............................................................................................................-65°C to 125°C
ESD protection on all pins ......................................................................................................................................... 4 KV
TABLE 1-1:
DC CHARACTERISTICS
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability
DC CHARACTERISTICS
Industrial (I):
T
A
= -40°C to +85°C
V
CC
= 1.8V to 5.5V
Automotive (E): T
A
= -40°C to +125°C V
CC
= 4.5V to 5.5V (25C040 only)
Param.
No.
Sym.
Characteristic
Min.
Max.
Units
Test Conditions
D001
V
IH
1
High-level input
voltage
2.0
V
CC
+1
V
V
CC
≥
2.7V (Note)
D002
V
IH
2
0.7 V
CC
V
CC
+1
V
V
CC
< 2.7V (Note)
D003
V
IL
1
Low-level input
voltage
-0.3
0.8
V
V
CC
≥
2.7V (Note)
D004
V
IL
2
-0.3
0.3 V
CC
V
V
CC
< 2.7V (Note)
D005
V
OL
Low-level output
voltage
—
0.4
V
I
OL
= 2.1 mA
D006
V
OL
—
0.2
V
I
OL
= 1.0 mA, V
CC
< 2.5V
D007
V
OH
High-level output
voltage
V
CC
-0.5
—
V
I
OH
=-400
μ
A
D008
I
LI
Input leakage current
—
±1
μ
A
CS = V
CC
, V
IN
= V
SS
TO
V
CC
D009
I
LO
Output leakage
current
—
±1
μ
A
CS = V
CC
, V
OUT
= V
SS
TO
V
CC
D010
C
INT
Internal Capacitance
(all inputs and
outputs)
—
7
pF
T
A
= 25°C, CLK = 1.0 MHz,
V
CC
= 5.0V (Note)
D011
I
CC
Read Operating Current
—
—
1
500
mA
μ
A
V
CC
= 5.5V; F
CLK
= 3.0 MHz; SO = Open
V
CC
= 2.5V; F
CLK
= 2.0 MHz; SO = Open
D012
I
CC
Write
—
—
5
3
mA
mA
V
CC
= 5.5V
V
CC
= 2.5V
D013
I
CCS
Standby Current
—
—
5
1
μ
A
μ
A
CS = V
CC
= 5.5V, Inputs tied to V
CC
or
V
SS
CS = V
CC
= 2.5V, Inputs tied to V
CC
or
V
SS
Note:
This parameter is periodically sampled and not 100% tested.
©
2006 Microchip Technology Inc.
DS21204E-page 3
25AA040/25LC040/25C040
TABLE 1-2:
AC CHARACTERISTICS
AC CHARACTERISTICS
Industrial (I):
T
A
= -40°C to +85°C
V
CC
= 1.8V to 5.5V
Automotive (E):
T
A
= -40°C to +125°C
V
CC
= 4.5V to 5.5V (25C040 only)
Param
No.
Sym.
Characteristic
Min.
Max.
Units
Test Conditions
1
F
CLK
Clock Frequency
—
—
—
3
2
1
MHz
MHz
MHz
V
CC
= 4.5V to 5.5V
V
CC
= 2.5V to 4.5V
V
CC
= 1.8V to 2.5V
2
T
CSS
CS Setup Time
100
250
500
—
—
—
ns
ns
ns
V
CC
= 4.5V to 5.5V
V
CC
= 2.5V to 4.5V
V
CC
= 1.8V to 2.5V
3
T
CSH
CS Hold Time
150
250
475
—
—
—
ns
ns
ns
V
CC
= 4.5V to 5.5V
V
CC
= 2.5V to 4.5V
V
CC
= 1.8V to 2.5V
4
T
CSD
CS Disable Time
500
—
ns
—
5
T
SU
Data Setup Time
30
50
50
—
—
—
ns
ns
ns
V
CC
= 4.5V to 5.5V
V
CC
= 2.5V to 4.5V
V
CC
= 1.8V to 2.5V
6
T
HD
Data Hold Time
50
100
100
—
—
—
ns
ns
ns
V
CC
= 4.5V to 5.5V
V
CC
= 2.5V to 4.5V
V
CC
= 1.8V to 2.5V
7
T
R
CLK Rise Time
—
2
μ
s
(Note 1)
8
T
F
CLK Fall Time
—
2
μ
s
(Note 1)
9
T
HI
Clock High Time
150
230
475
—
—
—
ns
ns
ns
V
CC
= 4.5V to 5.5V
V
CC
= 2.5V to 4.5V
V
CC
= 1.8V to 2.5V
10
T
LO
Clock Low Time
150
230
475
—
—
—
ns
ns
ns
V
CC
= 4.5V to 5.5V
V
CC
= 2.5V to 4.5V
V
CC
= 1.8V to 2.5V
11
T
CLD
Clock Delay Time
50
—
ns
—
12
T
CLE
Clock Enable Time
50
—
ns
—
13
T
V
Output Valid from Clock Low
—
—
—
150
230
475
ns
ns
ns
V
CC
= 4.5V to 5.5V
V
CC
= 2.5V to 4.5V
V
CC
= 1.8V to 2.5V
14
T
HO
Output Hold Time
0
—
ns
(Note 1)
15
T
DIS
Output Disable Time
—
—
—
200
250
500
ns
ns
ns
V
CC
= 4.5V to 5.5V (Note 1)
V
CC
= 2.5V to 4.5V (Note 1)
V
CC
= 1.8V to 2.5V (Note 1)
16
T
HS
HOLD Setup Time
100
100
200
—
—
—
ns
ns
ns
V
CC
= 4.5V to 5.5V
V
CC
= 2.5V to 4.5V
V
CC
= 1.8V to 2.5V
17
T
HH
HOLD Hold Time
100
100
200
—
—
—
ns
ns
ns
V
CC
= 4.5V to 5.5V
V
CC
= 2.5V to 4.5V
V
CC
= 1.8V to 2.5V
18
T
HZ
HOLD Low to Output High-Z
100
150
200
—
—
—
ns
ns
ns
V
CC
= 4.5V to 5.5V (Note 1)
V
CC
= 2.5V to 4.5V (Note 1)
V
CC
= 1.8V to 2.5V (Note 1)
19
T
HV
HOLD High to Output Valid
100
150
200
—
—
—
ns
ns
ns
V
CC
= 4.5V to 5.5V
V
CC
= 2.5V to 4.5V
V
CC
= 1.8V to 2.5V
20
T
WC
Internal Write Cycle Time
—
5
ms
—
21
—
Endurance
1M
—
E/W
Cycles
(Note 2)
Note 1:
This parameter is periodically sampled and not 100% tested.
2:
This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please
consult the Total Endurance™ Model which can be obtained from our web site: www.microchip.com.
25AA040/25LC040/25C040
DS21204E-page 4
©
2006 Microchip Technology Inc.
FIGURE 1-1:
HOLD TIMING
FIGURE 1-2:
SERIAL INPUT TIMING
FIGURE 1-3:
SERIAL OUTPUT TIMING
CS
SCK
SO
SI
HOLD
17
16
16
17
19
18
Don’t Care
5
High-impedance
n + 2
n + 1
n
n - 1
n
n + 2
n + 1
n
n
n - 1
CS
SCK
SI
SO
6
5
8
7
11
3
LSB in
MSB in
High-impedance
12
Mode 1,1
Mode 0,0
2
4
CS
SCK
SO
10
9
13
MSB out
ISB out
3
15
Don’t Care
SI
Mode 1,1
Mode 0,0
14
©
2006 Microchip Technology Inc.
DS21204E-page 5
25AA040/25LC040/25C040
TABLE 1-3:
AC TEST CONDITIONS
FIGURE 1-4:
AC TEST CIRCUIT AC
AC Waveform:
V
LO
= 0.2V
—
V
H I
= V
CC
- 0.2V
(Note 1)
V
H I
= 4.0V
(Note 2)
Timing Measurement Reference Level
Input
0.5 V
CC
Output
0.5 V
CC
Note 1: For V
CC
≤
4.0V
2: For V
CC
> 4.0V
V
CC
SO
100 pF
1.8 K
Ω
2.25 K
Ω
25AA040/25LC040/25C040
DS21204E-page 6
©
2006 Microchip Technology Inc.
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
PIN FUNCTION TABLE
2.1
Chip Select (CS)
A low level on this pin selects the device. A high level
deselects the device and forces it into Standby mode.
However, a programming cycle which is already
initiated or in progress will be completed, regardless of
the CS input signal. If CS is brought high during a
program cycle, the device will go in Standby mode as
soon as the programming cycle is complete. When the
device is deselected, SO goes into the high-impedance
state, allowing multiple parts to share the same SPI
bus. A low-to-high transition on CS after a valid write
sequence initiates an internal write cycle. After power-
up, a low level on CS is required prior to any sequence
being initiated.
2.2
Serial Output (SO)
The SO pin is used to transfer data out of the 25XX040.
During a read cycle, data is shifted out on this pin after
the falling edge of the serial clock.
2.3
Write-Protect (WP)
This pin is a hardware write-protect input pin. When
WP is low, all writes to the array or STATUS register
are disabled, but any other operation functions
normally. When WP is high, all functions, including
nonvolatile writes operate normally. WP going low at
any time will reset the write enable latch and inhibit
programming, except when an internal write has
already begun. If an internal write cycle has already
begun, WP going low will have no effect on the write.
See Table 3-3 for Write-Protect Functionality Matrix.
2.4
Serial Input (SI)
The SI pin is used to transfer data into the device. It
receives instructions, addresses and data. Data is
latched on the rising edge of the serial clock.
2.5
Serial Clock (SCK)
The SCK is used to synchronize the communication
between a master and the 25XX040. Instructions,
addresses or data present on the SI pin are latched on
the rising edge of the clock input, while data on the SO
pin is updated after the falling edge of the clock input.
2.6
Hold (HOLD)
The HOLD pin is used to suspend transmission to the
25XX040 while in the middle of a serial sequence
without having to retransmit the entire sequence again
at a later time. It must be held high any time this func-
tion is not being used. Once the device is selected and
a serial sequence is underway, the HOLD pin may be
pulled low to pause further serial communication
without resetting the serial sequence. The HOLD pin
must be brought low while SCK is low, otherwise the
HOLD function will not be invoked until the next SCK
high-to-low transition. The 25XX040 must remain
selected during this sequence. The SI, SCK and SO
pins are in a high-impedance state during the time the
part is paused and transitions on these pins will be
ignored. To resume serial communication, HOLD must
be brought high while the SCK pin is low, otherwise
serial communication will not resume. Lowering the
HOLD line at any time will tri-state the SO line.
Name
PDIP
SOIC
TSSOP
Description
CS
1
1
3
Chip Select Input
SO
2
2
4
Serial Data Output
WP
3
3
5
Write-Protect Pin
V
SS
4
4
6
Ground
SI
5
5
7
Serial Data Input
SCK
6
6
8
Serial Clock Input
HOLD
7
7
1
Hold Input
V
CC
8
8
2
Supply Voltage
©
2006 Microchip Technology Inc.
DS21204E-page 7
25AA040/25LC040/25C040
3.0
FUNCTIONAL DESCRIPTION
3.1
Principles of Operation
The 25XX040 is a 512 byte Serial EEPROM designed
to interface directly with the Serial Peripheral Interface
(SPI) port of many of today’s popular microcontroller
families, including Microchip’s PIC16C6X/7X micro-
controllers. It may also interface with microcontrollers
that do not have a built-in SPI port by using discrete
I/O lines programmed properly with the software.
The 25XX040 contains an 8-bit instruction register. The
part is accessed via the SI pin, with data being clocked
in on the rising edge of SCK. The CS pin must be low
and the HOLD pin must be high for the entire operation.
The WP pin must be held high to allow writing to the
memory array.
Table 3-1 contains a list of the possible instruction
bytes and format for device operation. The Most
Significant address bit (A8) is located in the instruction
byte. All instructions, addresses, and data are
transferred MSB first, LSB last.
Data is sampled on the first rising edge of SCK after CS
goes low. If the clock line is shared with other periph-
eral devices on the SPI bus, the user can assert the
HOLD input and place the 25XX040 in ‘HOLD’ mode.
After releasing the HOLD pin, operation will resume
from the point when the HOLD was asserted.
3.2
Read Sequence
The part is selected by pulling CS low. The 8-bit
READ
instruction with the A8 address bit is transmitted to the
25XX040 followed by the lower 8-bit address (A7
through A0). After the correct
READ
instruction and
address are sent, the data stored in the memory at the
selected address is shifted out on the SO pin. The data
stored in the memory at the next address can be read
sequentially by continuing to provide clock pulses. The
internal Address Pointer is automatically incremented
to the next higher address after each byte of data is
shifted out. When the highest address is reached
(01FFh), the address counter rolls over to address
0000h allowing the read cycle to be continued
indefinitely. The read operation is terminated by raising
the CS pin (Figure 3-1).
3.3
Write Sequence
Prior to any attempt to write data to the 25XX040, the
write enable latch must be set by issuing the
WREN
instruction (Figure 3-4). This is done by setting CS low
and then clocking out the proper instruction into the
25XX040. After all eight bits of the instruction are
transmitted, the CS must be brought high to set the
write enable latch. If the write operation is initiated
immediately after the
WREN
instruction without CS
being brought high, the data will not be written to the
array because the write enable latch will not have been
properly set.
Once the write enable latch is set, the user may
proceed by setting the CS low, issuing a
WRITE
instruction, followed by the address, and then the data
to be written. Keep in mind that the Most Significant
address bit (A8) is included in the instruction byte. Up
to 16 bytes of data can be sent to the 25XX040 before
a write cycle is necessary. The only restriction is that all
of the bytes must reside in the same page. A page
address begins with
XXXX
0000
and ends with
XXXX
1111
. If the internal address counter reaches
XXXX
1111
and the clock continues, the counter will roll back
to the first address of the page and overwrite any data
in the page that may have been written.
For the data to be actually written to the array, the CS
must be brought high after the least significant bit (D0)
of the n
th
data byte has been clocked in. If CS is
brought high at any other time, the write operation will
not be completed. Refer to Figure 3-2 and Figure 3-3
for more detailed illustrations on the byte write
sequence and the page write sequence respectively.
While the write is in progress, the STATUS register may
be read to check the status of the WIP, WEL, BP1 and
BP0 bits (Figure 3-6). A read attempt of a memory
array location will not be possible during a write cycle.
When the write cycle is completed, the write enable
latch is reset.
TABLE 3-1:
INSTRUCTION SET
Instruction Name
Instruction Format
Description
READ
0000 A
8
011
Read data from memory array beginning at selected address
WRITE
0000 A
8
010
Write data to memory array beginning at selected address
WRDI
0000 0100
Reset the write enable latch (disable write operations)
WREN
0000 0110
Set the write enable latch (enable write operations)
RDSR
0000 0101
Read STATUS register
WRSR
0000 0001
Write STATUS register
Note:
A
8
is the 9
th
address bit necessary to fully address 512 bytes.
25AA040/25LC040/25C040
DS21204E-page 8
©
2006 Microchip Technology Inc.
FIGURE 3-1:
READ SEQUENCE
FIGURE 3-2:
BYTE WRITE SEQUENCE
FIGURE 3-3:
PAGE WRITE SEQUENCE
SO
SI
SCK
CS
0
2
3
4
5
6
7
8
9
10 11
12 13 14 15 16 17 18 19 20 21 22
1
0
1
A8
0
0
0
0
1
A7
6
5
4
1
A0
7
6
5
4
3
2
1
0
Instruction
Lower Address Byte
Data Out
High-impedance
23
3
2
Don’t Care
SO
SI
SCK
CS
0
2
3
4
5
6
7
8
9
10 11
12 13 14 15 16 17 18 19 20 21 22
1
0
0
A8
0
0
0
0
A7
6
5
4
1
A0
7
6
5
4
3
2
1
0
Instruction
Lower Address Byte
Data Byte
High-impedance
23
3
2
1
T
WC
SI
CS
9 10 11
14 15 16 17 18 19 20 21 22 23 24
0
0
A8
0
0
0
0
1
A7
6
5
4
2
1
0
7
6
5
4
3
2
1
0
Instruction
Lower Address Byte
Data Byte 1
SCK
0
2
3
4
5
6
7
1
8
SI
CS
34 35 36
39 40
7
6
5
4
3
2
1
0
Data Byte n (16 max)
SCK
25
27 28 29 30
31 32
26
33
7
6
5
4
3
2
1
0
Data Byte 3
7
6
5
4
3
2
1
0
Data Byte 2
37 38
3
13
©
2006 Microchip Technology Inc.
DS21204E-page 9
25AA040/25LC040/25C040
3.4
Write Enable (WREN) and Write
Disable (WRDI)
The 25XX040 contains a write enable latch. See
Table 3-3 for the Write-Protect Functionality Matrix.
This latch must be set before any write operation will be
completed internally. The
WREN
instruction will set the
latch, and the
WRDI
will reset the latch.
The following is a list of conditions under which the
write enable latch will be reset:
• Power-up
•
WRDI
instruction successfully executed
•
WRSR
instruction successfully executed
•
WRITE
instruction successfully executed
• WP line is low
FIGURE 3-4:
WRITE ENABLE SEQUENCE
FIGURE 3-5:
WRITE DISABLE SEQUENCE
SCK
0
2
3
4
5
6
7
1
SI
High-impedance
SO
CS
0
1
0
0
0
0
0
1
SCK
0
2
3
4
5
6
7
1
SI
High-impedance
SO
CS
0
1
0
0
0
0
0
1
0
25AA040/25LC040/25C040
DS21204E-page 10
©
2006 Microchip Technology Inc.
3.5
Read Status Register (RDSR)
The
RDSR
instruction provides access to the STATUS
register. The STATUS register may be read at any time,
even during a write cycle. The STATUS register is
formatted as follows:
The Write-In-Process (WIP) bit indicates whether the
25XX040 is busy with a write operation. When set to a
‘
1
’, a write is in progress, when set to a ‘
0
’, no write is
in progress. This bit is read-only.
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch. When set to a ‘
1
’, the latch
allows writes to the array, when set to a ‘
0
’, the latch
prohibits writes to the array. The state of this bit can
always be updated via the WREN or WRDI commands
regardless of the state of write protection on the
STATUS register. This bit is read-only.
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the
WRSR
instruction. These
bits are nonvolatile.
See Figure 3-6 for
RDSR
timing sequence.
3.6
Write Status Register (WRSR)
The
WRSR
instruction allows the user to select one of
four levels of protection for the array by writing to the
appropriate bits in the STATUS register. The array is
divided up into four segments. The user has the ability
to write-protect none, one, two, or all four of the
segments of the array. The partitioning is controlled as
illustrated in Table 3-2.
See Figure 3-7 for
WRSR
timing sequence.
TABLE 3-2:
ARRAY PROTECTION
FIGURE 3-6:
READ STATUS REGISTER SEQUENCE
FIGURE 3-7:
WRITE STATUS REGISTER SEQUENCE
7
6
5
4
3
2
1
0
X
X
X
X
BP1
BP0
WEL
WIP
BP1
BP0
Array Addresses
Write-Protected
0
0
none
0
1
upper 1/4
(0180h-01FFh)
1
0
upper 1/2
(0100h-01FFh)
1
1
all
(0000h-01FFh)
SO
SI
CS
9
10
11
12
13
14
15
1
1
0
0
0
0
0
0
7
6
5
4
2
1
0
Instruction
Data from STATUS register
High-impedance
SCK
0
2
3
4
5
6
7
1
8
3
SO
SI
CS
9
10
11
12
13
14
15
0
1
0
0
0
0
0
0
7
6
5
4
2
1
0
Instruction
Data to STATUS register
High-impedance
SCK
0
2
3
4
5
6
7
1
8
3