21130F.book

 1996-2012 Microchip Technology Inc.

DS21130F-page 1

93AA76/86

Features:

• Single supply operation down to 1.8V

• Low-power CMOS technology:

- 1 mA active current typical

- 5 

A standby current (typical) at 3.0V

• ORG pin selectable memory configuration:

- 1024 x 8 or 512 x 16-bit organization 

(93AA76)

- 2048 x 8 or 1024 x 16-bit organization 

(93AA86)

• Self-timed erase and write cycles

• Automatic ERAL before WRAL

• Power on/off data protection circuitry

• Industry standard 3-wire serial I/O

• Device status signal during erase/write cycles

• Sequential read function

• 1,000,000 erase/write cycles ensured

• Data retention > 200 years

• 8-pin PDIP/SOIC package

• Temperature ranges available:

- Commercial (C): 0

C to +70C

Description:

The Microchip Technology Inc. 93AA76/86 are 8K and
16K low voltage serial Electrically Erasable PROMs.
The device memory is configured as x8 or x16 bits
depending on the ORG pin setup. Advanced CMOS
technology makes these devices ideal for low power
nonvolatile memory applications. These devices also
have a Program Enable (PE) pin to allow the user to
write-protect the entire contents of the memory array.
The 93AA76/86 is available in standard 8-pin PDIP and
8-pin surface mount SOIC packages.

Package Types

Block Diagram

SOIC Package

PDIP Package

CS

CLK

DI

DO

V

SS

PE

V

CC

ORG

CS

CLK

DI

DO

V

CC

PE
ORG
V

SS

93
AA76

/86

93
A

A

76
/8

6

1

2

3

4

8

7

6

5

1

2

3

4

8

7

6

5

DO

CS

CLK

V

CC

V

SS

Memory

Array

Address

Decoder

Data

Register

Counter

Address

Output

Buffer

Mode

Decode

Logic

Generator

Clock

DI

PE

8K/16K 1.8V Microwire Serial EEPROM

Not recommended for new designs –

Please use 93AA76C or 93AA86C.

21130F.book  Page 1  Wednesday, December 5, 2012  2:47 PM

93AA76/86

DS21130F-page 2

 1996-2012 Microchip Technology Inc.

1.0

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

(†)

V

CC

.............................................................................................................................................................................7.0V

All inputs and outputs w.r.t. V

SS

  ........................................................................................................ -0.6V to Vcc + 1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied ................................................................................................-40°C to +125°C

Soldering temperature of leads (10 seconds) ....................................................................................................... +300°C

ESD protection on all pins .......................................................................................................................................... 4 kV

1.1

 AC Test Conditions

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.

AC Waveform:

V

LO

 = 2.0V

V

HI

 = Vcc - 0.2V

(Note 1)

V

HI

 = 4.0V for

(Note 2)

Timing Measurement Reference Level:

Input

0.5 V

CC

Output

0.5 V

CC

Note 1:

For V

CC

 4.0V

2:

For V

CC

 4.0V

21130F.book  Page 2  Wednesday, December 5, 2012  2:47 PM

 1996-2012 Microchip Technology Inc.

DS21130F-page 3

93AA76/86

TABLE 1-1:

DC CHARACTERISTICS

DC CHARACTERISTICS

Applicable over recommended operating ranges shown below unless otherwise noted:
V

CC

 = +1.8V to +6.0V

Commercial (C): T

A

  =   0°C to +70°C

Parameter

Symbol

Min.

Max.

Units

Conditions

High-level input voltage

V

IH1

2.0

V

CC

 + 1

V

V

CC

 2.7V

V

IH2

0.7 V

CC

V

CC

 + 1

V

V

CC

 < 2.7V

Low-level input voltage

V

IL1

-0.3

0.8

V

V

CC

 2.7V

V

IL2

-0.3

0.2 V

CC

V

V

CC

 < 2.7V

Low-level output voltage

V

OL1

—

0.4

V

I

OL

 = 2.1 mA; V

CC

 = 4.5V

V

OL2

—

0.2

V

I

OL

 =100 

A; V

CC

 = V

CC

 Min.

High-level output voltage

V

OH1

2.4

—

V

I

OH

 = -400 

A; V

CC

 = 4.5V

V

OH2

V

CC

-0.2

—

V

I

OH

 = -100 

A; V

CC

 = V

CC

 Min.

Input leakage current

I

LI

-10

10

A

V

IN

 = 0.1V to V

CC

Output leakage current

I

LO

-10

10

A

V

OUT

 = 0.1V to V

CC

Pin capacitance
(all inputs/outputs)

C

INT

—

7

pF

 (Note 1)
 T

A

 = +25°C, F

CLK

 = 1 MHz 

Operating current 

I

CC

 write

—

3

mA

V

CC

 = 5.5V

I

CC

 read

—

1 

500

mA

A

F

CLK

 = 3 MHz; V

CC

 = 5.5V

F

CLK

 = 1 MHz; V

CC

 = 3.0V

Standby current

I

CCS

—

100

30

A
A

CLK = CS = 0V; V

CC

 = 5.5V

CLK = CS = 0V; V

CC 

= 3.0V 

DI = PE = V

SS

ORG = V

SS

 or V

CC

Note 1:

This parameter is periodically sampled and not 100% tested.

21130F.book  Page 3  Wednesday, December 5, 2012  2:47 PM

93AA76/86

DS21130F-page 4

 1996-2012 Microchip Technology Inc.

TABLE 1-2:

AC CHARACTERISTICS

AC CHARACTERISTICS

Applicable over recommended operating ranges shown below unless otherwise noted:
V

CC

 = +1.8V to +6.0V

Commercial (C): T

A

  =   0°C to +70°C

Parameter

Symbol

Min.

Max.

Units

Conditions

Clock frequency

F

CLK

—

3
2
1

MHz
MHz

Mhz

4.5V 

V

CC  

 6.0V

2.5V 

 V

CC

 4.5V

1.8V 

V

CC 

 2.5V

Clock high time

T

CKH

200
300
500

—

ns
ns
ns

4.5V  

V

CC 

 6.0V

2.5V  

V

CC 

 4.5V

1.8V  

V

CC 

 2.5V

Clock low time

T

CKL

100
200
500

—

ns
ns
ns

4.5V  

V

CC 

 6.0V

2.5V  

V

CC 

 4.5V

1.8V 

 V

CC

 < 2.5V

Chip select setup time

T

CSS

50

100
250

—

ns
ns
ns

4.5V  

V

CC 

 6.0V, Relative to CLK

2.5V  

V

CC 

 4.5V, Relative to CLK

1.8V  

V

CC 

 2.5V, Relative to CLK

Chip select hold time

T

CSH

0

—

ns

1.8V  

V

CC 

 6.0V

Chip select low time

T

CSL

250

—

ns

1.8V  

V

CC 

 6.0V, Relative to CLK

Data input setup time

T

DIS

50

100
250

—

ns
ns
ns

4.5V  

V

CC 

 6.0V, Relative to CLK

2.5V  

V

CC

 <4.5V, Relative to CLK

1.8V  

V

CC

 < 2.5V, Relative to CLK

Data input hold time

T

DIH

50

100
250

—

ns
ns
ns

4.5V  

V

CC 

 6.0V, Relative to CLK

2.5V  

V

CC 

 4.5V, Relative to CLK

1.8V  

V

CC

 < 2.5V, Relative to CLK

Data output delay time

T

PD

—

100
250
500

ns
ns
ns

4.5V  

V

CC 

 6.0V, C

L 

= 100 pF

2.5V  

V

CC

 < 4.5V, C

L

 = 100 pF

1.8V  

V

CC

 < 2.5V, C

L

 = 100 pF

Data output disable time

T

CZ

—

100
500

ns
ns

4.5V  

V

CC 

 5.5V (Note 1)

1.8V  

 V

CC

 < 4.5V  (Note 1)

Status valid time

Tsv

—

200
300
500

ns
ns
ns

4.5V  

V

CC 

 6.0V, C

L

 = 100 pF

2.5V  

V

CC 

< 4.5V, C

L

 = 100 pF

1.8V  

V

CC 

< 2.5V, C

L

 = 100 pF

Program cycle time

T

WC

—

5

ms

Erase/Write mode

T

EC

—

15

ms

ERAL mode

T

WL

—

30

ms

WRAL mode 

Endurance

—

1M

—

cycles

25°C, V

CC

 = 5.0V, Block mode (Note 2)

Note 1:

This parameter is periodically sampled and not 100% tested.

2:

This parameter is not tested but ensured by characterization. For endurance estimates in a specific 
application, please consult the Total Endurance

™ 

Model which can be obtained from Microchip’s web site 

at: www.microchip.com

21130F.book  Page 4  Wednesday, December 5, 2012  2:47 PM

 1996-2012 Microchip Technology Inc.

DS21130F-page 5

93AA76/86

TABLE 1-3:

INSTRUCTION SET FOR 93AA76: ORG = 1 (X16 ORGANIZATION)

TABLE 1-4:

INSTRUCTION SET FOR 93AA76: ORG = 0 (X8 ORGANIZATION)

TABLE 1-5:

INSTRUCTION SET FOR 93AA86: ORG = 1 (X16 ORGANIZATION)

TABLE 1-6:

INSTRUCTION SET FOR 93AA86: ORG = 0 (X8 ORGANIZATION)

Instruction

SB

Opcode

Address

Data In 

Data Out

Req. CLK Cycles

READ

1

10

X A8 A7 A6 A5 A4 A3 A2 A1 A0

—

D15 - D0

29

EWEN

1

00

1   1   X   X   X   X   X   X   X   X

—

High-Z

13

ERASE

1

11

X A8 A7 A6 A5 A4 A3 A2 A1 A0

—

(RDY/BSY)

13

ERAL

1

00

1   0   X   X   X   X   X   X   X   X

—

(RDY/BSY)

13

WRITE

1

01

X A8 A7 A6 A5 A4 A3 A2 A1 A0

D15 - D0

(RDY/BSY)

29

WRAL

1

00

0   1   X   X   X   X   X   X   X   X

D15 - D0

(RDY/BSY)

29

EWDS

1

00

0   0   X   X   X   X   X   X   X   X

—

High-Z

13

Instruction

SB

Opcode

Address

Data In 

Data Out

Req. CLK 

Cycles

READ

1

10

X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

—

D7 - D0

22

EWEN

1

00

1   1   X   X   X   X   X   X   X   X

—

High-Z

14

ERASE

1

11

 X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

—

(RDY/BSY)

14

ERAL

1

00

1   0   X   X   X   X   X   X   X   X

—

(RDY/BSY)

14

WRITE

1

01

 X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

D7 - D0

(RDY/BSY)

22

WRAL

1

00

0   1   X   X   X   X   X   X   X   X

D7 - D0

(RDY/BSY)

22

EWDS

1

00

0   0   X   X   X   X   X   X   X   X

—

High-Z

14

Instruction

SB

Opcode

Address

Data In 

Data Out

Req. CLK Cycles

READ

1

10

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

—

D15 - D0

29

EWEN

1

00

1   1   X   X   X   X   X   X  X   X 

—

High-Z

13

ERASE

1

11

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

—

(RDY/BSY)

13

ERAL

1

00

1   0   X   X   X   X   X   X  X   X

—

(RDY/BSY)

13

WRITE

1

01

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

D15 - D0

(RDY/BSY)

29

WRAL

1

00

0   1   X   X   X   X   X   X   X   X

D15 - D0

(RDY/BSY)

29

EWDS

1

00

0   0   X   X   X   X   X   X   X   X

—

High-Z

13

Instruction

SB

Opcode

Address

Data In 

Data Out

Req. CLK Cycles

READ

1

10

A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

—

D7 - D0

22

EWEN

1

00

1    1    X    X    X    X    X    X    X    X

—

High-Z

14

ERASE

1

11

A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

—

(RDY/BSY)

14

ERAL

1

00

1    0    X    X    X    X    X    X    X    X  

—

(RDY/BSY)

14

WRITE

1

01

A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

D7 - D0

(RDY/BSY)

22

WRAL

1

00

0    1    X    X   X    X    X    X    X    X

D7 - D0

(RDY/BSY)

22

EWDS

1

00

0    0    X    X    X    X    X    X    X    X

—

High-Z

14

21130F.book  Page 5  Wednesday, December 5, 2012  2:47 PM

93AA76/86

DS21130F-page 6

 1996-2012 Microchip Technology Inc.

2.0

PRINCIPLES OF OPERATION

When the ORG pin is connected to V

CC

, the x16

organization is selected. When it is connected to ground,
the x8 organization is selected. Instructions, addresses
and write data are clocked into the DI pin on the rising
edge of the clock (CLK). The DO pin is normally held in
a high-Z state except when reading data from the
device, or when checking the Ready/Busy status during
a programming operation. The Ready/Busy status can
be verified during an erase/write operation by polling the
DO pin; DO low indicates that programming is still in
progress, while DO high indicates the device is ready.
The DO will enter the high-impedance state on the falling
edge of the CS.

2.1

Start Condition

The Start bit is detected by the device if CS and DI are
both high with respect to the positive edge of CLK for
the first time.

Before a Start condition is detected, CS, CLK and DI
may change in any combination (except to that of a
Start condition), without resulting in any device opera-
tion (Read, Write, Erase, EWEN, EWDS, ERAL and
WRAL). As soon as CS is high, the device is no longer
in the Standby mode.

An instruction following a Start condition will only be
executed if the required amount of opcode, address
and data bits for any particular instruction are clocked
in.

After execution of an instruction (i.e., clock in or out of
the last required address or data bit) CLK and DI
become “don't care” bits until a new Start condition is
detected.

2.2

DI/DO

It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero”
that precedes the read operation, if A0 is a logic high
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of A0,
the higher the voltage at the Data Out pin. 

2.3

Erase/Write Enable and Disable 
(EWEN, EWDS)

The 93AA76/86 powers up in the Erase/Write Disable
(EWDS) state. All programming modes must be
preceded by an Erase/Write Enable (EWEN) instruction.
Once the EWEN instruction is executed, programming
remains enabled until an EWDS instruction is executed
or V

CC

 is removed from the device. To protect against

accidental data disturb, the EWDS instruction can be
used to disable all erase/write functions and should
follow all programming operations. Execution of a READ
instruction is independent of both the EWEN and EWDS
instructions.

2.4

Data Protection

During power-up, all programming modes of operation
are inhibited until V

CC

 has reached a level greater than

1.4V. During power-down, the source data protection
circuitry acts to inhibit all programming modes when
V

CC

 has fallen below 1.4V.

The EWEN and EWDS commands give additional
protection against accidentally programming during
normal operation.

After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before any ERASE or WRITE instruction can
be executed.

21130F.book  Page 6  Wednesday, December 5, 2012  2:47 PM

 1996-2012 Microchip Technology Inc.

DS21130F-page 7

93AA76/86

3.0

DEVICE OPERATION

3.1

READ

The  READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 16-bit (x16 organization) or 8-bit
(x8 organization) output string. The output data bits will
toggle on the rising edge of the CLK and are stable
after the specified time delay (T

PD

). Sequential read is

possible when CS is held high and clock transitions
continue. The memory address pointer will automati-
cally increment and output data sequentially.

3.2

ERASE

The  ERASE instruction forces all data bits of the
specified address to the logical “1” state. The self-timed
programming cycle is initiated on the rising edge of
CLK as the last address bit (A0) is clocked in. At this
point, the CLK, CS and DI inputs become “don’t cares”. 

The DO pin indicates the Ready/Busy status of the
device if the CS is high. The Ready/Busy status will be
displayed on the DO pin until the next Start bit is
received as long as CS is high. Bringing the CS low will
place the device in Standby mode and cause the DO
pin to enter the high-impedance state. DO at logical “0”
indicates that programming is still in progress. DO at
logical “1” indicates that the register at the specified
address has been erased and the device is ready for
another instruction.

The erase cycle takes 3 ms per word (typical).

3.3

WRITE

The  WRITE instruction is followed by 16 bits (or by 8
bits) of data to be written into the specified address.
The self-timed programming cycle is initiated on the
rising edge of CLK as the last data bit (D0) is clocked
in. At this point, the CLK, CS and DI inputs become
“don’t cares”.

The DO pin indicates the Ready/Busy status of the
device if the CS is high. The Ready/Busy status will be
displayed on the DO pin until the next Start bit is
received as long as CS is high. Bringing the CS low will
place the device in Standby mode and cause the DO
pin to enter the high-impedance state. DO at logical “0”
indicates that programming is still in progress. DO at
logical “1” indicates that the register at the specified
address has been written and the device is ready for
another instruction.

The write cycle takes 3 ms per word (typical).

3.4

Erase All (ERAL)

The ERAL instruction will erase the entire memory array
to the logical “1” state. The ERAL cycle is identical to
the erase cycle except for the different opcode. The
ERAL cycle is completely self-timed and commences
on the rising edge of the last address bit (A0). Note that
the Least Significant 8 or 9 address bits are “don’t care”
bits, depending on selection of x16 or x8 mode.
Clocking of the CLK pin is not necessary after the
device has entered the self clocking mode. The ERAL
instruction is ensured at Vcc = +4.5V to +6.0V.

The DO pin indicates the Ready/Busy status of the
device if the CS is high. The Ready/Busy status will be
displayed on the DO pin until the next Start bit is
received as long as CS is high. Bringing the CS low will
place the device in Standby mode and cause the DO
pin to enter the high-impedance state. DO at logical “0”
indicates that programming is still in progress. DO at
logical “1” indicates that the entire device has been
erased and is ready for another instruction.

The ERAL cycle takes 15 ms maximum (8 ms typical).

3.5

Write All (WRAL)

The WRAL instruction will write the entire memory array
with the data specified in the command. The WRAL
cycle is completely self-timed and commences on the
rising edge of the last address bit (A0). Note that the
Least Significant 8 or 9 address bits are “don’t cares”,
depending on selection of x16 or x8 mode. Clocking of
the CLK pin is not necessary after the device has
entered the self clocking mode. The WRAL command
does include an automatic ERAL cycle for the device.
Therefore, the WRAL instruction does not require an
ERAL

 instruction but the chip must be in the EWEN

status. The WRAL instruction is ensured at Vcc = +4.5V
to +6.0V.

The DO pin indicates the Ready/Busy status of the
device if the CS is high. The Ready/Busy status will be
displayed on the DO pin until the next Start bit is
received as long as CS is high. Bringing the CS low will
place the device in Standby mode and cause the DO
pin to enter the high-impedance state. DO at logical “0”
indicates that programming is still in progress. DO at
logical “1” indicates that the entire device has been
written and is ready for another instruction.

The WRAL cycle takes 30 ms maximum (16 ms
typical).

21130F.book  Page 7  Wednesday, December 5, 2012  2:47 PM

93AA76/86

DS21130F-page 8

 1996-2012 Microchip Technology Inc.

FIGURE 3-1:

SYNCHRONOUS DATA TIMING

FIGURE 3-2:

READ

FIGURE 3-3:

EWEN

The memory automatically cycles to the next register.

V

IH

V

IL

V

IH

V

IL

V

IH

V

OH

V

OL

V

OH

V

OL

V

IL

T

SV

T

DIS

T

PD

T

DIH

T

CSS

T

CKH

T

CKL

T

PD

T

CSH

T

CZ

T

CZ

CS

CLK

DI

DO

DO

(Program)

(Read)

Status Valid

1

1

0

A

N

A

0

D

N

D

N

D

0

D

0

...

...

...

High-impedance

T

CSL

CS

CLK

DI

DO

0

CS

CLK

DI

1

1

1

0

0

T

CSL

X

X

...

ORG = V

CC

, 8 X’s

ORG = V

SS

, 9 X’s

21130F.book  Page 8  Wednesday, December 5, 2012  2:47 PM

 1996-2012 Microchip Technology Inc.

DS21130F-page 9

93AA76/86

FIGURE 3-4:

EWDS

FIGURE 3-5:

WRITE

FIGURE 3-6:

WRAL

1

0

0

0

0

X

X

...

CS

CLK

DI

T

CSL

ORG = V

CC

, 8 X’s

ORG = V

SS

, 9 X’S

1

0

1

A

N

A

0

...

D

N

...

D

0

T

WC

Ready

Busy

High-impedance

CS

CLK

DI

DO

Standby

T

CZ

Ensured at Vcc = +4.5V to +6.0V.

1

0

0

0

1

X

...

X

D

N

...

D

0

Busy

Ready

High-impedance

Standby

CS

CLK

DI

DO

ORG = V

CC

, 8 X’s

ORG = V

SS

, 9 X’s

T

WL

T

CZ

21130F.book  Page 9  Wednesday, December 5, 2012  2:47 PM

93AA76/86

DS21130F-page 10

 1996-2012 Microchip Technology Inc.

FIGURE 3-7:

ERASE

FIGURE 3-8:

ERAL

1

1

1

A

N

...

A

0

T

CZ

High-impedance

CS

CLK

DI

DO

Standby

Ready

Busy

T

WC

...

Ensured at V

CC

 = +4.5V to +6.0V.

ORG = V

CC

, 8 X’s

ORG = V

SS

, 9 X’s

1

0

0

1

0

X

X

...

CS

CLK

DI

DO

T

EC

T

CZ

High-impedance

Busy

Ready

Standby

21130F.book  Page 10  Wednesday, December 5, 2012  2:47 PM

 1996-2012 Microchip Technology Inc.

DS21130F-page 1

93AA76/86

Features:

• Single supply operation down to 1.8V

• Low-power CMOS technology:

- 1 mA active current typical

- 5 

A standby current (typical) at 3.0V

• ORG pin selectable memory configuration:

- 1024 x 8 or 512 x 16-bit organization 

(93AA76)

- 2048 x 8 or 1024 x 16-bit organization 

(93AA86)

• Self-timed erase and write cycles

• Automatic ERAL before WRAL

• Power on/off data protection circuitry

• Industry standard 3-wire serial I/O

• Device status signal during erase/write cycles

• Sequential read function

• 1,000,000 erase/write cycles ensured

• Data retention > 200 years

• 8-pin PDIP/SOIC package

• Temperature ranges available:

- Commercial (C): 0

C to +70C

Description:

The Microchip Technology Inc. 93AA76/86 are 8K and
16K low voltage serial Electrically Erasable PROMs.
The device memory is configured as x8 or x16 bits
depending on the ORG pin setup. Advanced CMOS
technology makes these devices ideal for low power
nonvolatile memory applications. These devices also
have a Program Enable (PE) pin to allow the user to
write-protect the entire contents of the memory array.
The 93AA76/86 is available in standard 8-pin PDIP and
8-pin surface mount SOIC packages.

Package Types

Block Diagram

SOIC Package

PDIP Package

CS

CLK

DI

DO

V

SS

PE

V

CC

ORG

CS

CLK

DI

DO

V

CC

PE
ORG
V

SS

93
AA76

/86

93
A

A

76
/8

6

1

2

3

4

8

7

6

5

1

2

3

4

8

7

6

5

DO

CS

CLK

V

CC

V

SS

Memory

Array

Address

Decoder

Data

Register

Counter

Address

Output

Buffer

Mode

Decode

Logic

Generator

Clock

DI

PE

8K/16K 1.8V Microwire Serial EEPROM

Not recommended for new designs –

Please use 93AA76C or 93AA86C.

21130F.book  Page 1  Wednesday, December 5, 2012  2:47 PM

93AA76/86

DS21130F-page 2

 1996-2012 Microchip Technology Inc.

1.0

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

(†)

V

CC

.............................................................................................................................................................................7.0V

All inputs and outputs w.r.t. V

SS

  ........................................................................................................ -0.6V to Vcc + 1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied ................................................................................................-40°C to +125°C

Soldering temperature of leads (10 seconds) ....................................................................................................... +300°C

ESD protection on all pins .......................................................................................................................................... 4 kV

1.1

 AC Test Conditions

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.

AC Waveform:

V

LO

 = 2.0V

V

HI

 = Vcc - 0.2V

(Note 1)

V

HI

 = 4.0V for

(Note 2)

Timing Measurement Reference Level:

Input

0.5 V

CC

Output

0.5 V

CC

Note 1:

For V

CC

 4.0V

2:

For V

CC

 4.0V

21130F.book  Page 2  Wednesday, December 5, 2012  2:47 PM

 1996-2012 Microchip Technology Inc.

DS21130F-page 3

93AA76/86

TABLE 1-1:

DC CHARACTERISTICS

DC CHARACTERISTICS

Applicable over recommended operating ranges shown below unless otherwise noted:
V

CC

 = +1.8V to +6.0V

Commercial (C): T

A

  =   0°C to +70°C

Parameter

Symbol

Min.

Max.

Units

Conditions

High-level input voltage

V

IH1

2.0

V

CC

 + 1

V

V

CC

 2.7V

V

IH2

0.7 V

CC

V

CC

 + 1

V

V

CC

 < 2.7V

Low-level input voltage

V

IL1

-0.3

0.8

V

V

CC

 2.7V

V

IL2

-0.3

0.2 V

CC

V

V

CC

 < 2.7V

Low-level output voltage

V

OL1

—

0.4

V

I

OL

 = 2.1 mA; V

CC

 = 4.5V

V

OL2

—

0.2

V

I

OL

 =100 

A; V

CC

 = V

CC

 Min.

High-level output voltage

V

OH1

2.4

—

V

I

OH

 = -400 

A; V

CC

 = 4.5V

V

OH2

V

CC

-0.2

—

V

I

OH

 = -100 

A; V

CC

 = V

CC

 Min.

Input leakage current

I

LI

-10

10

A

V

IN

 = 0.1V to V

CC

Output leakage current

I

LO

-10

10

A

V

OUT

 = 0.1V to V

CC

Pin capacitance
(all inputs/outputs)

C

INT

—

7

pF

 (Note 1)
 T

A

 = +25°C, F

CLK

 = 1 MHz 

Operating current 

I

CC

 write

—

3

mA

V

CC

 = 5.5V

I

CC

 read

—

1 

500

mA

A

F

CLK

 = 3 MHz; V

CC

 = 5.5V

F

CLK

 = 1 MHz; V

CC

 = 3.0V

Standby current

I

CCS

—

100

30

A
A

CLK = CS = 0V; V

CC

 = 5.5V

CLK = CS = 0V; V

CC 

= 3.0V 

DI = PE = V

SS

ORG = V

SS

 or V

CC

Note 1:

This parameter is periodically sampled and not 100% tested.

21130F.book  Page 3  Wednesday, December 5, 2012  2:47 PM

93AA76/86

DS21130F-page 4

 1996-2012 Microchip Technology Inc.

TABLE 1-2:

AC CHARACTERISTICS

AC CHARACTERISTICS

Applicable over recommended operating ranges shown below unless otherwise noted:
V

CC

 = +1.8V to +6.0V

Commercial (C): T

A

  =   0°C to +70°C

Parameter

Symbol

Min.

Max.

Units

Conditions

Clock frequency

F

CLK

—

3
2
1

MHz
MHz

Mhz

4.5V 

V

CC  

 6.0V

2.5V 

 V

CC

 4.5V

1.8V 

V

CC 

 2.5V

Clock high time

T

CKH

200
300
500

—

ns
ns
ns

4.5V  

V

CC 

 6.0V

2.5V  

V

CC 

 4.5V

1.8V  

V

CC 

 2.5V

Clock low time

T

CKL

100
200
500

—

ns
ns
ns

4.5V  

V

CC 

 6.0V

2.5V  

V

CC 

 4.5V

1.8V 

 V

CC

 < 2.5V

Chip select setup time

T

CSS

50

100
250

—

ns
ns
ns

4.5V  

V

CC 

 6.0V, Relative to CLK

2.5V  

V

CC 

 4.5V, Relative to CLK

1.8V  

V

CC 

 2.5V, Relative to CLK

Chip select hold time

T

CSH

0

—

ns

1.8V  

V

CC 

 6.0V

Chip select low time

T

CSL

250

—

ns

1.8V  

V

CC 

 6.0V, Relative to CLK

Data input setup time

T

DIS

50

100
250

—

ns
ns
ns

4.5V  

V

CC 

 6.0V, Relative to CLK

2.5V  

V

CC

 <4.5V, Relative to CLK

1.8V  

V

CC

 < 2.5V, Relative to CLK

Data input hold time

T

DIH

50

100
250

—

ns
ns
ns

4.5V  

V

CC 

 6.0V, Relative to CLK

2.5V  

V

CC 

 4.5V, Relative to CLK

1.8V  

V

CC

 < 2.5V, Relative to CLK

Data output delay time

T

PD

—

100
250
500

ns
ns
ns

4.5V  

V

CC 

 6.0V, C

L 

= 100 pF

2.5V  

V

CC

 < 4.5V, C

L

 = 100 pF

1.8V  

V

CC

 < 2.5V, C

L

 = 100 pF

Data output disable time

T

CZ

—

100
500

ns
ns

4.5V  

V

CC 

 5.5V (Note 1)

1.8V  

 V

CC

 < 4.5V  (Note 1)

Status valid time

Tsv

—

200
300
500

ns
ns
ns

4.5V  

V

CC 

 6.0V, C

L

 = 100 pF

2.5V  

V

CC 

< 4.5V, C

L

 = 100 pF

1.8V  

V

CC 

< 2.5V, C

L

 = 100 pF

Program cycle time

T

WC

—

5

ms

Erase/Write mode

T

EC

—

15

ms

ERAL mode

T

WL

—

30

ms

WRAL mode 

Endurance

—

1M

—

cycles

25°C, V

CC

 = 5.0V, Block mode (Note 2)

Note 1:

This parameter is periodically sampled and not 100% tested.

2:

This parameter is not tested but ensured by characterization. For endurance estimates in a specific 
application, please consult the Total Endurance

™ 

Model which can be obtained from Microchip’s web site 

at: www.microchip.com

21130F.book  Page 4  Wednesday, December 5, 2012  2:47 PM

 1996-2012 Microchip Technology Inc.

DS21130F-page 5

93AA76/86

TABLE 1-3:

INSTRUCTION SET FOR 93AA76: ORG = 1 (X16 ORGANIZATION)

TABLE 1-4:

INSTRUCTION SET FOR 93AA76: ORG = 0 (X8 ORGANIZATION)

TABLE 1-5:

INSTRUCTION SET FOR 93AA86: ORG = 1 (X16 ORGANIZATION)

TABLE 1-6:

INSTRUCTION SET FOR 93AA86: ORG = 0 (X8 ORGANIZATION)

Instruction

SB

Opcode

Address

Data In 

Data Out

Req. CLK Cycles

READ

1

10

X A8 A7 A6 A5 A4 A3 A2 A1 A0

—

D15 - D0

29

EWEN

1

00

1   1   X   X   X   X   X   X   X   X

—

High-Z

13

ERASE

1

11

X A8 A7 A6 A5 A4 A3 A2 A1 A0

—

(RDY/BSY)

13

ERAL

1

00

1   0   X   X   X   X   X   X   X   X

—

(RDY/BSY)

13

WRITE

1

01

X A8 A7 A6 A5 A4 A3 A2 A1 A0

D15 - D0

(RDY/BSY)

29

WRAL

1

00

0   1   X   X   X   X   X   X   X   X

D15 - D0

(RDY/BSY)

29

EWDS

1

00

0   0   X   X   X   X   X   X   X   X

—

High-Z

13

Instruction

SB

Opcode

Address

Data In 

Data Out

Req. CLK 

Cycles

READ

1

10

X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

—

D7 - D0

22

EWEN

1

00

1   1   X   X   X   X   X   X   X   X

—

High-Z

14

ERASE

1

11

 X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

—

(RDY/BSY)

14

ERAL

1

00

1   0   X   X   X   X   X   X   X   X

—

(RDY/BSY)

14

WRITE

1

01

 X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

D7 - D0

(RDY/BSY)

22

WRAL

1

00

0   1   X   X   X   X   X   X   X   X

D7 - D0

(RDY/BSY)

22

EWDS

1

00

0   0   X   X   X   X   X   X   X   X

—

High-Z

14

Instruction

SB

Opcode

Address

Data In 

Data Out

Req. CLK Cycles

READ

1

10

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

—

D15 - D0

29

EWEN

1

00

1   1   X   X   X   X   X   X  X   X 

—

High-Z

13

ERASE

1

11

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

—

(RDY/BSY)

13

ERAL

1

00

1   0   X   X   X   X   X   X  X   X

—

(RDY/BSY)

13

WRITE

1

01

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

D15 - D0

(RDY/BSY)

29

WRAL

1

00

0   1   X   X   X   X   X   X   X   X

D15 - D0

(RDY/BSY)

29

EWDS

1

00

0   0   X   X   X   X   X   X   X   X

—

High-Z

13

Instruction

SB

Opcode

Address

Data In 

Data Out

Req. CLK Cycles

READ

1

10

A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

—

D7 - D0

22

EWEN

1

00

1    1    X    X    X    X    X    X    X    X

—

High-Z

14

ERASE

1

11

A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

—

(RDY/BSY)

14

ERAL

1

00

1    0    X    X    X    X    X    X    X    X  

—

(RDY/BSY)

14

WRITE

1

01

A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

D7 - D0

(RDY/BSY)

22

WRAL

1

00

0    1    X    X   X    X    X    X    X    X

D7 - D0

(RDY/BSY)

22

EWDS

1

00

0    0    X    X    X    X    X    X    X    X

—

High-Z

14

21130F.book  Page 5  Wednesday, December 5, 2012  2:47 PM

93AA76/86

DS21130F-page 6

 1996-2012 Microchip Technology Inc.

2.0

PRINCIPLES OF OPERATION

When the ORG pin is connected to V

CC

, the x16

organization is selected. When it is connected to ground,
the x8 organization is selected. Instructions, addresses
and write data are clocked into the DI pin on the rising
edge of the clock (CLK). The DO pin is normally held in
a high-Z state except when reading data from the
device, or when checking the Ready/Busy status during
a programming operation. The Ready/Busy status can
be verified during an erase/write operation by polling the
DO pin; DO low indicates that programming is still in
progress, while DO high indicates the device is ready.
The DO will enter the high-impedance state on the falling
edge of the CS.

2.1

Start Condition

The Start bit is detected by the device if CS and DI are
both high with respect to the positive edge of CLK for
the first time.

Before a Start condition is detected, CS, CLK and DI
may change in any combination (except to that of a
Start condition), without resulting in any device opera-
tion (Read, Write, Erase, EWEN, EWDS, ERAL and
WRAL). As soon as CS is high, the device is no longer
in the Standby mode.

An instruction following a Start condition will only be
executed if the required amount of opcode, address
and data bits for any particular instruction are clocked
in.

After execution of an instruction (i.e., clock in or out of
the last required address or data bit) CLK and DI
become “don't care” bits until a new Start condition is
detected.

2.2

DI/DO

It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero”
that precedes the read operation, if A0 is a logic high
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of A0,
the higher the voltage at the Data Out pin. 

2.3

Erase/Write Enable and Disable 
(EWEN, EWDS)

The 93AA76/86 powers up in the Erase/Write Disable
(EWDS) state. All programming modes must be
preceded by an Erase/Write Enable (EWEN) instruction.
Once the EWEN instruction is executed, programming
remains enabled until an EWDS instruction is executed
or V

CC

 is removed from the device. To protect against

accidental data disturb, the EWDS instruction can be
used to disable all erase/write functions and should
follow all programming operations. Execution of a READ
instruction is independent of both the EWEN and EWDS
instructions.

2.4

Data Protection

During power-up, all programming modes of operation
are inhibited until V

CC

 has reached a level greater than

1.4V. During power-down, the source data protection
circuitry acts to inhibit all programming modes when
V

CC

 has fallen below 1.4V.

The EWEN and EWDS commands give additional
protection against accidentally programming during
normal operation.

After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before any ERASE or WRITE instruction can
be executed.

21130F.book  Page 6  Wednesday, December 5, 2012  2:47 PM

 1996-2012 Microchip Technology Inc.

DS21130F-page 7

93AA76/86

3.0

DEVICE OPERATION

3.1

READ

The  READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 16-bit (x16 organization) or 8-bit
(x8 organization) output string. The output data bits will
toggle on the rising edge of the CLK and are stable
after the specified time delay (T

PD

). Sequential read is

possible when CS is held high and clock transitions
continue. The memory address pointer will automati-
cally increment and output data sequentially.

3.2

ERASE

The  ERASE instruction forces all data bits of the
specified address to the logical “1” state. The self-timed
programming cycle is initiated on the rising edge of
CLK as the last address bit (A0) is clocked in. At this
point, the CLK, CS and DI inputs become “don’t cares”. 

The DO pin indicates the Ready/Busy status of the
device if the CS is high. The Ready/Busy status will be
displayed on the DO pin until the next Start bit is
received as long as CS is high. Bringing the CS low will
place the device in Standby mode and cause the DO
pin to enter the high-impedance state. DO at logical “0”
indicates that programming is still in progress. DO at
logical “1” indicates that the register at the specified
address has been erased and the device is ready for
another instruction.

The erase cycle takes 3 ms per word (typical).

3.3

WRITE

The  WRITE instruction is followed by 16 bits (or by 8
bits) of data to be written into the specified address.
The self-timed programming cycle is initiated on the
rising edge of CLK as the last data bit (D0) is clocked
in. At this point, the CLK, CS and DI inputs become
“don’t cares”.

The DO pin indicates the Ready/Busy status of the
device if the CS is high. The Ready/Busy status will be
displayed on the DO pin until the next Start bit is
received as long as CS is high. Bringing the CS low will
place the device in Standby mode and cause the DO
pin to enter the high-impedance state. DO at logical “0”
indicates that programming is still in progress. DO at
logical “1” indicates that the register at the specified
address has been written and the device is ready for
another instruction.

The write cycle takes 3 ms per word (typical).

3.4

Erase All (ERAL)

The ERAL instruction will erase the entire memory array
to the logical “1” state. The ERAL cycle is identical to
the erase cycle except for the different opcode. The
ERAL cycle is completely self-timed and commences
on the rising edge of the last address bit (A0). Note that
the Least Significant 8 or 9 address bits are “don’t care”
bits, depending on selection of x16 or x8 mode.
Clocking of the CLK pin is not necessary after the
device has entered the self clocking mode. The ERAL
instruction is ensured at Vcc = +4.5V to +6.0V.

The DO pin indicates the Ready/Busy status of the
device if the CS is high. The Ready/Busy status will be
displayed on the DO pin until the next Start bit is
received as long as CS is high. Bringing the CS low will
place the device in Standby mode and cause the DO
pin to enter the high-impedance state. DO at logical “0”
indicates that programming is still in progress. DO at
logical “1” indicates that the entire device has been
erased and is ready for another instruction.

The ERAL cycle takes 15 ms maximum (8 ms typical).

3.5

Write All (WRAL)

The WRAL instruction will write the entire memory array
with the data specified in the command. The WRAL
cycle is completely self-timed and commences on the
rising edge of the last address bit (A0). Note that the
Least Significant 8 or 9 address bits are “don’t cares”,
depending on selection of x16 or x8 mode. Clocking of
the CLK pin is not necessary after the device has
entered the self clocking mode. The WRAL command
does include an automatic ERAL cycle for the device.
Therefore, the WRAL instruction does not require an
ERAL

 instruction but the chip must be in the EWEN

status. The WRAL instruction is ensured at Vcc = +4.5V
to +6.0V.

The DO pin indicates the Ready/Busy status of the
device if the CS is high. The Ready/Busy status will be
displayed on the DO pin until the next Start bit is
received as long as CS is high. Bringing the CS low will
place the device in Standby mode and cause the DO
pin to enter the high-impedance state. DO at logical “0”
indicates that programming is still in progress. DO at
logical “1” indicates that the entire device has been
written and is ready for another instruction.

The WRAL cycle takes 30 ms maximum (16 ms
typical).

21130F.book  Page 7  Wednesday, December 5, 2012  2:47 PM

93AA76/86

DS21130F-page 8

 1996-2012 Microchip Technology Inc.

FIGURE 3-1:

SYNCHRONOUS DATA TIMING

FIGURE 3-2:

READ

FIGURE 3-3:

EWEN

The memory automatically cycles to the next register.

V

IH

V

IL

V

IH

V

IL

V

IH

V

OH

V

OL

V

OH

V

OL

V

IL

T

SV

T

DIS

T

PD

T

DIH

T

CSS

T

CKH

T

CKL

T

PD

T

CSH

T

CZ

T

CZ

CS

CLK

DI

DO

DO

(Program)

(Read)

Status Valid

1

1

0

A

N

A

0

D

N

D

N

D

0

D

0

...

...

...

High-impedance

T

CSL

CS

CLK

DI

DO

0

CS

CLK

DI

1

1

1

0

0

T

CSL

X

X

...

ORG = V

CC

, 8 X’s

ORG = V

SS

, 9 X’s

21130F.book  Page 8  Wednesday, December 5, 2012  2:47 PM

 1996-2012 Microchip Technology Inc.

DS21130F-page 9

93AA76/86

FIGURE 3-4:

EWDS

FIGURE 3-5:

WRITE

FIGURE 3-6:

WRAL

1

0

0

0

0

X

X

...

CS

CLK

DI

T

CSL

ORG = V

CC

, 8 X’s

ORG = V

SS

, 9 X’S

1

0

1

A

N

A

0

...

D

N

...

D

0

T

WC

Ready

Busy

High-impedance

CS

CLK

DI

DO

Standby

T

CZ

Ensured at Vcc = +4.5V to +6.0V.

1

0

0

0

1

X

...

X

D

N

...

D

0

Busy

Ready

High-impedance

Standby

CS

CLK

DI

DO

ORG = V

CC

, 8 X’s

ORG = V

SS

, 9 X’s

T

WL

T

CZ

21130F.book  Page 9  Wednesday, December 5, 2012  2:47 PM

93AA76/86

DS21130F-page 10

 1996-2012 Microchip Technology Inc.

FIGURE 3-7:

ERASE

FIGURE 3-8:

ERAL

1

1

1

A

N

...

A

0

T

CZ

High-impedance

CS

CLK

DI

DO

Standby

Ready

Busy

T

WC

...

Ensured at V

CC

 = +4.5V to +6.0V.

ORG = V

CC

, 8 X’s

ORG = V

SS

, 9 X’s

1

0

0

1

0

X

X

...

CS

CLK

DI

DO

T

EC

T

CZ

High-impedance

Busy

Ready

Standby

21130F.book  Page 10  Wednesday, December 5, 2012  2:47 PM

 1996-2012 Microchip Technology Inc.

DS21130F-page 1

93AA76/86

Features:

• Single supply operation down to 1.8V

• Low-power CMOS technology:

- 1 mA active current typical

- 5 

A standby current (typical) at 3.0V

• ORG pin selectable memory configuration:

- 1024 x 8 or 512 x 16-bit organization 

(93AA76)

- 2048 x 8 or 1024 x 16-bit organization 

(93AA86)

• Self-timed erase and write cycles

• Automatic ERAL before WRAL

• Power on/off data protection circuitry

• Industry standard 3-wire serial I/O

• Device status signal during erase/write cycles

• Sequential read function

• 1,000,000 erase/write cycles ensured

• Data retention > 200 years

• 8-pin PDIP/SOIC package

• Temperature ranges available:

- Commercial (C): 0

C to +70C

Description:

The Microchip Technology Inc. 93AA76/86 are 8K and
16K low voltage serial Electrically Erasable PROMs.
The device memory is configured as x8 or x16 bits
depending on the ORG pin setup. Advanced CMOS
technology makes these devices ideal for low power
nonvolatile memory applications. These devices also
have a Program Enable (PE) pin to allow the user to
write-protect the entire contents of the memory array.
The 93AA76/86 is available in standard 8-pin PDIP and
8-pin surface mount SOIC packages.

Package Types

Block Diagram

SOIC Package

PDIP Package

CS

CLK

DI

DO

V

SS

PE

V

CC

ORG

CS

CLK

DI

DO

V

CC

PE
ORG
V

SS

93
AA76

/86

93
A

A

76
/8

6

1

2

3

4

8

7

6

5

1

2

3

4

8

7

6

5

DO

CS

CLK

V

CC

V

SS

Memory

Array

Address

Decoder

Data

Register

Counter

Address

Output

Buffer

Mode

Decode

Logic

Generator

Clock

DI

PE

8K/16K 1.8V Microwire Serial EEPROM

Not recommended for new designs –

Please use 93AA76C or 93AA86C.

21130F.book  Page 1  Wednesday, December 5, 2012  2:47 PM

93AA76/86

DS21130F-page 2

 1996-2012 Microchip Technology Inc.

1.0

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

(†)

V

CC

.............................................................................................................................................................................7.0V

All inputs and outputs w.r.t. V

SS

  ........................................................................................................ -0.6V to Vcc + 1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied ................................................................................................-40°C to +125°C

Soldering temperature of leads (10 seconds) ....................................................................................................... +300°C

ESD protection on all pins .......................................................................................................................................... 4 kV

1.1

 AC Test Conditions

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.

AC Waveform:

V

LO

 = 2.0V

V

HI

 = Vcc - 0.2V

(Note 1)

V

HI

 = 4.0V for

(Note 2)

Timing Measurement Reference Level:

Input

0.5 V

CC

Output

0.5 V

CC

Note 1:

For V

CC

 4.0V

2:

For V

CC

 4.0V

21130F.book  Page 2  Wednesday, December 5, 2012  2:47 PM

 1996-2012 Microchip Technology Inc.

DS21130F-page 3

93AA76/86

TABLE 1-1:

DC CHARACTERISTICS

DC CHARACTERISTICS

Applicable over recommended operating ranges shown below unless otherwise noted:
V

CC

 = +1.8V to +6.0V

Commercial (C): T

A

  =   0°C to +70°C

Parameter

Symbol

Min.

Max.

Units

Conditions

High-level input voltage

V

IH1

2.0

V

CC

 + 1

V

V

CC

 2.7V

V

IH2

0.7 V

CC

V

CC

 + 1

V

V

CC

 < 2.7V

Low-level input voltage

V

IL1

-0.3

0.8

V

V

CC

 2.7V

V

IL2

-0.3

0.2 V

CC

V

V

CC

 < 2.7V

Low-level output voltage

V

OL1

—

0.4

V

I

OL

 = 2.1 mA; V

CC

 = 4.5V

V

OL2

—

0.2

V

I

OL

 =100 

A; V

CC

 = V

CC

 Min.

High-level output voltage

V

OH1

2.4

—

V

I

OH

 = -400 

A; V

CC

 = 4.5V

V

OH2

V

CC

-0.2

—

V

I

OH

 = -100 

A; V

CC

 = V

CC

 Min.

Input leakage current

I

LI

-10

10

A

V

IN

 = 0.1V to V

CC

Output leakage current

I

LO

-10

10

A

V

OUT

 = 0.1V to V

CC

Pin capacitance
(all inputs/outputs)

C

INT

—

7

pF

 (Note 1)
 T

A

 = +25°C, F

CLK

 = 1 MHz 

Operating current 

I

CC

 write

—

3

mA

V

CC

 = 5.5V

I

CC

 read

—

1 

500

mA

A

F

CLK

 = 3 MHz; V

CC

 = 5.5V

F

CLK

 = 1 MHz; V

CC

 = 3.0V

Standby current

I

CCS

—

100

30

A
A

CLK = CS = 0V; V

CC

 = 5.5V

CLK = CS = 0V; V

CC 

= 3.0V 

DI = PE = V

SS

ORG = V

SS

 or V

CC

Note 1:

This parameter is periodically sampled and not 100% tested.

21130F.book  Page 3  Wednesday, December 5, 2012  2:47 PM

93AA76/86

DS21130F-page 4

 1996-2012 Microchip Technology Inc.

TABLE 1-2:

AC CHARACTERISTICS

AC CHARACTERISTICS

Applicable over recommended operating ranges shown below unless otherwise noted:
V

CC

 = +1.8V to +6.0V

Commercial (C): T

A

  =   0°C to +70°C

Parameter

Symbol

Min.

Max.

Units

Conditions

Clock frequency

F

CLK

—

3
2
1

MHz
MHz

Mhz

4.5V 

V

CC  

 6.0V

2.5V 

 V

CC

 4.5V

1.8V 

V

CC 

 2.5V

Clock high time

T

CKH

200
300
500

—

ns
ns
ns

4.5V  

V

CC 

 6.0V

2.5V  

V

CC 

 4.5V

1.8V  

V

CC 

 2.5V

Clock low time

T

CKL

100
200
500

—

ns
ns
ns

4.5V  

V

CC 

 6.0V

2.5V  

V

CC 

 4.5V

1.8V 

 V

CC

 < 2.5V

Chip select setup time

T

CSS

50

100
250

—

ns
ns
ns

4.5V  

V

CC 

 6.0V, Relative to CLK

2.5V  

V

CC 

 4.5V, Relative to CLK

1.8V  

V

CC 

 2.5V, Relative to CLK

Chip select hold time

T

CSH

0

—

ns

1.8V  

V

CC 

 6.0V

Chip select low time

T

CSL

250

—

ns

1.8V  

V

CC 

 6.0V, Relative to CLK

Data input setup time

T

DIS

50

100
250

—

ns
ns
ns

4.5V  

V

CC 

 6.0V, Relative to CLK

2.5V  

V

CC

 <4.5V, Relative to CLK

1.8V  

V

CC

 < 2.5V, Relative to CLK

Data input hold time

T

DIH

50

100
250

—

ns
ns
ns

4.5V  

V

CC 

 6.0V, Relative to CLK

2.5V  

V

CC 

 4.5V, Relative to CLK

1.8V  

V

CC

 < 2.5V, Relative to CLK

Data output delay time

T

PD

—

100
250
500

ns
ns
ns

4.5V  

V

CC 

 6.0V, C

L 

= 100 pF

2.5V  

V

CC

 < 4.5V, C

L

 = 100 pF

1.8V  

V

CC

 < 2.5V, C

L

 = 100 pF

Data output disable time

T

CZ

—

100
500

ns
ns

4.5V  

V

CC 

 5.5V (Note 1)

1.8V  

 V

CC

 < 4.5V  (Note 1)

Status valid time

Tsv

—

200
300
500

ns
ns
ns

4.5V  

V

CC 

 6.0V, C

L

 = 100 pF

2.5V  

V

CC 

< 4.5V, C

L

 = 100 pF

1.8V  

V

CC 

< 2.5V, C

L

 = 100 pF

Program cycle time

T

WC

—

5

ms

Erase/Write mode

T

EC

—

15

ms

ERAL mode

T

WL

—

30

ms

WRAL mode 

Endurance

—

1M

—

cycles

25°C, V

CC

 = 5.0V, Block mode (Note 2)

Note 1:

This parameter is periodically sampled and not 100% tested.

2:

This parameter is not tested but ensured by characterization. For endurance estimates in a specific 
application, please consult the Total Endurance

™ 

Model which can be obtained from Microchip’s web site 

at: www.microchip.com

21130F.book  Page 4  Wednesday, December 5, 2012  2:47 PM

 1996-2012 Microchip Technology Inc.

DS21130F-page 5

93AA76/86

TABLE 1-3:

INSTRUCTION SET FOR 93AA76: ORG = 1 (X16 ORGANIZATION)

TABLE 1-4:

INSTRUCTION SET FOR 93AA76: ORG = 0 (X8 ORGANIZATION)

TABLE 1-5:

INSTRUCTION SET FOR 93AA86: ORG = 1 (X16 ORGANIZATION)

TABLE 1-6:

INSTRUCTION SET FOR 93AA86: ORG = 0 (X8 ORGANIZATION)

Instruction

SB

Opcode

Address

Data In 

Data Out

Req. CLK Cycles

READ

1

10

X A8 A7 A6 A5 A4 A3 A2 A1 A0

—

D15 - D0

29

EWEN

1

00

1   1   X   X   X   X   X   X   X   X

—

High-Z

13

ERASE

1

11

X A8 A7 A6 A5 A4 A3 A2 A1 A0

—

(RDY/BSY)

13

ERAL

1

00

1   0   X   X   X   X   X   X   X   X

—

(RDY/BSY)

13

WRITE

1

01

X A8 A7 A6 A5 A4 A3 A2 A1 A0

D15 - D0

(RDY/BSY)

29

WRAL

1

00

0   1   X   X   X   X   X   X   X   X

D15 - D0

(RDY/BSY)

29

EWDS

1

00

0   0   X   X   X   X   X   X   X   X

—

High-Z

13

Instruction

SB

Opcode

Address

Data In 

Data Out

Req. CLK 

Cycles

READ

1

10

X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

—

D7 - D0

22

EWEN

1

00

1   1   X   X   X   X   X   X   X   X

—

High-Z

14

ERASE

1

11

 X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

—

(RDY/BSY)

14

ERAL

1

00

1   0   X   X   X   X   X   X   X   X

—

(RDY/BSY)

14

WRITE

1

01

 X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

D7 - D0

(RDY/BSY)

22

WRAL

1

00

0   1   X   X   X   X   X   X   X   X

D7 - D0

(RDY/BSY)

22

EWDS

1

00

0   0   X   X   X   X   X   X   X   X

—

High-Z

14

Instruction

SB

Opcode

Address

Data In 

Data Out

Req. CLK Cycles

READ

1

10

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

—

D15 - D0

29

EWEN

1

00

1   1   X   X   X   X   X   X  X   X 

—

High-Z

13

ERASE

1

11

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

—

(RDY/BSY)

13

ERAL

1

00

1   0   X   X   X   X   X   X  X   X

—

(RDY/BSY)

13

WRITE

1

01

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

D15 - D0

(RDY/BSY)

29

WRAL

1

00

0   1   X   X   X   X   X   X   X   X

D15 - D0

(RDY/BSY)

29

EWDS

1

00

0   0   X   X   X   X   X   X   X   X

—

High-Z

13

Instruction

SB

Opcode

Address

Data In 

Data Out

Req. CLK Cycles

READ

1

10

A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

—

D7 - D0

22

EWEN

1

00

1    1    X    X    X    X    X    X    X    X

—

High-Z

14

ERASE

1

11

A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

—

(RDY/BSY)

14

ERAL

1

00

1    0    X    X    X    X    X    X    X    X  

—

(RDY/BSY)

14

WRITE

1

01

A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

D7 - D0

(RDY/BSY)

22

WRAL

1

00

0    1    X    X   X    X    X    X    X    X

D7 - D0

(RDY/BSY)

22

EWDS

1

00

0    0    X    X    X    X    X    X    X    X

—

High-Z

14

21130F.book  Page 5  Wednesday, December 5, 2012  2:47 PM

93AA76/86

DS21130F-page 6

 1996-2012 Microchip Technology Inc.

2.0

PRINCIPLES OF OPERATION

When the ORG pin is connected to V

CC

, the x16

organization is selected. When it is connected to ground,
the x8 organization is selected. Instructions, addresses
and write data are clocked into the DI pin on the rising
edge of the clock (CLK). The DO pin is normally held in
a high-Z state except when reading data from the
device, or when checking the Ready/Busy status during
a programming operation. The Ready/Busy status can
be verified during an erase/write operation by polling the
DO pin; DO low indicates that programming is still in
progress, while DO high indicates the device is ready.
The DO will enter the high-impedance state on the falling
edge of the CS.

2.1

Start Condition

The Start bit is detected by the device if CS and DI are
both high with respect to the positive edge of CLK for
the first time.

Before a Start condition is detected, CS, CLK and DI
may change in any combination (except to that of a
Start condition), without resulting in any device opera-
tion (Read, Write, Erase, EWEN, EWDS, ERAL and
WRAL). As soon as CS is high, the device is no longer
in the Standby mode.

An instruction following a Start condition will only be
executed if the required amount of opcode, address
and data bits for any particular instruction are clocked
in.

After execution of an instruction (i.e., clock in or out of
the last required address or data bit) CLK and DI
become “don't care” bits until a new Start condition is
detected.

2.2

DI/DO

It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero”
that precedes the read operation, if A0 is a logic high
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of A0,
the higher the voltage at the Data Out pin. 

2.3

Erase/Write Enable and Disable 
(EWEN, EWDS)

The 93AA76/86 powers up in the Erase/Write Disable
(EWDS) state. All programming modes must be
preceded by an Erase/Write Enable (EWEN) instruction.
Once the EWEN instruction is executed, programming
remains enabled until an EWDS instruction is executed
or V

CC

 is removed from the device. To protect against

accidental data disturb, the EWDS instruction can be
used to disable all erase/write functions and should
follow all programming operations. Execution of a READ
instruction is independent of both the EWEN and EWDS
instructions.

2.4

Data Protection

During power-up, all programming modes of operation
are inhibited until V

CC

 has reached a level greater than

1.4V. During power-down, the source data protection
circuitry acts to inhibit all programming modes when
V

CC

 has fallen below 1.4V.

The EWEN and EWDS commands give additional
protection against accidentally programming during
normal operation.

After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before any ERASE or WRITE instruction can
be executed.

21130F.book  Page 6  Wednesday, December 5, 2012  2:47 PM

 1996-2012 Microchip Technology Inc.

DS21130F-page 7

93AA76/86

3.0

DEVICE OPERATION

3.1

READ

The  READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 16-bit (x16 organization) or 8-bit
(x8 organization) output string. The output data bits will
toggle on the rising edge of the CLK and are stable
after the specified time delay (T

PD

). Sequential read is

possible when CS is held high and clock transitions
continue. The memory address pointer will automati-
cally increment and output data sequentially.

3.2

ERASE

The  ERASE instruction forces all data bits of the
specified address to the logical “1” state. The self-timed
programming cycle is initiated on the rising edge of
CLK as the last address bit (A0) is clocked in. At this
point, the CLK, CS and DI inputs become “don’t cares”. 

The DO pin indicates the Ready/Busy status of the
device if the CS is high. The Ready/Busy status will be
displayed on the DO pin until the next Start bit is
received as long as CS is high. Bringing the CS low will
place the device in Standby mode and cause the DO
pin to enter the high-impedance state. DO at logical “0”
indicates that programming is still in progress. DO at
logical “1” indicates that the register at the specified
address has been erased and the device is ready for
another instruction.

The erase cycle takes 3 ms per word (typical).

3.3

WRITE

The  WRITE instruction is followed by 16 bits (or by 8
bits) of data to be written into the specified address.
The self-timed programming cycle is initiated on the
rising edge of CLK as the last data bit (D0) is clocked
in. At this point, the CLK, CS and DI inputs become
“don’t cares”.

The DO pin indicates the Ready/Busy status of the
device if the CS is high. The Ready/Busy status will be
displayed on the DO pin until the next Start bit is
received as long as CS is high. Bringing the CS low will
place the device in Standby mode and cause the DO
pin to enter the high-impedance state. DO at logical “0”
indicates that programming is still in progress. DO at
logical “1” indicates that the register at the specified
address has been written and the device is ready for
another instruction.

The write cycle takes 3 ms per word (typical).

3.4

Erase All (ERAL)

The ERAL instruction will erase the entire memory array
to the logical “1” state. The ERAL cycle is identical to
the erase cycle except for the different opcode. The
ERAL cycle is completely self-timed and commences
on the rising edge of the last address bit (A0). Note that
the Least Significant 8 or 9 address bits are “don’t care”
bits, depending on selection of x16 or x8 mode.
Clocking of the CLK pin is not necessary after the
device has entered the self clocking mode. The ERAL
instruction is ensured at Vcc = +4.5V to +6.0V.

The DO pin indicates the Ready/Busy status of the
device if the CS is high. The Ready/Busy status will be
displayed on the DO pin until the next Start bit is
received as long as CS is high. Bringing the CS low will
place the device in Standby mode and cause the DO
pin to enter the high-impedance state. DO at logical “0”
indicates that programming is still in progress. DO at
logical “1” indicates that the entire device has been
erased and is ready for another instruction.

The ERAL cycle takes 15 ms maximum (8 ms typical).

3.5

Write All (WRAL)

The WRAL instruction will write the entire memory array
with the data specified in the command. The WRAL
cycle is completely self-timed and commences on the
rising edge of the last address bit (A0). Note that the
Least Significant 8 or 9 address bits are “don’t cares”,
depending on selection of x16 or x8 mode. Clocking of
the CLK pin is not necessary after the device has
entered the self clocking mode. The WRAL command
does include an automatic ERAL cycle for the device.
Therefore, the WRAL instruction does not require an
ERAL

 instruction but the chip must be in the EWEN

status. The WRAL instruction is ensured at Vcc = +4.5V
to +6.0V.

The DO pin indicates the Ready/Busy status of the
device if the CS is high. The Ready/Busy status will be
displayed on the DO pin until the next Start bit is
received as long as CS is high. Bringing the CS low will
place the device in Standby mode and cause the DO
pin to enter the high-impedance state. DO at logical “0”
indicates that programming is still in progress. DO at
logical “1” indicates that the entire device has been
written and is ready for another instruction.

The WRAL cycle takes 30 ms maximum (16 ms
typical).

21130F.book  Page 7  Wednesday, December 5, 2012  2:47 PM

93AA76/86

DS21130F-page 8

 1996-2012 Microchip Technology Inc.

FIGURE 3-1:

SYNCHRONOUS DATA TIMING

FIGURE 3-2:

READ

FIGURE 3-3:

EWEN

The memory automatically cycles to the next register.

V

IH

V

IL

V

IH

V

IL

V

IH

V

OH

V

OL

V

OH

V

OL

V

IL

T

SV

T

DIS

T

PD

T

DIH

T

CSS

T

CKH

T

CKL

T

PD

T

CSH

T

CZ

T

CZ

CS

CLK

DI

DO

DO

(Program)

(Read)

Status Valid

1

1

0

A

N

A

0

D

N

D

N

D

0

D

0

...

...

...

High-impedance

T

CSL

CS

CLK

DI

DO

0

CS

CLK

DI

1

1

1

0

0

T

CSL

X

X

...

ORG = V

CC

, 8 X’s

ORG = V

SS

, 9 X’s

21130F.book  Page 8  Wednesday, December 5, 2012  2:47 PM

 1996-2012 Microchip Technology Inc.

DS21130F-page 9

93AA76/86

FIGURE 3-4:

EWDS

FIGURE 3-5:

WRITE

FIGURE 3-6:

WRAL

1

0

0

0

0

X

X

...

CS

CLK

DI

T

CSL

ORG = V

CC

, 8 X’s

ORG = V

SS

, 9 X’S

1

0

1

A

N

A

0

...

D

N

...

D

0

T

WC

Ready

Busy

High-impedance

CS

CLK

DI

DO

Standby

T

CZ

Ensured at Vcc = +4.5V to +6.0V.

1

0

0

0

1

X

...

X

D

N

...

D

0

Busy

Ready

High-impedance

Standby

CS

CLK

DI

DO

ORG = V

CC

, 8 X’s

ORG = V

SS

, 9 X’s

T

WL

T

CZ

21130F.book  Page 9  Wednesday, December 5, 2012  2:47 PM

93AA76/86

DS21130F-page 10

 1996-2012 Microchip Technology Inc.

FIGURE 3-7:

ERASE

FIGURE 3-8:

ERAL

1

1

1

A

N

...

A

0

T

CZ

High-impedance

CS

CLK

DI

DO

Standby

Ready

Busy

T

WC

...

Ensured at V

CC

 = +4.5V to +6.0V.

ORG = V

CC

, 8 X’s

ORG = V

SS

, 9 X’s

1

0

0

1

0

X

X

...

CS

CLK

DI

DO

T

EC

T

CZ

High-impedance

Busy

Ready

Standby

21130F.book  Page 10  Wednesday, December 5, 2012  2:47 PM

 1996-2012 Microchip Technology Inc.

DS21130F-page 1

93AA76/86

Features:

• Single supply operation down to 1.8V

• Low-power CMOS technology:

- 1 mA active current typical

- 5 

A standby current (typical) at 3.0V

• ORG pin selectable memory configuration:

- 1024 x 8 or 512 x 16-bit organization 

(93AA76)

- 2048 x 8 or 1024 x 16-bit organization 

(93AA86)

• Self-timed erase and write cycles

• Automatic ERAL before WRAL

• Power on/off data protection circuitry

• Industry standard 3-wire serial I/O

• Device status signal during erase/write cycles

• Sequential read function

• 1,000,000 erase/write cycles ensured

• Data retention > 200 years

• 8-pin PDIP/SOIC package

• Temperature ranges available:

- Commercial (C): 0

C to +70C

Description:

The Microchip Technology Inc. 93AA76/86 are 8K and
16K low voltage serial Electrically Erasable PROMs.
The device memory is configured as x8 or x16 bits
depending on the ORG pin setup. Advanced CMOS
technology makes these devices ideal for low power
nonvolatile memory applications. These devices also
have a Program Enable (PE) pin to allow the user to
write-protect the entire contents of the memory array.
The 93AA76/86 is available in standard 8-pin PDIP and
8-pin surface mount SOIC packages.

Package Types

Block Diagram

SOIC Package

PDIP Package

CS

CLK

DI

DO

V

SS

PE

V

CC

ORG

CS

CLK

DI

DO

V

CC

PE
ORG
V

SS

93
AA76

/86

93
A

A

76
/8

6

1

2

3

4

8

7

6

5

1

2

3

4

8

7

6

5

DO

CS

CLK

V

CC

V

SS

Memory

Array

Address

Decoder

Data

Register

Counter

Address

Output

Buffer

Mode

Decode

Logic

Generator

Clock

DI

PE

8K/16K 1.8V Microwire Serial EEPROM

Not recommended for new designs –

Please use 93AA76C or 93AA86C.

21130F.book  Page 1  Wednesday, December 5, 2012  2:47 PM

93AA76/86

DS21130F-page 2

 1996-2012 Microchip Technology Inc.

1.0

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

(†)

V

CC

.............................................................................................................................................................................7.0V

All inputs and outputs w.r.t. V

SS

  ........................................................................................................ -0.6V to Vcc + 1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied ................................................................................................-40°C to +125°C

Soldering temperature of leads (10 seconds) ....................................................................................................... +300°C

ESD protection on all pins .......................................................................................................................................... 4 kV

1.1

 AC Test Conditions

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.

AC Waveform:

V

LO

 = 2.0V

V

HI

 = Vcc - 0.2V

(Note 1)

V

HI

 = 4.0V for

(Note 2)

Timing Measurement Reference Level:

Input

0.5 V

CC

Output

0.5 V

CC

Note 1:

For V

CC

 4.0V

2:

For V

CC

 4.0V

21130F.book  Page 2  Wednesday, December 5, 2012  2:47 PM

 1996-2012 Microchip Technology Inc.

DS21130F-page 3

93AA76/86

TABLE 1-1:

DC CHARACTERISTICS

DC CHARACTERISTICS

Applicable over recommended operating ranges shown below unless otherwise noted:
V

CC

 = +1.8V to +6.0V

Commercial (C): T

A

  =   0°C to +70°C

Parameter

Symbol

Min.

Max.

Units

Conditions

High-level input voltage

V

IH1

2.0

V

CC

 + 1

V

V

CC

 2.7V

V

IH2

0.7 V

CC

V

CC

 + 1

V

V

CC

 < 2.7V

Low-level input voltage

V

IL1

-0.3

0.8

V

V

CC

 2.7V

V

IL2

-0.3

0.2 V

CC

V

V

CC

 < 2.7V

Low-level output voltage

V

OL1

—

0.4

V

I

OL

 = 2.1 mA; V

CC

 = 4.5V

V

OL2

—

0.2

V

I

OL

 =100 

A; V

CC

 = V

CC

 Min.

High-level output voltage

V

OH1

2.4

—

V

I

OH

 = -400 

A; V

CC

 = 4.5V

V

OH2

V

CC

-0.2

—

V

I

OH

 = -100 

A; V

CC

 = V

CC

 Min.

Input leakage current

I

LI

-10

10

A

V

IN

 = 0.1V to V

CC

Output leakage current

I

LO

-10

10

A

V

OUT

 = 0.1V to V

CC

Pin capacitance
(all inputs/outputs)

C

INT

—

7

pF

 (Note 1)
 T

A

 = +25°C, F

CLK

 = 1 MHz 

Operating current 

I

CC

 write

—

3

mA

V

CC

 = 5.5V

I

CC

 read

—

1 

500

mA

A

F

CLK

 = 3 MHz; V

CC

 = 5.5V

F

CLK

 = 1 MHz; V

CC

 = 3.0V

Standby current

I

CCS

—

100

30

A
A

CLK = CS = 0V; V

CC

 = 5.5V

CLK = CS = 0V; V

CC 

= 3.0V 

DI = PE = V

SS

ORG = V

SS

 or V

CC

Note 1:

This parameter is periodically sampled and not 100% tested.

21130F.book  Page 3  Wednesday, December 5, 2012  2:47 PM

93AA76/86

DS21130F-page 4

 1996-2012 Microchip Technology Inc.

TABLE 1-2:

AC CHARACTERISTICS

AC CHARACTERISTICS

Applicable over recommended operating ranges shown below unless otherwise noted:
V

CC

 = +1.8V to +6.0V

Commercial (C): T

A

  =   0°C to +70°C

Parameter

Symbol

Min.

Max.

Units

Conditions

Clock frequency

F

CLK

—

3
2
1

MHz
MHz

Mhz

4.5V 

V

CC  

 6.0V

2.5V 

 V

CC

 4.5V

1.8V 

V

CC 

 2.5V

Clock high time

T

CKH

200
300
500

—

ns
ns
ns

4.5V  

V

CC 

 6.0V

2.5V  

V

CC 

 4.5V

1.8V  

V

CC 

 2.5V

Clock low time

T

CKL

100
200
500

—

ns
ns
ns

4.5V  

V

CC 

 6.0V

2.5V  

V

CC 

 4.5V

1.8V 

 V

CC

 < 2.5V

Chip select setup time

T

CSS

50

100
250

—

ns
ns
ns

4.5V  

V

CC 

 6.0V, Relative to CLK

2.5V  

V

CC 

 4.5V, Relative to CLK

1.8V  

V

CC 

 2.5V, Relative to CLK

Chip select hold time

T

CSH

0

—

ns

1.8V  

V

CC 

 6.0V

Chip select low time

T

CSL

250

—

ns

1.8V  

V

CC 

 6.0V, Relative to CLK

Data input setup time

T

DIS

50

100
250

—

ns
ns
ns

4.5V  

V

CC 

 6.0V, Relative to CLK

2.5V  

V

CC

 <4.5V, Relative to CLK

1.8V  

V

CC

 < 2.5V, Relative to CLK

Data input hold time

T

DIH

50

100
250

—

ns
ns
ns

4.5V  

V

CC 

 6.0V, Relative to CLK

2.5V  

V

CC 

 4.5V, Relative to CLK

1.8V  

V

CC

 < 2.5V, Relative to CLK

Data output delay time

T

PD

—

100
250
500

ns
ns
ns

4.5V  

V

CC 

 6.0V, C

L 

= 100 pF

2.5V  

V

CC

 < 4.5V, C

L

 = 100 pF

1.8V  

V

CC

 < 2.5V, C

L

 = 100 pF

Data output disable time

T

CZ

—

100
500

ns
ns

4.5V  

V

CC 

 5.5V (Note 1)

1.8V  

 V

CC

 < 4.5V  (Note 1)

Status valid time

Tsv

—

200
300
500

ns
ns
ns

4.5V  

V

CC 

 6.0V, C

L

 = 100 pF

2.5V  

V

CC 

< 4.5V, C

L

 = 100 pF

1.8V  

V

CC 

< 2.5V, C

L

 = 100 pF

Program cycle time

T

WC

—

5

ms

Erase/Write mode

T

EC

—

15

ms

ERAL mode

T

WL

—

30

ms

WRAL mode 

Endurance

—

1M

—

cycles

25°C, V

CC

 = 5.0V, Block mode (Note 2)

Note 1:

This parameter is periodically sampled and not 100% tested.

2:

This parameter is not tested but ensured by characterization. For endurance estimates in a specific 
application, please consult the Total Endurance

™ 

Model which can be obtained from Microchip’s web site 

at: www.microchip.com

21130F.book  Page 4  Wednesday, December 5, 2012  2:47 PM

 1996-2012 Microchip Technology Inc.

DS21130F-page 5

93AA76/86

TABLE 1-3:

INSTRUCTION SET FOR 93AA76: ORG = 1 (X16 ORGANIZATION)

TABLE 1-4:

INSTRUCTION SET FOR 93AA76: ORG = 0 (X8 ORGANIZATION)

TABLE 1-5:

INSTRUCTION SET FOR 93AA86: ORG = 1 (X16 ORGANIZATION)

TABLE 1-6:

INSTRUCTION SET FOR 93AA86: ORG = 0 (X8 ORGANIZATION)

Instruction

SB

Opcode

Address

Data In 

Data Out

Req. CLK Cycles

READ

1

10

X A8 A7 A6 A5 A4 A3 A2 A1 A0

—

D15 - D0

29

EWEN

1

00

1   1   X   X   X   X   X   X   X   X

—

High-Z

13

ERASE

1

11

X A8 A7 A6 A5 A4 A3 A2 A1 A0

—

(RDY/BSY)

13

ERAL

1

00

1   0   X   X   X   X   X   X   X   X

—

(RDY/BSY)

13

WRITE

1

01

X A8 A7 A6 A5 A4 A3 A2 A1 A0

D15 - D0

(RDY/BSY)

29

WRAL

1

00

0   1   X   X   X   X   X   X   X   X

D15 - D0

(RDY/BSY)

29

EWDS

1

00

0   0   X   X   X   X   X   X   X   X

—

High-Z

13

Instruction

SB

Opcode

Address

Data In 

Data Out

Req. CLK 

Cycles

READ

1

10

X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

—

D7 - D0

22

EWEN

1

00

1   1   X   X   X   X   X   X   X   X

—

High-Z

14

ERASE

1

11

 X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

—

(RDY/BSY)

14

ERAL

1

00

1   0   X   X   X   X   X   X   X   X

—

(RDY/BSY)

14

WRITE

1

01

 X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

D7 - D0

(RDY/BSY)

22

WRAL

1

00

0   1   X   X   X   X   X   X   X   X

D7 - D0

(RDY/BSY)

22

EWDS

1

00

0   0   X   X   X   X   X   X   X   X

—

High-Z

14

Instruction

SB

Opcode

Address

Data In 

Data Out

Req. CLK Cycles

READ

1

10

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

—

D15 - D0

29

EWEN

1

00

1   1   X   X   X   X   X   X  X   X 

—

High-Z

13

ERASE

1

11

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

—

(RDY/BSY)

13

ERAL

1

00

1   0   X   X   X   X   X   X  X   X

—

(RDY/BSY)

13

WRITE

1

01

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

D15 - D0

(RDY/BSY)

29

WRAL

1

00

0   1   X   X   X   X   X   X   X   X

D15 - D0

(RDY/BSY)

29

EWDS

1

00

0   0   X   X   X   X   X   X   X   X

—

High-Z

13

Instruction

SB

Opcode

Address

Data In 

Data Out

Req. CLK Cycles

READ

1

10

A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

—

D7 - D0

22

EWEN

1

00

1    1    X    X    X    X    X    X    X    X

—

High-Z

14

ERASE

1

11

A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

—

(RDY/BSY)

14

ERAL

1

00

1    0    X    X    X    X    X    X    X    X  

—

(RDY/BSY)

14

WRITE

1

01

A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

D7 - D0

(RDY/BSY)

22

WRAL

1

00

0    1    X    X   X    X    X    X    X    X

D7 - D0

(RDY/BSY)

22

EWDS

1

00

0    0    X    X    X    X    X    X    X    X

—

High-Z

14

21130F.book  Page 5  Wednesday, December 5, 2012  2:47 PM

93AA76/86

DS21130F-page 6

 1996-2012 Microchip Technology Inc.

2.0

PRINCIPLES OF OPERATION

When the ORG pin is connected to V

CC

, the x16

organization is selected. When it is connected to ground,
the x8 organization is selected. Instructions, addresses
and write data are clocked into the DI pin on the rising
edge of the clock (CLK). The DO pin is normally held in
a high-Z state except when reading data from the
device, or when checking the Ready/Busy status during
a programming operation. The Ready/Busy status can
be verified during an erase/write operation by polling the
DO pin; DO low indicates that programming is still in
progress, while DO high indicates the device is ready.
The DO will enter the high-impedance state on the falling
edge of the CS.

2.1

Start Condition

The Start bit is detected by the device if CS and DI are
both high with respect to the positive edge of CLK for
the first time.

Before a Start condition is detected, CS, CLK and DI
may change in any combination (except to that of a
Start condition), without resulting in any device opera-
tion (Read, Write, Erase, EWEN, EWDS, ERAL and
WRAL). As soon as CS is high, the device is no longer
in the Standby mode.

An instruction following a Start condition will only be
executed if the required amount of opcode, address
and data bits for any particular instruction are clocked
in.

After execution of an instruction (i.e., clock in or out of
the last required address or data bit) CLK and DI
become “don't care” bits until a new Start condition is
detected.

2.2

DI/DO

It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero”
that precedes the read operation, if A0 is a logic high
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of A0,
the higher the voltage at the Data Out pin. 

2.3

Erase/Write Enable and Disable 
(EWEN, EWDS)

The 93AA76/86 powers up in the Erase/Write Disable
(EWDS) state. All programming modes must be
preceded by an Erase/Write Enable (EWEN) instruction.
Once the EWEN instruction is executed, programming
remains enabled until an EWDS instruction is executed
or V

CC

 is removed from the device. To protect against

accidental data disturb, the EWDS instruction can be
used to disable all erase/write functions and should
follow all programming operations. Execution of a READ
instruction is independent of both the EWEN and EWDS
instructions.

2.4

Data Protection

During power-up, all programming modes of operation
are inhibited until V

CC

 has reached a level greater than

1.4V. During power-down, the source data protection
circuitry acts to inhibit all programming modes when
V

CC

 has fallen below 1.4V.

The EWEN and EWDS commands give additional
protection against accidentally programming during
normal operation.

After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before any ERASE or WRITE instruction can
be executed.

21130F.book  Page 6  Wednesday, December 5, 2012  2:47 PM

 1996-2012 Microchip Technology Inc.

DS21130F-page 7

93AA76/86

3.0

DEVICE OPERATION

3.1

READ

The  READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 16-bit (x16 organization) or 8-bit
(x8 organization) output string. The output data bits will
toggle on the rising edge of the CLK and are stable
after the specified time delay (T

PD

). Sequential read is

possible when CS is held high and clock transitions
continue. The memory address pointer will automati-
cally increment and output data sequentially.

3.2

ERASE

The  ERASE instruction forces all data bits of the
specified address to the logical “1” state. The self-timed
programming cycle is initiated on the rising edge of
CLK as the last address bit (A0) is clocked in. At this
point, the CLK, CS and DI inputs become “don’t cares”. 

The DO pin indicates the Ready/Busy status of the
device if the CS is high. The Ready/Busy status will be
displayed on the DO pin until the next Start bit is
received as long as CS is high. Bringing the CS low will
place the device in Standby mode and cause the DO
pin to enter the high-impedance state. DO at logical “0”
indicates that programming is still in progress. DO at
logical “1” indicates that the register at the specified
address has been erased and the device is ready for
another instruction.

The erase cycle takes 3 ms per word (typical).

3.3

WRITE

The  WRITE instruction is followed by 16 bits (or by 8
bits) of data to be written into the specified address.
The self-timed programming cycle is initiated on the
rising edge of CLK as the last data bit (D0) is clocked
in. At this point, the CLK, CS and DI inputs become
“don’t cares”.

The DO pin indicates the Ready/Busy status of the
device if the CS is high. The Ready/Busy status will be
displayed on the DO pin until the next Start bit is
received as long as CS is high. Bringing the CS low will
place the device in Standby mode and cause the DO
pin to enter the high-impedance state. DO at logical “0”
indicates that programming is still in progress. DO at
logical “1” indicates that the register at the specified
address has been written and the device is ready for
another instruction.

The write cycle takes 3 ms per word (typical).

3.4

Erase All (ERAL)

The ERAL instruction will erase the entire memory array
to the logical “1” state. The ERAL cycle is identical to
the erase cycle except for the different opcode. The
ERAL cycle is completely self-timed and commences
on the rising edge of the last address bit (A0). Note that
the Least Significant 8 or 9 address bits are “don’t care”
bits, depending on selection of x16 or x8 mode.
Clocking of the CLK pin is not necessary after the
device has entered the self clocking mode. The ERAL
instruction is ensured at Vcc = +4.5V to +6.0V.

The DO pin indicates the Ready/Busy status of the
device if the CS is high. The Ready/Busy status will be
displayed on the DO pin until the next Start bit is
received as long as CS is high. Bringing the CS low will
place the device in Standby mode and cause the DO
pin to enter the high-impedance state. DO at logical “0”
indicates that programming is still in progress. DO at
logical “1” indicates that the entire device has been
erased and is ready for another instruction.

The ERAL cycle takes 15 ms maximum (8 ms typical).

3.5

Write All (WRAL)

The WRAL instruction will write the entire memory array
with the data specified in the command. The WRAL
cycle is completely self-timed and commences on the
rising edge of the last address bit (A0). Note that the
Least Significant 8 or 9 address bits are “don’t cares”,
depending on selection of x16 or x8 mode. Clocking of
the CLK pin is not necessary after the device has
entered the self clocking mode. The WRAL command
does include an automatic ERAL cycle for the device.
Therefore, the WRAL instruction does not require an
ERAL

 instruction but the chip must be in the EWEN

status. The WRAL instruction is ensured at Vcc = +4.5V
to +6.0V.

The DO pin indicates the Ready/Busy status of the
device if the CS is high. The Ready/Busy status will be
displayed on the DO pin until the next Start bit is
received as long as CS is high. Bringing the CS low will
place the device in Standby mode and cause the DO
pin to enter the high-impedance state. DO at logical “0”
indicates that programming is still in progress. DO at
logical “1” indicates that the entire device has been
written and is ready for another instruction.

The WRAL cycle takes 30 ms maximum (16 ms
typical).

21130F.book  Page 7  Wednesday, December 5, 2012  2:47 PM

93AA76/86

DS21130F-page 8

 1996-2012 Microchip Technology Inc.

FIGURE 3-1:

SYNCHRONOUS DATA TIMING

FIGURE 3-2:

READ

FIGURE 3-3:

EWEN

The memory automatically cycles to the next register.

V

IH

V

IL

V

IH

V

IL

V

IH

V

OH

V

OL

V

OH

V

OL

V

IL

T

SV

T

DIS

T

PD

T

DIH

T

CSS

T

CKH

T

CKL

T

PD

T

CSH

T

CZ

T

CZ

CS

CLK

DI

DO

DO

(Program)

(Read)

Status Valid

1

1

0

A

N

A

0

D

N

D

N

D

0

D

0

...

...

...

High-impedance

T

CSL

CS

CLK

DI

DO

0

CS

CLK

DI

1

1

1

0

0

T

CSL

X

X

...

ORG = V

CC

, 8 X’s

ORG = V

SS

, 9 X’s

21130F.book  Page 8  Wednesday, December 5, 2012  2:47 PM

 1996-2012 Microchip Technology Inc.

DS21130F-page 9

93AA76/86

FIGURE 3-4:

EWDS

FIGURE 3-5:

WRITE

FIGURE 3-6:

WRAL

1

0

0

0

0

X

X

...

CS

CLK

DI

T

CSL

ORG = V

CC

, 8 X’s

ORG = V

SS

, 9 X’S

1

0

1

A

N

A

0

...

D

N

...

D

0

T

WC

Ready

Busy

High-impedance

CS

CLK

DI

DO

Standby

T

CZ

Ensured at Vcc = +4.5V to +6.0V.

1

0

0

0

1

X

...

X

D

N

...

D

0

Busy

Ready

High-impedance

Standby

CS

CLK

DI

DO

ORG = V

CC

, 8 X’s

ORG = V

SS

, 9 X’s

T

WL

T

CZ

21130F.book  Page 9  Wednesday, December 5, 2012  2:47 PM

93AA76/86

DS21130F-page 10

 1996-2012 Microchip Technology Inc.

FIGURE 3-7:

ERASE

FIGURE 3-8:

ERAL

1

1

1

A

N

...

A

0

T

CZ

High-impedance

CS

CLK

DI

DO

Standby

Ready

Busy

T

WC

...

Ensured at V

CC

 = +4.5V to +6.0V.

ORG = V

CC

, 8 X’s

ORG = V

SS

, 9 X’s

1

0

0

1

0

X

X

...

CS

CLK

DI

DO

T

EC

T

CZ

High-impedance

Busy

Ready

Standby

21130F.book  Page 10  Wednesday, December 5, 2012  2:47 PM

 1996-2012 Microchip Technology Inc.

DS21130F-page 1

93AA76/86

Features:

• Single supply operation down to 1.8V

• Low-power CMOS technology:

- 1 mA active current typical

- 5 

A standby current (typical) at 3.0V

• ORG pin selectable memory configuration:

- 1024 x 8 or 512 x 16-bit organization 

(93AA76)

- 2048 x 8 or 1024 x 16-bit organization 

(93AA86)

• Self-timed erase and write cycles

• Automatic ERAL before WRAL

• Power on/off data protection circuitry

• Industry standard 3-wire serial I/O

• Device status signal during erase/write cycles

• Sequential read function

• 1,000,000 erase/write cycles ensured

• Data retention > 200 years

• 8-pin PDIP/SOIC package

• Temperature ranges available:

- Commercial (C): 0

C to +70C

Description:

The Microchip Technology Inc. 93AA76/86 are 8K and
16K low voltage serial Electrically Erasable PROMs.
The device memory is configured as x8 or x16 bits
depending on the ORG pin setup. Advanced CMOS
technology makes these devices ideal for low power
nonvolatile memory applications. These devices also
have a Program Enable (PE) pin to allow the user to
write-protect the entire contents of the memory array.
The 93AA76/86 is available in standard 8-pin PDIP and
8-pin surface mount SOIC packages.

Package Types

Block Diagram

SOIC Package

PDIP Package

CS

CLK

DI

DO

V

SS

PE

V

CC

ORG

CS

CLK

DI

DO

V

CC

PE
ORG
V

SS

93
AA76

/86

93
A

A

76
/8

6

1

2

3

4

8

7

6

5

1

2

3

4

8

7

6

5

DO

CS

CLK

V

CC

V

SS

Memory

Array

Address

Decoder

Data

Register

Counter

Address

Output

Buffer

Mode

Decode

Logic

Generator

Clock

DI

PE

8K/16K 1.8V Microwire Serial EEPROM

Not recommended for new designs –

Please use 93AA76C or 93AA86C.

21130F.book  Page 1  Wednesday, December 5, 2012  2:47 PM

93AA76/86

DS21130F-page 2

 1996-2012 Microchip Technology Inc.

1.0

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

(†)

V

CC

.............................................................................................................................................................................7.0V

All inputs and outputs w.r.t. V

SS

  ........................................................................................................ -0.6V to Vcc + 1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied ................................................................................................-40°C to +125°C

Soldering temperature of leads (10 seconds) ....................................................................................................... +300°C

ESD protection on all pins .......................................................................................................................................... 4 kV

1.1

 AC Test Conditions

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.

AC Waveform:

V

LO

 = 2.0V

V

HI

 = Vcc - 0.2V

(Note 1)

V

HI

 = 4.0V for

(Note 2)

Timing Measurement Reference Level:

Input

0.5 V

CC

Output

0.5 V

CC

Note 1:

For V

CC

 4.0V

2:

For V

CC

 4.0V

21130F.book  Page 2  Wednesday, December 5, 2012  2:47 PM

 1996-2012 Microchip Technology Inc.

DS21130F-page 3

93AA76/86

TABLE 1-1:

DC CHARACTERISTICS

DC CHARACTERISTICS

Applicable over recommended operating ranges shown below unless otherwise noted:
V

CC

 = +1.8V to +6.0V

Commercial (C): T

A

  =   0°C to +70°C

Parameter

Symbol

Min.

Max.

Units

Conditions

High-level input voltage

V

IH1

2.0

V

CC

 + 1

V

V

CC

 2.7V

V

IH2

0.7 V

CC

V

CC

 + 1

V

V

CC

 < 2.7V

Low-level input voltage

V

IL1

-0.3

0.8

V

V

CC

 2.7V

V

IL2

-0.3

0.2 V

CC

V

V

CC

 < 2.7V

Low-level output voltage

V

OL1

—

0.4

V

I

OL

 = 2.1 mA; V

CC

 = 4.5V

V

OL2

—

0.2

V

I

OL

 =100 

A; V

CC

 = V

CC

 Min.

High-level output voltage

V

OH1

2.4

—

V

I

OH

 = -400 

A; V

CC

 = 4.5V

V

OH2

V

CC

-0.2

—

V

I

OH

 = -100 

A; V

CC

 = V

CC

 Min.

Input leakage current

I

LI

-10

10

A

V

IN

 = 0.1V to V

CC

Output leakage current

I

LO

-10

10

A

V

OUT

 = 0.1V to V

CC

Pin capacitance
(all inputs/outputs)

C

INT

—

7

pF

 (Note 1)
 T

A

 = +25°C, F

CLK

 = 1 MHz 

Operating current 

I

CC

 write

—

3

mA

V

CC

 = 5.5V

I

CC

 read

—

1 

500

mA

A

F

CLK

 = 3 MHz; V

CC

 = 5.5V

F

CLK

 = 1 MHz; V

CC

 = 3.0V

Standby current

I

CCS

—

100

30

A
A

CLK = CS = 0V; V

CC

 = 5.5V

CLK = CS = 0V; V

CC 

= 3.0V 

DI = PE = V

SS

ORG = V

SS

 or V

CC

Note 1:

This parameter is periodically sampled and not 100% tested.

21130F.book  Page 3  Wednesday, December 5, 2012  2:47 PM

93AA76/86

DS21130F-page 4

 1996-2012 Microchip Technology Inc.

TABLE 1-2:

AC CHARACTERISTICS

AC CHARACTERISTICS

Applicable over recommended operating ranges shown below unless otherwise noted:
V

CC

 = +1.8V to +6.0V

Commercial (C): T

A

  =   0°C to +70°C

Parameter

Symbol

Min.

Max.

Units

Conditions

Clock frequency

F

CLK

—

3
2
1

MHz
MHz

Mhz

4.5V 

V

CC  

 6.0V

2.5V 

 V

CC

 4.5V

1.8V 

V

CC 

 2.5V

Clock high time

T

CKH

200
300
500

—

ns
ns
ns

4.5V  

V

CC 

 6.0V

2.5V  

V

CC 

 4.5V

1.8V  

V

CC 

 2.5V

Clock low time

T

CKL

100
200
500

—

ns
ns
ns

4.5V  

V

CC 

 6.0V

2.5V  

V

CC 

 4.5V

1.8V 

 V

CC

 < 2.5V

Chip select setup time

T

CSS

50

100
250

—

ns
ns
ns

4.5V  

V

CC 

 6.0V, Relative to CLK

2.5V  

V

CC 

 4.5V, Relative to CLK

1.8V  

V

CC 

 2.5V, Relative to CLK

Chip select hold time

T

CSH

0

—

ns

1.8V  

V

CC 

 6.0V

Chip select low time

T

CSL

250

—

ns

1.8V  

V

CC 

 6.0V, Relative to CLK

Data input setup time

T

DIS

50

100
250

—

ns
ns
ns

4.5V  

V

CC 

 6.0V, Relative to CLK

2.5V  

V

CC

 <4.5V, Relative to CLK

1.8V  

V

CC

 < 2.5V, Relative to CLK

Data input hold time

T

DIH

50

100
250

—

ns
ns
ns

4.5V  

V

CC 

 6.0V, Relative to CLK

2.5V  

V

CC 

 4.5V, Relative to CLK

1.8V  

V

CC

 < 2.5V, Relative to CLK

Data output delay time

T

PD

—

100
250
500

ns
ns
ns

4.5V  

V

CC 

 6.0V, C

L 

= 100 pF

2.5V  

V

CC

 < 4.5V, C

L

 = 100 pF

1.8V  

V

CC

 < 2.5V, C

L

 = 100 pF

Data output disable time

T

CZ

—

100
500

ns
ns

4.5V  

V

CC 

 5.5V (Note 1)

1.8V  

 V

CC

 < 4.5V  (Note 1)

Status valid time

Tsv

—

200
300
500

ns
ns
ns

4.5V  

V

CC 

 6.0V, C

L

 = 100 pF

2.5V  

V

CC 

< 4.5V, C

L

 = 100 pF

1.8V  

V

CC 

< 2.5V, C

L

 = 100 pF

Program cycle time

T

WC

—

5

ms

Erase/Write mode

T

EC

—

15

ms

ERAL mode

T

WL

—

30

ms

WRAL mode 

Endurance

—

1M

—

cycles

25°C, V

CC

 = 5.0V, Block mode (Note 2)

Note 1:

This parameter is periodically sampled and not 100% tested.

2:

This parameter is not tested but ensured by characterization. For endurance estimates in a specific 
application, please consult the Total Endurance

™ 

Model which can be obtained from Microchip’s web site 

at: www.microchip.com

21130F.book  Page 4  Wednesday, December 5, 2012  2:47 PM

 1996-2012 Microchip Technology Inc.

DS21130F-page 5

93AA76/86

TABLE 1-3:

INSTRUCTION SET FOR 93AA76: ORG = 1 (X16 ORGANIZATION)

TABLE 1-4:

INSTRUCTION SET FOR 93AA76: ORG = 0 (X8 ORGANIZATION)

TABLE 1-5:

INSTRUCTION SET FOR 93AA86: ORG = 1 (X16 ORGANIZATION)

TABLE 1-6:

INSTRUCTION SET FOR 93AA86: ORG = 0 (X8 ORGANIZATION)

Instruction

SB

Opcode

Address

Data In 

Data Out

Req. CLK Cycles

READ

1

10

X A8 A7 A6 A5 A4 A3 A2 A1 A0

—

D15 - D0

29

EWEN

1

00

1   1   X   X   X   X   X   X   X   X

—

High-Z

13

ERASE

1

11

X A8 A7 A6 A5 A4 A3 A2 A1 A0

—

(RDY/BSY)

13

ERAL

1

00

1   0   X   X   X   X   X   X   X   X

—

(RDY/BSY)

13

WRITE

1

01

X A8 A7 A6 A5 A4 A3 A2 A1 A0

D15 - D0

(RDY/BSY)

29

WRAL

1

00

0   1   X   X   X   X   X   X   X   X

D15 - D0

(RDY/BSY)

29

EWDS

1

00

0   0   X   X   X   X   X   X   X   X

—

High-Z

13

Instruction

SB

Opcode

Address

Data In 

Data Out

Req. CLK 

Cycles

READ

1

10

X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

—

D7 - D0

22

EWEN

1

00

1   1   X   X   X   X   X   X   X   X

—

High-Z

14

ERASE

1

11

 X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

—

(RDY/BSY)

14

ERAL

1

00

1   0   X   X   X   X   X   X   X   X

—

(RDY/BSY)

14

WRITE

1

01

 X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

D7 - D0

(RDY/BSY)

22

WRAL

1

00

0   1   X   X   X   X   X   X   X   X

D7 - D0

(RDY/BSY)

22

EWDS

1

00

0   0   X   X   X   X   X   X   X   X

—

High-Z

14

Instruction

SB

Opcode

Address

Data In 

Data Out

Req. CLK Cycles

READ

1

10

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

—

D15 - D0

29

EWEN

1

00

1   1   X   X   X   X   X   X  X   X 

—

High-Z

13

ERASE

1

11

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

—

(RDY/BSY)

13

ERAL

1

00

1   0   X   X   X   X   X   X  X   X

—

(RDY/BSY)

13

WRITE

1

01

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

D15 - D0

(RDY/BSY)

29

WRAL

1

00

0   1   X   X   X   X   X   X   X   X

D15 - D0

(RDY/BSY)

29

EWDS

1

00

0   0   X   X   X   X   X   X   X   X

—

High-Z

13

Instruction

SB

Opcode

Address

Data In 

Data Out

Req. CLK Cycles

READ

1

10

A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

—

D7 - D0

22

EWEN

1

00

1    1    X    X    X    X    X    X    X    X

—

High-Z

14

ERASE

1

11

A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

—

(RDY/BSY)

14

ERAL

1

00

1    0    X    X    X    X    X    X    X    X  

—

(RDY/BSY)

14

WRITE

1

01

A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

D7 - D0

(RDY/BSY)

22

WRAL

1

00

0    1    X    X   X    X    X    X    X    X

D7 - D0

(RDY/BSY)

22

EWDS

1

00

0    0    X    X    X    X    X    X    X    X

—

High-Z

14

21130F.book  Page 5  Wednesday, December 5, 2012  2:47 PM

93AA76/86

DS21130F-page 6

 1996-2012 Microchip Technology Inc.

2.0

PRINCIPLES OF OPERATION

When the ORG pin is connected to V

CC

, the x16

organization is selected. When it is connected to ground,
the x8 organization is selected. Instructions, addresses
and write data are clocked into the DI pin on the rising
edge of the clock (CLK). The DO pin is normally held in
a high-Z state except when reading data from the
device, or when checking the Ready/Busy status during
a programming operation. The Ready/Busy status can
be verified during an erase/write operation by polling the
DO pin; DO low indicates that programming is still in
progress, while DO high indicates the device is ready.
The DO will enter the high-impedance state on the falling
edge of the CS.

2.1

Start Condition

The Start bit is detected by the device if CS and DI are
both high with respect to the positive edge of CLK for
the first time.

Before a Start condition is detected, CS, CLK and DI
may change in any combination (except to that of a
Start condition), without resulting in any device opera-
tion (Read, Write, Erase, EWEN, EWDS, ERAL and
WRAL). As soon as CS is high, the device is no longer
in the Standby mode.

An instruction following a Start condition will only be
executed if the required amount of opcode, address
and data bits for any particular instruction are clocked
in.

After execution of an instruction (i.e., clock in or out of
the last required address or data bit) CLK and DI
become “don't care” bits until a new Start condition is
detected.

2.2

DI/DO

It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero”
that precedes the read operation, if A0 is a logic high
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of A0,
the higher the voltage at the Data Out pin. 

2.3

Erase/Write Enable and Disable 
(EWEN, EWDS)

The 93AA76/86 powers up in the Erase/Write Disable
(EWDS) state. All programming modes must be
preceded by an Erase/Write Enable (EWEN) instruction.
Once the EWEN instruction is executed, programming
remains enabled until an EWDS instruction is executed
or V

CC

 is removed from the device. To protect against

accidental data disturb, the EWDS instruction can be
used to disable all erase/write functions and should
follow all programming operations. Execution of a READ
instruction is independent of both the EWEN and EWDS
instructions.

2.4

Data Protection

During power-up, all programming modes of operation
are inhibited until V

CC

 has reached a level greater than

1.4V. During power-down, the source data protection
circuitry acts to inhibit all programming modes when
V

CC

 has fallen below 1.4V.

The EWEN and EWDS commands give additional
protection against accidentally programming during
normal operation.

After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before any ERASE or WRITE instruction can
be executed.

21130F.book  Page 6  Wednesday, December 5, 2012  2:47 PM

 1996-2012 Microchip Technology Inc.

DS21130F-page 7

93AA76/86

3.0

DEVICE OPERATION

3.1

READ

The  READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 16-bit (x16 organization) or 8-bit
(x8 organization) output string. The output data bits will
toggle on the rising edge of the CLK and are stable
after the specified time delay (T

PD

). Sequential read is

possible when CS is held high and clock transitions
continue. The memory address pointer will automati-
cally increment and output data sequentially.

3.2

ERASE

The  ERASE instruction forces all data bits of the
specified address to the logical “1” state. The self-timed
programming cycle is initiated on the rising edge of
CLK as the last address bit (A0) is clocked in. At this
point, the CLK, CS and DI inputs become “don’t cares”. 

The DO pin indicates the Ready/Busy status of the
device if the CS is high. The Ready/Busy status will be
displayed on the DO pin until the next Start bit is
received as long as CS is high. Bringing the CS low will
place the device in Standby mode and cause the DO
pin to enter the high-impedance state. DO at logical “0”
indicates that programming is still in progress. DO at
logical “1” indicates that the register at the specified
address has been erased and the device is ready for
another instruction.

The erase cycle takes 3 ms per word (typical).

3.3

WRITE

The  WRITE instruction is followed by 16 bits (or by 8
bits) of data to be written into the specified address.
The self-timed programming cycle is initiated on the
rising edge of CLK as the last data bit (D0) is clocked
in. At this point, the CLK, CS and DI inputs become
“don’t cares”.

The DO pin indicates the Ready/Busy status of the
device if the CS is high. The Ready/Busy status will be
displayed on the DO pin until the next Start bit is
received as long as CS is high. Bringing the CS low will
place the device in Standby mode and cause the DO
pin to enter the high-impedance state. DO at logical “0”
indicates that programming is still in progress. DO at
logical “1” indicates that the register at the specified
address has been written and the device is ready for
another instruction.

The write cycle takes 3 ms per word (typical).

3.4

Erase All (ERAL)

The ERAL instruction will erase the entire memory array
to the logical “1” state. The ERAL cycle is identical to
the erase cycle except for the different opcode. The
ERAL cycle is completely self-timed and commences
on the rising edge of the last address bit (A0). Note that
the Least Significant 8 or 9 address bits are “don’t care”
bits, depending on selection of x16 or x8 mode.
Clocking of the CLK pin is not necessary after the
device has entered the self clocking mode. The ERAL
instruction is ensured at Vcc = +4.5V to +6.0V.

The DO pin indicates the Ready/Busy status of the
device if the CS is high. The Ready/Busy status will be
displayed on the DO pin until the next Start bit is
received as long as CS is high. Bringing the CS low will
place the device in Standby mode and cause the DO
pin to enter the high-impedance state. DO at logical “0”
indicates that programming is still in progress. DO at
logical “1” indicates that the entire device has been
erased and is ready for another instruction.

The ERAL cycle takes 15 ms maximum (8 ms typical).

3.5

Write All (WRAL)

The WRAL instruction will write the entire memory array
with the data specified in the command. The WRAL
cycle is completely self-timed and commences on the
rising edge of the last address bit (A0). Note that the
Least Significant 8 or 9 address bits are “don’t cares”,
depending on selection of x16 or x8 mode. Clocking of
the CLK pin is not necessary after the device has
entered the self clocking mode. The WRAL command
does include an automatic ERAL cycle for the device.
Therefore, the WRAL instruction does not require an
ERAL

 instruction but the chip must be in the EWEN

status. The WRAL instruction is ensured at Vcc = +4.5V
to +6.0V.

The DO pin indicates the Ready/Busy status of the
device if the CS is high. The Ready/Busy status will be
displayed on the DO pin until the next Start bit is
received as long as CS is high. Bringing the CS low will
place the device in Standby mode and cause the DO
pin to enter the high-impedance state. DO at logical “0”
indicates that programming is still in progress. DO at
logical “1” indicates that the entire device has been
written and is ready for another instruction.

The WRAL cycle takes 30 ms maximum (16 ms
typical).

21130F.book  Page 7  Wednesday, December 5, 2012  2:47 PM

93AA76/86

DS21130F-page 8

 1996-2012 Microchip Technology Inc.

FIGURE 3-1:

SYNCHRONOUS DATA TIMING

FIGURE 3-2:

READ

FIGURE 3-3:

EWEN

The memory automatically cycles to the next register.

V

IH

V

IL

V

IH

V

IL

V

IH

V

OH

V

OL

V

OH

V

OL

V

IL

T

SV

T

DIS

T

PD

T

DIH

T

CSS

T

CKH

T

CKL

T

PD

T

CSH

T

CZ

T

CZ

CS

CLK

DI

DO

DO

(Program)

(Read)

Status Valid

1

1

0

A

N

A

0

D

N

D

N

D

0

D

0

...

...

...

High-impedance

T

CSL

CS

CLK

DI

DO

0

CS

CLK

DI

1

1

1

0

0

T

CSL

X

X

...

ORG = V

CC

, 8 X’s

ORG = V

SS

, 9 X’s

21130F.book  Page 8  Wednesday, December 5, 2012  2:47 PM

 1996-2012 Microchip Technology Inc.

DS21130F-page 9

93AA76/86

FIGURE 3-4:

EWDS

FIGURE 3-5:

WRITE

FIGURE 3-6:

WRAL

1

0

0

0

0

X

X

...

CS

CLK

DI

T

CSL

ORG = V

CC

, 8 X’s

ORG = V

SS

, 9 X’S

1

0

1

A

N

A

0

...

D

N

...

D

0

T

WC

Ready

Busy

High-impedance

CS

CLK

DI

DO

Standby

T

CZ

Ensured at Vcc = +4.5V to +6.0V.

1

0

0

0

1

X

...

X

D

N

...

D

0

Busy

Ready

High-impedance

Standby

CS

CLK

DI

DO

ORG = V

CC

, 8 X’s

ORG = V

SS

, 9 X’s

T

WL

T

CZ

21130F.book  Page 9  Wednesday, December 5, 2012  2:47 PM

93AA76/86

DS21130F-page 10

 1996-2012 Microchip Technology Inc.

FIGURE 3-7:

ERASE

FIGURE 3-8:

ERAL

1

1

1

A

N

...

A

0

T

CZ

High-impedance

CS

CLK

DI

DO

Standby

Ready

Busy

T

WC

...

Ensured at V

CC

 = +4.5V to +6.0V.

ORG = V

CC

, 8 X’s

ORG = V

SS

, 9 X’s

1

0

0

1

0

X

X

...

CS

CLK

DI

DO

T

EC

T

CZ

High-impedance

Busy

Ready

Standby

21130F.book  Page 10  Wednesday, December 5, 2012  2:47 PM