21127G.book | Datasheet Lookup

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 1995-2012 Microchip Technology Inc.

DS21127G-page 1

24LCS21

Features:

• Completely implements DDC1

™

/DDC2

™

interface

for monitor identification

• Hardware write-protect pin

• Single supply with operation down to 2.5V

• Low-power CMOS technology:

- 1 mA active current, typical

- 10

A standby current, typical at 5.5V

• 2-wire serial interface bus, I

™

compatible (SCL)

• Self-timed write cycle (including auto-erase)

• Page-write buffer for up to 8 bytes

• 100 kHz (2.5V) and 400 kHz (5V) compatibility

(SCL)

• 1,000,000 erase/write cycles ensured

• Data retention > 200 years

• 8-pin PDIP and SOIC package

• Available for extended temperature ranges:

Description:

The Microchip Technology Inc. 24LCS21 is a 128 x 8-bit
dual-mode Electrically Erasable PROM. This device is
designed for use in applications requiring storage and
serial transmission of configuration and control informa-
tion. Two modes of operation have been implemented:
Transmit-Only mode and Bidirectional mode. Upon
power-up, the device will be in the Transmit-Only mode,
sending a serial bit stream of the entire memory array
contents, clocked by the V

CLK

pin. A valid high-to-low

transition on the SCL pin will cause the device to enter
the Bidirectional mode, with byte selectable read/write
capability of the memory array in standard I

C protocol.

The 24LCS21 also enables the user to write-protect the
entire memory contents using its write-protect pin. The
24LCS21 is available in a standard 8-pin PDIP and
SOIC package in both commercial and industrial
temperature ranges.

Package Types

Block Diagram

- Commercial (C):

0°C

to +70°C

- Industrial (I)

-40°C

to +85°C

S21

SOIC

CLK

SCL

SDA

24L

PDIP

CLK

SCL

SDA

I/O

Control

Logic

EEPROM

Array

Page Latches

HV Generator

Sense Amp

R/W Control

Memory

Control

Logic

XDEC

YDEC

SDA SCL

CLK

1K 2.5V Dual Mode I

™

Serial EEPROM

Not recommended for new designs –

Please use 24LCS21A.

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24LCS21

DS21127G-page 2

 1995-2012 Microchip Technology Inc.

1.0

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

(†)

.............................................................................................................................................................................7.0V

All inputs and outputs w.r.t. V

........................................................................................................ -0.6V to V

+ 1.0V

Storage temperature ...............................................................................................................................-65

C to +150C

Ambient temperature with power applied ................................................................................................-40

C to +125C

Soldering temperature of leads (10 seconds) ....................................................................................................... +300

C

ESD protection on all pins

4 kV

TABLE 1-1:

DC CHARACTERISTICS

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.

DC CHARACTERISTICS

= +2.5V to 5.5V

Commercial (C): T

= 0

C to +70C

Industrial (I):

= -40

C to +85C

Parameter

Symbol

Min

Max

Units

Conditions

SCL and SDA pins:

High-level input voltage
Low-level input voltage

0.7 V

0.3 V

V
V

Input levels on V

CLK

pin:

High-level input voltage
Low-level input voltage

2.0

0.8

0.2 V

V
V

 2.7V (Note 1)

< 2.7V (Note 1)

Hysteresis of Schmitt Trigger inputs

HYS

.05 V

—

(Note 1)

Low-level output voltage

0.4

= 3 mA, V

= 2.5V (Note 1)

Low-level output voltage

0.6

= 6 mA, V

= 2.5V

Input leakage current

-10

A

= 0.1V to V

Output leakage current

-10

A

OUT

= 0.1V to V

Pin capacitance (all inputs/outputs)

INT

= 5.0V (Note 1),

= 25

C, F

CLK

= 1 MHz

Operating current

Write

Read

—
—

3
1

mA
mA

= 5.5V, SCL = 400 kHz

Standby current

CCS

—

100

A
A

= 3.0V, SDA = SCL = V

= 5.5V, SDA = SCL = V

CLK

= V

Note 1:

This parameter is periodically sampled and not 100% tested.

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 1995-2012 Microchip Technology Inc.

DS21127G-page 3

24LCS21

TABLE 1-2:

AC CHARACTERISTICS

Parameter

Symbol

= 2.5-5.5V

= 4.5-5.5V

Units

Remarks

Min

Max

Min

Max

Clock frequency

CLK

100

400

kHz

Clock high time

HIGH

4000

—

600

—

Clock low time

LOW

4700

—

1300

—

SDA and SCL rise time

—

1000

—

300

(Note 1)

SDA and SCL fall time

—

300

—

300

(Note 1)

Start condition hold time

STA

4000

—

600

—

After this period the first
clock pulse is generated

Start condition setup time

STA

4700

—

600

—

Only relevant for repeated
Start condition

Data input hold time

DAT

—

(Note 2)

Data input setup time

DAT

250

—

100

—

Stop condition setup time

STO

4000

—

600

—

Output valid from clock

—

3500

—

900

(Note 2)

Bus free time

BUF

4700

—

1300

—

Time the bus must be free
before a new transmission
can start

Output fall time from V

minimum to V

maximum

—

250

20 + 0.1

250

(Note 1), C

100 pF

Input filter spike suppression
(SDA and SCL pins)

—

100

—

(Note 3)

Write cycle time

—

Byte or Page mode

Transmit-Only Mode Parameters

Output valid from V

CLK

VAA

—

2000

—

1000

CLK

high time

VHIGH

4000

—

600

—

CLK

low time

VLOW

4700

—

1300

—

CLK

setup time

VHST

—

CLK

hold time

SPVL

4000

—

600

—

Mode transition time

VHZ

—

500

—

500

Transmit-only power-up time

VPU

—

Input filter spike suppression
(V

CLK

pin)

SPV

—

100

—

100

Endurance

—

cycles

25°C, V

= 5.0V, Block

mode (Note 4)

Note 1:

Not 100% tested. C

= total capacitance of one bus line in pF.

As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

The combined T

and V

HYS

specifications are due to Schmitt Trigger inputs which provide noise and

spike suppression. This eliminates the need for a T

specification for standard operation.

This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance

™

Model which can be obtained from Microchip’s web site

at www.microchip.com.

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24LCS21

DS21127G-page 4

 1995-2012 Microchip Technology Inc.

2.0

FUNCTIONAL DESCRIPTION

The 24LCS21 operates in two modes, the Transmit-
Only mode and the Bidirectional mode. There is a
separate two-wire protocol to support each mode, each
having a separate clock input but sharing a common
data line (SDA). The device enters the Transmit-Only
mode upon power-up. In this mode, the device
transmits data bits on the SDA pin in response to a
clock signal on the V

CLK

pin. The device will remain in

this mode until a valid high-to-low transition is placed
on the SCL input. When a valid transition on SCL is
recognized, the device will switch into the Bidirectional
mode. The only way to switch the device back to the
Transmit-Only mode is to remove power from the
device.

2.1

Transmit-Only Mode

The device will power-up in the Transmit-Only mode at
address 00h. This mode supports a unidirectional two-
wire protocol for continuous transmission of the
contents of the memory array. This device requires that
it be initialized prior to valid data being sent in the

Transmit-Only mode (see Initialization Procedure,
below). In this mode, data is transmitted on the SDA pin
in 8-bit bytes, with each byte followed by a ninth, null bit
(Figure 2-1). The clock source for the Transmit-Only
mode is provided on the V

CLK

pin, and a data bit is out-

put on the rising edge on this pin. The eight bits in each
byte are transmitted Most Significant bit first. Each byte
within the memory array will be output in sequence.
When the last byte in the memory array is transmitted,
the internal Address Pointers will wrap around to the
first memory location (00h) and continue. The
Bidirectional mode clock (SCL) pin must be held high
for the device to remain in the Transmit-Only mode.

2.2

Initialization Procedure

After V

has stabilized, the device will be in the Trans-

mit-Only mode. Nine clock cycles on the V

CLK

pin must

be given to the device for it to perform internal synchro-
nization. During this period, the SDA pin will be in a
high-impedance state. On the rising edge of the tenth
clock cycle, the device will output the first valid data bit
which will be the Most Significant bit in address 00h.
(Figure 2-2).

FIGURE 2-1:

TRANSMIT-ONLY MODE

FIGURE 2-2:

DEVICE INITIALIZATION

SCL

SDA

CLK

VAA

Bit 1 (LSB)

Null Bit

Bit 1 (MSB)

Bit 7

VLOW

VHIGH

VAA

Bit 8

Bit 7

High-impedance for 9 clock cycles

VPU

SCL

SDA

CLK

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 1995-2012 Microchip Technology Inc.

DS21127G-page 5

24LCS21

3.0

BIDIRECTIONAL MODE

The 24LCS21 can be switched into the Bidirectional
mode (Figure 3-1) by applying a valid high-to-low
transition on the Bidirectional mode clock (SCL). When
the device has been switched into the Bidirectional
mode, the V

CLK

input is disregarded, with the exception

that a logic high level is required to enable write capa-
bility. This mode supports a two-wire bidirectional data
transmission protocol (I

™

). In this protocol, a device

that sends data on the bus is defined to be the transmit-
ter and a device that receives data from the bus is
defined to be the receiver. The bus must be controlled
by a master device that generates the Bidirectional
mode clock (SCL), controls access to the bus and gen-
erates the Start and Stop conditions, while the
24LCS21 acts as the slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is activated.

In this mode, the 24LCS21 only responds to
commands for device ‘1010 000X’.

3.1

Bidirectional Mode Bus
Characteristics

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.

Accordingly, the following bus conditions have been
defined (Figure 3-2).

3.1.1

BUS NOT BUSY (A)

Both data and clock lines remain high.

3.1.2

START DATA TRANSFER (B)

A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.

3.1.3

STOP DATA TRANSFER (C)

A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.

FIGURE 3-1:

MODE TRANSITION

FIGURE 3-2:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

SCL

SDA

CLK

Bidirectional mode

VHZ

Transmit-Only mode

(A)

(B)

(D)

(A)

(C)

Start

Condition

Address or

Acknowledge

Valid

Data

Allowed

to Change

Stop

Condition

SCL

SDA

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24LCS21

DS21127G-page 6

 1995-2012 Microchip Technology Inc.

3.1.4

DATA VALID (D)

The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.

The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.

Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is
theoretically unlimited, although only the last eight will
be stored when doing a write operation. When an
overwrite does occur, it will replace data in a first-in
first-out (FIFO) fashion.

3.1.5

ACKNOWLEDGE

Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.

The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an Acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line high to enable
the master to generate the Stop condition.

FIGURE 3-3:

BUS TIMING START/STOP

FIGURE 3-4:

BUS TIMING DATA

Note:

Once switched into Bidirectional mode,
the 24LCS21 will remain in that mode
until power goes away. Removing power
is the only way to reset the 24LCS21 into
the Transmit-Only mode.

Note:

The 24LCS21 does not generate any
Acknowledge bits if an internal
programming cycle is in progress.

STA

HYS

STO

Start

Stop

SCL

SDA

SCL

SDA
IN

SDA
OUT

STA

LOW

HIGH

STA

DAT

STO

BUF

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 1995-2012 Microchip Technology Inc.

DS21127G-page 7

24LCS21

3.1.6

SLAVE ADDRESS

After generating a Start condition, the bus master
transmits the slave address consisting of a 7-bit device
code ‘1010000’ for the 24LCS21.

The eighth bit of the slave address determines whether
the master device wants to read or write to the
24LCS21 (Figure 3-5).

The 24LCS21 monitors the bus for its corresponding
slave address continuously. It generates an
Acknowledge bit if the slave address was true and it is
not in a programming mode.

FIGURE 3-5:

CONTROL BYTE
ALLOCATION

Operation

Slave Address

R/W

Read

1010000

Write

1010000

Slave Address

R/W

Start

Read/Write

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24LCS21

DS21127G-page 8

 1995-2012 Microchip Technology Inc.

4.0

WRITE OPERATION

4.1

Byte Write

Following the Start signal from the master, the slave
address (4 bits), three zero bits (000) and the R/W bit,
which is a logic low, are placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will
follow after it has generated an Acknowledge bit during
the ninth clock cycle. Therefore, the next byte
transmitted by the master is the word address and will
be written into the Address Pointer of the 24LCS21.

After receiving another Acknowledge signal from the
24LCS21, the master device will transmit the data word
to be written into the addressed memory location. The
24LCS21 acknowledges again and the master
generates a Stop condition. This initiates the internal
write cycle, and during this time the 24LCS21 will not
generate Acknowledge signals (Figure 4-1).

It is required that V

CLK

be held at a logic high level

during command and data transfer in order to program
the device. This applies to both byte write and page
write operation. Note, however, that the V

CLK

is ignored

during the self-timed program operation. Changing
V

CLK

from high-to-low during the self-timed program

operation will not halt programming of the device.

FIGURE 4-1:

BYTE WRITE

FIGURE 4-2:

VCLK WRITE ENABLE TIMING

Bus Activity

SDA Line

Bus Activity

Control

Byte

Word

Address

Data

S
T

A
C
K

CLK

Activity

SPVL

STO

STA

VHST

CLK

SDA

SCL

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 1995-2012 Microchip Technology Inc.

DS21127G-page 9

24LCS21

4.2

Page Write

The write control byte, word address and the first data
byte are transmitted to the 24LCS21 in the same way
as in a byte write. But instead of generating a Stop
condition, the master transmits up to eight data bytes to
the 24LCS21, which are temporarily stored in the on-
chip page buffer and will be written into the memory
after the master has transmitted a Stop condition. After
the receipt of each word, the three lower order Address
Pointer bits are internally incremented by one. The
higher order five bits of the word address remains
constant. If the master should transmit more than eight
words prior to generating the Stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the Stop condition is received an
internal write cycle will begin (Figure 5-2).

It is required that V

CLK

be held at a logic high level

during command and data transfer in order to program
the device. This applies to both byte write and page
write operation. Note, however, that the V

CLK

is ignored

during the self-timed program operation. Changing
V

CLK

from high-to-low during the self-timed program

operation will not halt programming of the device.

Note:

Page write operations are limited to writing
bytes within a single physical page,
regardless of the number of bytes actually
being written. Physical page boundaries
start at addresses that are integer
multiples of the page buffer size (or ‘page
size’) and end at addresses that are
integer multiples of [page size – 1]. If a
page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.

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24LCS21

DS21127G-page 10

 1995-2012 Microchip Technology Inc.

5.0

ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition followed by the control byte
for a Write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If the cycle is complete, then the device will return the
ACK and the master can then proceed with the next
Read or Write command. See Figure 5-1 for the flow
diagram.

FIGURE 5-1:

ACKNOWLEDGE
POLLING FLOW

FIGURE 5-2:

PAGE WRITE

Did Device

Acknowledge

(ACK = 0)?

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Operation

Yes

Bus

Master

SDA Line

Bus

Control

Byte

Word

Address

Activity

Data n + 1

Data n + 7

Data (n)

CLK

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 1995-2012 Microchip Technology Inc.

DS21127G-page 1

24LCS21

Features:

• Completely implements DDC1

™

/DDC2

™

interface

for monitor identification

• Hardware write-protect pin

• Single supply with operation down to 2.5V

• Low-power CMOS technology:

- 1 mA active current, typical

- 10

A standby current, typical at 5.5V

• 2-wire serial interface bus, I

™

compatible (SCL)

• Self-timed write cycle (including auto-erase)

• Page-write buffer for up to 8 bytes

• 100 kHz (2.5V) and 400 kHz (5V) compatibility

(SCL)

• 1,000,000 erase/write cycles ensured

• Data retention > 200 years

• 8-pin PDIP and SOIC package

• Available for extended temperature ranges:

Description:

CLK

pin. A valid high-to-low

transition on the SCL pin will cause the device to enter
the Bidirectional mode, with byte selectable read/write
capability of the memory array in standard I

C protocol.

Package Types

Block Diagram

- Commercial (C):

0°C

to +70°C

- Industrial (I)

-40°C

to +85°C

S21

SOIC

CLK

SCL

SDA

24L

PDIP

CLK

SCL

SDA

I/O

Control

Logic

EEPROM

Array

Page Latches

HV Generator

Sense Amp

R/W Control

Memory

Control

Logic

XDEC

YDEC

SDA SCL

CLK

1K 2.5V Dual Mode I

™

Serial EEPROM

Not recommended for new designs –

Please use 24LCS21A.

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24LCS21

DS21127G-page 2

 1995-2012 Microchip Technology Inc.

1.0

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

(†)

.............................................................................................................................................................................7.0V

All inputs and outputs w.r.t. V

........................................................................................................ -0.6V to V

+ 1.0V

Storage temperature ...............................................................................................................................-65

C to +150C

Ambient temperature with power applied ................................................................................................-40

C to +125C

Soldering temperature of leads (10 seconds) ....................................................................................................... +300

C

ESD protection on all pins

TABLE 1-1:

DC CHARACTERISTICS

= +2.5V to 5.5V

Commercial (C): T

= 0

C to +70C

Industrial (I):

= -40

C to +85C

Parameter

Symbol

Min

Max

Units

Conditions

SCL and SDA pins:

High-level input voltage
Low-level input voltage

0.7 V

0.3 V

V
V

Input levels on V

CLK

pin:

High-level input voltage
Low-level input voltage

2.0

0.8

0.2 V

V
V

 2.7V (Note 1)

< 2.7V (Note 1)

Hysteresis of Schmitt Trigger inputs

HYS

.05 V

—

(Note 1)

Low-level output voltage

0.4

= 3 mA, V

= 2.5V (Note 1)

Low-level output voltage

0.6

= 6 mA, V

= 2.5V

Input leakage current

-10

A

= 0.1V to V

Output leakage current

-10

A

OUT

= 0.1V to V

Pin capacitance (all inputs/outputs)

INT

= 5.0V (Note 1),

= 25

C, F

CLK

= 1 MHz

Operating current

Write

Read

—
—

3
1

mA
mA

= 5.5V, SCL = 400 kHz

Standby current

CCS

—

100

A
A

= 3.0V, SDA = SCL = V

= 5.5V, SDA = SCL = V

CLK

= V

Note 1:

This parameter is periodically sampled and not 100% tested.

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 1995-2012 Microchip Technology Inc.

DS21127G-page 3

24LCS21

TABLE 1-2:

AC CHARACTERISTICS

Parameter

Symbol

= 2.5-5.5V

= 4.5-5.5V

Units

Remarks

Min

Max

Min

Max

Clock frequency

CLK

100

400

kHz

Clock high time

HIGH

4000

—

600

—

Clock low time

LOW

4700

—

1300

—

SDA and SCL rise time

—

1000

—

300

(Note 1)

SDA and SCL fall time

—

300

—

300

(Note 1)

Start condition hold time

STA

4000

—

600

—

After this period the first
clock pulse is generated

Start condition setup time

STA

4700

—

600

—

Only relevant for repeated
Start condition

Data input hold time

DAT

—

(Note 2)

Data input setup time

DAT

250

—

100

—

Stop condition setup time

STO

4000

—

600

—

Output valid from clock

—

3500

—

900

(Note 2)

Bus free time

BUF

4700

—

1300

—

Time the bus must be free
before a new transmission
can start

Output fall time from V

minimum to V

maximum

—

250

20 + 0.1

250

(Note 1), C

100 pF

Input filter spike suppression
(SDA and SCL pins)

—

100

—

(Note 3)

Write cycle time

—

Byte or Page mode

Transmit-Only Mode Parameters

Output valid from V

CLK

VAA

—

2000

—

1000

CLK

high time

VHIGH

4000

—

600

—

CLK

low time

VLOW

4700

—

1300

—

CLK

setup time

VHST

—

CLK

hold time

SPVL

4000

—

600

—

Mode transition time

VHZ

—

500

—

500

Transmit-only power-up time

VPU

—

Input filter spike suppression
(V

CLK

pin)

SPV

—

100

—

100

Endurance

—

cycles

25°C, V

= 5.0V, Block

mode (Note 4)

Note 1:

Not 100% tested. C

= total capacitance of one bus line in pF.

The combined T

and V

HYS

specifications are due to Schmitt Trigger inputs which provide noise and

spike suppression. This eliminates the need for a T

specification for standard operation.

This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance

™

Model which can be obtained from Microchip’s web site

at www.microchip.com.

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21127G-html.html

24LCS21

DS21127G-page 4

 1995-2012 Microchip Technology Inc.

2.0

FUNCTIONAL DESCRIPTION

CLK

pin. The device will remain in

2.1

Transmit-Only Mode

CLK

pin, and a data bit is out-

2.2

Initialization Procedure

After V

has stabilized, the device will be in the Trans-

mit-Only mode. Nine clock cycles on the V

CLK

pin must

FIGURE 2-1:

TRANSMIT-ONLY MODE

FIGURE 2-2:

DEVICE INITIALIZATION

SCL

SDA

CLK

VAA

Bit 1 (LSB)

Null Bit

Bit 1 (MSB)

Bit 7

VLOW

VHIGH

VAA

Bit 8

Bit 7

High-impedance for 9 clock cycles

VPU

SCL

SDA

CLK

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 1995-2012 Microchip Technology Inc.

DS21127G-page 5

24LCS21

3.0

BIDIRECTIONAL MODE

CLK

input is disregarded, with the exception

that a logic high level is required to enable write capa-
bility. This mode supports a two-wire bidirectional data
transmission protocol (I

™

). In this protocol, a device

In this mode, the 24LCS21 only responds to
commands for device ‘1010 000X’.

3.1

Bidirectional Mode Bus
Characteristics

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.

Accordingly, the following bus conditions have been
defined (Figure 3-2).

3.1.1

BUS NOT BUSY (A)

Both data and clock lines remain high.

3.1.2

START DATA TRANSFER (B)

A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.

3.1.3

STOP DATA TRANSFER (C)

A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.

FIGURE 3-1:

MODE TRANSITION

FIGURE 3-2:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

SCL

SDA

CLK

Bidirectional mode

VHZ

Transmit-Only mode

(A)

(B)

(D)

(A)

(C)

Start

Condition

Address or

Acknowledge

Valid

Data

Allowed

to Change

Stop

Condition

SCL

SDA

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24LCS21

DS21127G-page 6

 1995-2012 Microchip Technology Inc.

3.1.4

DATA VALID (D)

The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.

The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.

3.1.5

ACKNOWLEDGE

FIGURE 3-3:

BUS TIMING START/STOP

FIGURE 3-4:

BUS TIMING DATA

Note:

Once switched into Bidirectional mode,
the 24LCS21 will remain in that mode
until power goes away. Removing power
is the only way to reset the 24LCS21 into
the Transmit-Only mode.

Note:

The 24LCS21 does not generate any
Acknowledge bits if an internal
programming cycle is in progress.

STA

HYS

STO

Start

Stop

SCL

SDA

SCL

SDA
IN

SDA
OUT

STA

LOW

HIGH

STA

DAT

STO

BUF

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 1995-2012 Microchip Technology Inc.

DS21127G-page 7

24LCS21

3.1.6

SLAVE ADDRESS

After generating a Start condition, the bus master
transmits the slave address consisting of a 7-bit device
code ‘1010000’ for the 24LCS21.

The eighth bit of the slave address determines whether
the master device wants to read or write to the
24LCS21 (Figure 3-5).

The 24LCS21 monitors the bus for its corresponding
slave address continuously. It generates an
Acknowledge bit if the slave address was true and it is
not in a programming mode.

FIGURE 3-5:

CONTROL BYTE
ALLOCATION

Operation

Slave Address

R/W

Read

1010000

Write

1010000

Slave Address

R/W

Start

Read/Write

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24LCS21

DS21127G-page 8

 1995-2012 Microchip Technology Inc.

4.0

WRITE OPERATION

4.1

Byte Write

It is required that V

CLK

be held at a logic high level

during command and data transfer in order to program
the device. This applies to both byte write and page
write operation. Note, however, that the V

CLK

is ignored

during the self-timed program operation. Changing
V

CLK

from high-to-low during the self-timed program

operation will not halt programming of the device.

FIGURE 4-1:

BYTE WRITE

FIGURE 4-2:

VCLK WRITE ENABLE TIMING

Bus Activity

SDA Line

Bus Activity

Control

Byte

Word

Address

Data

S
T

A
C
K

CLK

Activity

SPVL

STO

STA

VHST

CLK

SDA

SCL

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 1995-2012 Microchip Technology Inc.

DS21127G-page 9

24LCS21

4.2

Page Write

It is required that V

CLK

be held at a logic high level

during command and data transfer in order to program
the device. This applies to both byte write and page
write operation. Note, however, that the V

CLK

is ignored

during the self-timed program operation. Changing
V

CLK

from high-to-low during the self-timed program

operation will not halt programming of the device.

Note:

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24LCS21

DS21127G-page 10

 1995-2012 Microchip Technology Inc.

5.0

ACKNOWLEDGE POLLING

FIGURE 5-1:

ACKNOWLEDGE
POLLING FLOW

FIGURE 5-2:

PAGE WRITE

Did Device

Acknowledge

(ACK = 0)?

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Operation

Yes

Bus

Master

SDA Line

Bus

Control

Byte

Word

Address

Activity

Data n + 1

Data n + 7

Data (n)

CLK

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 1995-2012 Microchip Technology Inc.

DS21127G-page 1

24LCS21

Features:

• Completely implements DDC1

™

/DDC2

™

interface

for monitor identification

• Hardware write-protect pin

• Single supply with operation down to 2.5V

• Low-power CMOS technology:

- 1 mA active current, typical

- 10

A standby current, typical at 5.5V

• 2-wire serial interface bus, I

™

compatible (SCL)

• Self-timed write cycle (including auto-erase)

• Page-write buffer for up to 8 bytes

• 100 kHz (2.5V) and 400 kHz (5V) compatibility

(SCL)

• 1,000,000 erase/write cycles ensured

• Data retention > 200 years

• 8-pin PDIP and SOIC package

• Available for extended temperature ranges:

Description:

CLK

pin. A valid high-to-low

transition on the SCL pin will cause the device to enter
the Bidirectional mode, with byte selectable read/write
capability of the memory array in standard I

C protocol.

Package Types

Block Diagram

- Commercial (C):

0°C

to +70°C

- Industrial (I)

-40°C

to +85°C

S21

SOIC

CLK

SCL

SDA

24L

PDIP

CLK

SCL

SDA

I/O

Control

Logic

EEPROM

Array

Page Latches

HV Generator

Sense Amp

R/W Control

Memory

Control

Logic

XDEC

YDEC

SDA SCL

CLK

1K 2.5V Dual Mode I

™

Serial EEPROM

Not recommended for new designs –

Please use 24LCS21A.

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21127G-html.html

24LCS21

DS21127G-page 2

 1995-2012 Microchip Technology Inc.

1.0

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

(†)

.............................................................................................................................................................................7.0V

All inputs and outputs w.r.t. V

........................................................................................................ -0.6V to V

+ 1.0V

Storage temperature ...............................................................................................................................-65

C to +150C

Ambient temperature with power applied ................................................................................................-40

C to +125C

Soldering temperature of leads (10 seconds) ....................................................................................................... +300

C

ESD protection on all pins

TABLE 1-1:

DC CHARACTERISTICS

= +2.5V to 5.5V

Commercial (C): T

= 0

C to +70C

Industrial (I):

= -40

C to +85C

Parameter

Symbol

Min

Max

Units

Conditions

SCL and SDA pins:

High-level input voltage
Low-level input voltage

0.7 V

0.3 V

V
V

Input levels on V

CLK

pin:

High-level input voltage
Low-level input voltage

2.0

0.8

0.2 V

V
V

 2.7V (Note 1)

< 2.7V (Note 1)

Hysteresis of Schmitt Trigger inputs

HYS

.05 V

—

(Note 1)

Low-level output voltage

0.4

= 3 mA, V

= 2.5V (Note 1)

Low-level output voltage

0.6

= 6 mA, V

= 2.5V

Input leakage current

-10

A

= 0.1V to V

Output leakage current

-10

A

OUT

= 0.1V to V

Pin capacitance (all inputs/outputs)

INT

= 5.0V (Note 1),

= 25

C, F

CLK

= 1 MHz

Operating current

Write

Read

—
—

3
1

mA
mA

= 5.5V, SCL = 400 kHz

Standby current

CCS

—

100

A
A

= 3.0V, SDA = SCL = V

= 5.5V, SDA = SCL = V

CLK

= V

Note 1:

This parameter is periodically sampled and not 100% tested.

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 1995-2012 Microchip Technology Inc.

DS21127G-page 3

24LCS21

TABLE 1-2:

AC CHARACTERISTICS

Parameter

Symbol

= 2.5-5.5V

= 4.5-5.5V

Units

Remarks

Min

Max

Min

Max

Clock frequency

CLK

100

400

kHz

Clock high time

HIGH

4000

—

600

—

Clock low time

LOW

4700

—

1300

—

SDA and SCL rise time

—

1000

—

300

(Note 1)

SDA and SCL fall time

—

300

—

300

(Note 1)

Start condition hold time

STA

4000

—

600

—

After this period the first
clock pulse is generated

Start condition setup time

STA

4700

—

600

—

Only relevant for repeated
Start condition

Data input hold time

DAT

—

(Note 2)

Data input setup time

DAT

250

—

100

—

Stop condition setup time

STO

4000

—

600

—

Output valid from clock

—

3500

—

900

(Note 2)

Bus free time

BUF

4700

—

1300

—

Time the bus must be free
before a new transmission
can start

Output fall time from V

minimum to V

maximum

—

250

20 + 0.1

250

(Note 1), C

100 pF

Input filter spike suppression
(SDA and SCL pins)

—

100

—

(Note 3)

Write cycle time

—

Byte or Page mode

Transmit-Only Mode Parameters

Output valid from V

CLK

VAA

—

2000

—

1000

CLK

high time

VHIGH

4000

—

600

—

CLK

low time

VLOW

4700

—

1300

—

CLK

setup time

VHST

—

CLK

hold time

SPVL

4000

—

600

—

Mode transition time

VHZ

—

500

—

500

Transmit-only power-up time

VPU

—

Input filter spike suppression
(V

CLK

pin)

SPV

—

100

—

100

Endurance

—

cycles

25°C, V

= 5.0V, Block

mode (Note 4)

Note 1:

Not 100% tested. C

= total capacitance of one bus line in pF.

The combined T

and V

HYS

specifications are due to Schmitt Trigger inputs which provide noise and

spike suppression. This eliminates the need for a T

specification for standard operation.

This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance

™

Model which can be obtained from Microchip’s web site

at www.microchip.com.

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21127G-html.html

24LCS21

DS21127G-page 4

 1995-2012 Microchip Technology Inc.

2.0

FUNCTIONAL DESCRIPTION

CLK

pin. The device will remain in

2.1

Transmit-Only Mode

CLK

pin, and a data bit is out-

2.2

Initialization Procedure

After V

has stabilized, the device will be in the Trans-

mit-Only mode. Nine clock cycles on the V

CLK

pin must

FIGURE 2-1:

TRANSMIT-ONLY MODE

FIGURE 2-2:

DEVICE INITIALIZATION

SCL

SDA

CLK

VAA

Bit 1 (LSB)

Null Bit

Bit 1 (MSB)

Bit 7

VLOW

VHIGH

VAA

Bit 8

Bit 7

High-impedance for 9 clock cycles

VPU

SCL

SDA

CLK

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 1995-2012 Microchip Technology Inc.

DS21127G-page 5

24LCS21

3.0

BIDIRECTIONAL MODE

CLK

input is disregarded, with the exception

that a logic high level is required to enable write capa-
bility. This mode supports a two-wire bidirectional data
transmission protocol (I

™

). In this protocol, a device

In this mode, the 24LCS21 only responds to
commands for device ‘1010 000X’.

3.1

Bidirectional Mode Bus
Characteristics

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.

Accordingly, the following bus conditions have been
defined (Figure 3-2).

3.1.1

BUS NOT BUSY (A)

Both data and clock lines remain high.

3.1.2

START DATA TRANSFER (B)

A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.

3.1.3

STOP DATA TRANSFER (C)

A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.

FIGURE 3-1:

MODE TRANSITION

FIGURE 3-2:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

SCL

SDA

CLK

Bidirectional mode

VHZ

Transmit-Only mode

(A)

(B)

(D)

(A)

(C)

Start

Condition

Address or

Acknowledge

Valid

Data

Allowed

to Change

Stop

Condition

SCL

SDA

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24LCS21

DS21127G-page 6

 1995-2012 Microchip Technology Inc.

3.1.4

DATA VALID (D)

The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.

The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.

3.1.5

ACKNOWLEDGE

FIGURE 3-3:

BUS TIMING START/STOP

FIGURE 3-4:

BUS TIMING DATA

Note:

Once switched into Bidirectional mode,
the 24LCS21 will remain in that mode
until power goes away. Removing power
is the only way to reset the 24LCS21 into
the Transmit-Only mode.

Note:

The 24LCS21 does not generate any
Acknowledge bits if an internal
programming cycle is in progress.

STA

HYS

STO

Start

Stop

SCL

SDA

SCL

SDA
IN

SDA
OUT

STA

LOW

HIGH

STA

DAT

STO

BUF

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 1995-2012 Microchip Technology Inc.

DS21127G-page 7

24LCS21

3.1.6

SLAVE ADDRESS

After generating a Start condition, the bus master
transmits the slave address consisting of a 7-bit device
code ‘1010000’ for the 24LCS21.

The eighth bit of the slave address determines whether
the master device wants to read or write to the
24LCS21 (Figure 3-5).

The 24LCS21 monitors the bus for its corresponding
slave address continuously. It generates an
Acknowledge bit if the slave address was true and it is
not in a programming mode.

FIGURE 3-5:

CONTROL BYTE
ALLOCATION

Operation

Slave Address

R/W

Read

1010000

Write

1010000

Slave Address

R/W

Start

Read/Write

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24LCS21

DS21127G-page 8

 1995-2012 Microchip Technology Inc.

4.0

WRITE OPERATION

4.1

Byte Write

It is required that V

CLK

be held at a logic high level

during command and data transfer in order to program
the device. This applies to both byte write and page
write operation. Note, however, that the V

CLK

is ignored

during the self-timed program operation. Changing
V

CLK

from high-to-low during the self-timed program

operation will not halt programming of the device.

FIGURE 4-1:

BYTE WRITE

FIGURE 4-2:

VCLK WRITE ENABLE TIMING

Bus Activity

SDA Line

Bus Activity

Control

Byte

Word

Address

Data

S
T

A
C
K

CLK

Activity

SPVL

STO

STA

VHST

CLK

SDA

SCL

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 1995-2012 Microchip Technology Inc.

DS21127G-page 9

24LCS21

4.2

Page Write

It is required that V

CLK

be held at a logic high level

during command and data transfer in order to program
the device. This applies to both byte write and page
write operation. Note, however, that the V

CLK

is ignored

during the self-timed program operation. Changing
V

CLK

from high-to-low during the self-timed program

operation will not halt programming of the device.

Note:

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21127G-html.html

24LCS21

DS21127G-page 10

 1995-2012 Microchip Technology Inc.

5.0

ACKNOWLEDGE POLLING

FIGURE 5-1:

ACKNOWLEDGE
POLLING FLOW

FIGURE 5-2:

PAGE WRITE

Did Device

Acknowledge

(ACK = 0)?

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Operation

Yes

Bus

Master

SDA Line

Bus

Control

Byte

Word

Address

Activity

Data n + 1

Data n + 7

Data (n)

CLK

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21127G-html.html

 1995-2012 Microchip Technology Inc.

DS21127G-page 1

24LCS21

Features:

• Completely implements DDC1

™

/DDC2

™

interface

for monitor identification

• Hardware write-protect pin

• Single supply with operation down to 2.5V

• Low-power CMOS technology:

- 1 mA active current, typical

- 10

A standby current, typical at 5.5V

• 2-wire serial interface bus, I

™

compatible (SCL)

• Self-timed write cycle (including auto-erase)

• Page-write buffer for up to 8 bytes

• 100 kHz (2.5V) and 400 kHz (5V) compatibility

(SCL)

• 1,000,000 erase/write cycles ensured

• Data retention > 200 years

• 8-pin PDIP and SOIC package

• Available for extended temperature ranges:

Description:

CLK

pin. A valid high-to-low

transition on the SCL pin will cause the device to enter
the Bidirectional mode, with byte selectable read/write
capability of the memory array in standard I

C protocol.

Package Types

Block Diagram

- Commercial (C):

0°C

to +70°C

- Industrial (I)

-40°C

to +85°C

S21

SOIC

CLK

SCL

SDA

24L

PDIP

CLK

SCL

SDA

I/O

Control

Logic

EEPROM

Array

Page Latches

HV Generator

Sense Amp

R/W Control

Memory

Control

Logic

XDEC

YDEC

SDA SCL

CLK

1K 2.5V Dual Mode I

™

Serial EEPROM

Not recommended for new designs –

Please use 24LCS21A.

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21127G-html.html

24LCS21

DS21127G-page 2

 1995-2012 Microchip Technology Inc.

1.0

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

(†)

.............................................................................................................................................................................7.0V

All inputs and outputs w.r.t. V

........................................................................................................ -0.6V to V

+ 1.0V

Storage temperature ...............................................................................................................................-65

C to +150C

Ambient temperature with power applied ................................................................................................-40

C to +125C

Soldering temperature of leads (10 seconds) ....................................................................................................... +300

C

ESD protection on all pins

TABLE 1-1:

DC CHARACTERISTICS

= +2.5V to 5.5V

Commercial (C): T

= 0

C to +70C

Industrial (I):

= -40

C to +85C

Parameter

Symbol

Min

Max

Units

Conditions

SCL and SDA pins:

High-level input voltage
Low-level input voltage

0.7 V

0.3 V

V
V

Input levels on V

CLK

pin:

High-level input voltage
Low-level input voltage

2.0

0.8

0.2 V

V
V

 2.7V (Note 1)

< 2.7V (Note 1)

Hysteresis of Schmitt Trigger inputs

HYS

.05 V

—

(Note 1)

Low-level output voltage

0.4

= 3 mA, V

= 2.5V (Note 1)

Low-level output voltage

0.6

= 6 mA, V

= 2.5V

Input leakage current

-10

A

= 0.1V to V

Output leakage current

-10

A

OUT

= 0.1V to V

Pin capacitance (all inputs/outputs)

INT

= 5.0V (Note 1),

= 25

C, F

CLK

= 1 MHz

Operating current

Write

Read

—
—

3
1

mA
mA

= 5.5V, SCL = 400 kHz

Standby current

CCS

—

100

A
A

= 3.0V, SDA = SCL = V

= 5.5V, SDA = SCL = V

CLK

= V

Note 1:

This parameter is periodically sampled and not 100% tested.

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DS21127G-page 3

24LCS21

TABLE 1-2:

AC CHARACTERISTICS

Parameter

Symbol

= 2.5-5.5V

= 4.5-5.5V

Units

Remarks

Min

Max

Min

Max

Clock frequency

CLK

100

400

kHz

Clock high time

HIGH

4000

—

600

—

Clock low time

LOW

4700

—

1300

—

SDA and SCL rise time

—

1000

—

300

(Note 1)

SDA and SCL fall time

—

300

—

300

(Note 1)

Start condition hold time

STA

4000

—

600

—

After this period the first
clock pulse is generated

Start condition setup time

STA

4700

—

600

—

Only relevant for repeated
Start condition

Data input hold time

DAT

—

(Note 2)

Data input setup time

DAT

250

—

100

—

Stop condition setup time

STO

4000

—

600

—

Output valid from clock

—

3500

—

900

(Note 2)

Bus free time

BUF

4700

—

1300

—

Time the bus must be free
before a new transmission
can start

Output fall time from V

minimum to V

maximum

—

250

20 + 0.1

250

(Note 1), C

100 pF

Input filter spike suppression
(SDA and SCL pins)

—

100

—

(Note 3)

Write cycle time

—

Byte or Page mode

Transmit-Only Mode Parameters

Output valid from V

CLK

VAA

—

2000

—

1000

CLK

high time

VHIGH

4000

—

600

—

CLK

low time

VLOW

4700

—

1300

—

CLK

setup time

VHST

—

CLK

hold time

SPVL

4000

—

600

—

Mode transition time

VHZ

—

500

—

500

Transmit-only power-up time

VPU

—

Input filter spike suppression
(V

CLK

pin)

SPV

—

100

—

100

Endurance

—

cycles

25°C, V

= 5.0V, Block

mode (Note 4)

Note 1:

Not 100% tested. C

= total capacitance of one bus line in pF.

The combined T

and V

HYS

specifications are due to Schmitt Trigger inputs which provide noise and

spike suppression. This eliminates the need for a T

specification for standard operation.

This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance

™

Model which can be obtained from Microchip’s web site

at www.microchip.com.

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24LCS21

DS21127G-page 4

 1995-2012 Microchip Technology Inc.

2.0

FUNCTIONAL DESCRIPTION

CLK

pin. The device will remain in

2.1

Transmit-Only Mode

CLK

pin, and a data bit is out-

2.2

Initialization Procedure

After V

has stabilized, the device will be in the Trans-

mit-Only mode. Nine clock cycles on the V

CLK

pin must

FIGURE 2-1:

TRANSMIT-ONLY MODE

FIGURE 2-2:

DEVICE INITIALIZATION

SCL

SDA

CLK

VAA

Bit 1 (LSB)

Null Bit

Bit 1 (MSB)

Bit 7

VLOW

VHIGH

VAA

Bit 8

Bit 7

High-impedance for 9 clock cycles

VPU

SCL

SDA

CLK

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 1995-2012 Microchip Technology Inc.

DS21127G-page 5

24LCS21

3.0

BIDIRECTIONAL MODE

CLK

input is disregarded, with the exception

that a logic high level is required to enable write capa-
bility. This mode supports a two-wire bidirectional data
transmission protocol (I

™

). In this protocol, a device

In this mode, the 24LCS21 only responds to
commands for device ‘1010 000X’.

3.1

Bidirectional Mode Bus
Characteristics

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.

Accordingly, the following bus conditions have been
defined (Figure 3-2).

3.1.1

BUS NOT BUSY (A)

Both data and clock lines remain high.

3.1.2

START DATA TRANSFER (B)

A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.

3.1.3

STOP DATA TRANSFER (C)

A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.

FIGURE 3-1:

MODE TRANSITION

FIGURE 3-2:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

SCL

SDA

CLK

Bidirectional mode

VHZ

Transmit-Only mode

(A)

(B)

(D)

(A)

(C)

Start

Condition

Address or

Acknowledge

Valid

Data

Allowed

to Change

Stop

Condition

SCL

SDA

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24LCS21

DS21127G-page 6

 1995-2012 Microchip Technology Inc.

3.1.4

DATA VALID (D)

The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.

The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.

3.1.5

ACKNOWLEDGE

FIGURE 3-3:

BUS TIMING START/STOP

FIGURE 3-4:

BUS TIMING DATA

Note:

Once switched into Bidirectional mode,
the 24LCS21 will remain in that mode
until power goes away. Removing power
is the only way to reset the 24LCS21 into
the Transmit-Only mode.

Note:

The 24LCS21 does not generate any
Acknowledge bits if an internal
programming cycle is in progress.

STA

HYS

STO

Start

Stop

SCL

SDA

SCL

SDA
IN

SDA
OUT

STA

LOW

HIGH

STA

DAT

STO

BUF

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DS21127G-page 7

24LCS21

3.1.6

SLAVE ADDRESS

After generating a Start condition, the bus master
transmits the slave address consisting of a 7-bit device
code ‘1010000’ for the 24LCS21.

The eighth bit of the slave address determines whether
the master device wants to read or write to the
24LCS21 (Figure 3-5).

The 24LCS21 monitors the bus for its corresponding
slave address continuously. It generates an
Acknowledge bit if the slave address was true and it is
not in a programming mode.

FIGURE 3-5:

CONTROL BYTE
ALLOCATION

Operation

Slave Address

R/W

Read

1010000

Write

1010000

Slave Address

R/W

Start

Read/Write

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24LCS21

DS21127G-page 8

 1995-2012 Microchip Technology Inc.

4.0

WRITE OPERATION

4.1

Byte Write

It is required that V

CLK

be held at a logic high level

during command and data transfer in order to program
the device. This applies to both byte write and page
write operation. Note, however, that the V

CLK

is ignored

during the self-timed program operation. Changing
V

CLK

from high-to-low during the self-timed program

operation will not halt programming of the device.

FIGURE 4-1:

BYTE WRITE

FIGURE 4-2:

VCLK WRITE ENABLE TIMING

Bus Activity

SDA Line

Bus Activity

Control

Byte

Word

Address

Data

S
T

A
C
K

CLK

Activity

SPVL

STO

STA

VHST

CLK

SDA

SCL

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 1995-2012 Microchip Technology Inc.

DS21127G-page 9

24LCS21

4.2

Page Write

It is required that V

CLK

be held at a logic high level

during command and data transfer in order to program
the device. This applies to both byte write and page
write operation. Note, however, that the V

CLK

is ignored

during the self-timed program operation. Changing
V

CLK

from high-to-low during the self-timed program

operation will not halt programming of the device.

Note:

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24LCS21

DS21127G-page 10

 1995-2012 Microchip Technology Inc.

5.0

ACKNOWLEDGE POLLING

FIGURE 5-1:

ACKNOWLEDGE
POLLING FLOW

FIGURE 5-2:

PAGE WRITE

Did Device

Acknowledge

(ACK = 0)?

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Operation

Yes

Bus

Master

SDA Line

Bus

Control

Byte

Word

Address

Activity

Data n + 1

Data n + 7

Data (n)

CLK

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 1995-2012 Microchip Technology Inc.

DS21127G-page 1

24LCS21

Features:

• Completely implements DDC1

™

/DDC2

™

interface

for monitor identification

• Hardware write-protect pin

• Single supply with operation down to 2.5V

• Low-power CMOS technology:

- 1 mA active current, typical

- 10

A standby current, typical at 5.5V

• 2-wire serial interface bus, I

™

compatible (SCL)

• Self-timed write cycle (including auto-erase)

• Page-write buffer for up to 8 bytes

• 100 kHz (2.5V) and 400 kHz (5V) compatibility

(SCL)

• 1,000,000 erase/write cycles ensured

• Data retention > 200 years

• 8-pin PDIP and SOIC package

• Available for extended temperature ranges:

Description:

CLK

pin. A valid high-to-low

transition on the SCL pin will cause the device to enter
the Bidirectional mode, with byte selectable read/write
capability of the memory array in standard I

C protocol.

Package Types

Block Diagram

- Commercial (C):

0°C

to +70°C

- Industrial (I)

-40°C

to +85°C

S21

SOIC

CLK

SCL

SDA

24L

PDIP

CLK

SCL

SDA

I/O

Control

Logic

EEPROM

Array

Page Latches

HV Generator

Sense Amp

R/W Control

Memory

Control

Logic

XDEC

YDEC

SDA SCL

CLK

1K 2.5V Dual Mode I

™

Serial EEPROM

Not recommended for new designs –

Please use 24LCS21A.

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24LCS21

DS21127G-page 2

 1995-2012 Microchip Technology Inc.

1.0

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

(†)

.............................................................................................................................................................................7.0V

All inputs and outputs w.r.t. V

........................................................................................................ -0.6V to V

+ 1.0V

Storage temperature ...............................................................................................................................-65

C to +150C

Ambient temperature with power applied ................................................................................................-40

C to +125C

Soldering temperature of leads (10 seconds) ....................................................................................................... +300

C

ESD protection on all pins

TABLE 1-1:

DC CHARACTERISTICS

= +2.5V to 5.5V

Commercial (C): T

= 0

C to +70C

Industrial (I):

= -40

C to +85C

Parameter

Symbol

Min

Max

Units

Conditions

SCL and SDA pins:

High-level input voltage
Low-level input voltage

0.7 V

0.3 V

V
V

Input levels on V

CLK

pin:

High-level input voltage
Low-level input voltage

2.0

0.8

0.2 V

V
V

 2.7V (Note 1)

< 2.7V (Note 1)

Hysteresis of Schmitt Trigger inputs

HYS

.05 V

—

(Note 1)

Low-level output voltage

0.4

= 3 mA, V

= 2.5V (Note 1)

Low-level output voltage

0.6

= 6 mA, V

= 2.5V

Input leakage current

-10

A

= 0.1V to V

Output leakage current

-10

A

OUT

= 0.1V to V

Pin capacitance (all inputs/outputs)

INT

= 5.0V (Note 1),

= 25

C, F

CLK

= 1 MHz

Operating current

Write

Read

—
—

3
1

mA
mA

= 5.5V, SCL = 400 kHz

Standby current

CCS

—

100

A
A

= 3.0V, SDA = SCL = V

= 5.5V, SDA = SCL = V

CLK

= V

Note 1:

This parameter is periodically sampled and not 100% tested.

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 1995-2012 Microchip Technology Inc.

DS21127G-page 3

24LCS21

TABLE 1-2:

AC CHARACTERISTICS

Parameter

Symbol

= 2.5-5.5V

= 4.5-5.5V

Units

Remarks

Min

Max

Min

Max

Clock frequency

CLK

100

400

kHz

Clock high time

HIGH

4000

—

600

—

Clock low time

LOW

4700

—

1300

—

SDA and SCL rise time

—

1000

—

300

(Note 1)

SDA and SCL fall time

—

300

—

300

(Note 1)

Start condition hold time

STA

4000

—

600

—

After this period the first
clock pulse is generated

Start condition setup time

STA

4700

—

600

—

Only relevant for repeated
Start condition

Data input hold time

DAT

—

(Note 2)

Data input setup time

DAT

250

—

100

—

Stop condition setup time

STO

4000

—

600

—

Output valid from clock

—

3500

—

900

(Note 2)

Bus free time

BUF

4700

—

1300

—

Time the bus must be free
before a new transmission
can start

Output fall time from V

minimum to V

maximum

—

250

20 + 0.1

250

(Note 1), C

100 pF

Input filter spike suppression
(SDA and SCL pins)

—

100

—

(Note 3)

Write cycle time

—

Byte or Page mode

Transmit-Only Mode Parameters

Output valid from V

CLK

VAA

—

2000

—

1000

CLK

high time

VHIGH

4000

—

600

—

CLK

low time

VLOW

4700

—

1300

—

CLK

setup time

VHST

—

CLK

hold time

SPVL

4000

—

600

—

Mode transition time

VHZ

—

500

—

500

Transmit-only power-up time

VPU

—

Input filter spike suppression
(V

CLK

pin)

SPV

—

100

—

100

Endurance

—

cycles

25°C, V

= 5.0V, Block

mode (Note 4)

Note 1:

Not 100% tested. C

= total capacitance of one bus line in pF.

The combined T

and V

HYS

specifications are due to Schmitt Trigger inputs which provide noise and

spike suppression. This eliminates the need for a T

specification for standard operation.

This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance

™

Model which can be obtained from Microchip’s web site

at www.microchip.com.

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24LCS21

DS21127G-page 4

 1995-2012 Microchip Technology Inc.

2.0

FUNCTIONAL DESCRIPTION

CLK

pin. The device will remain in

2.1

Transmit-Only Mode

CLK

pin, and a data bit is out-

2.2

Initialization Procedure

After V

has stabilized, the device will be in the Trans-

mit-Only mode. Nine clock cycles on the V

CLK

pin must

FIGURE 2-1:

TRANSMIT-ONLY MODE

FIGURE 2-2:

DEVICE INITIALIZATION

SCL

SDA

CLK

VAA

Bit 1 (LSB)

Null Bit

Bit 1 (MSB)

Bit 7

VLOW

VHIGH

VAA

Bit 8

Bit 7

High-impedance for 9 clock cycles

VPU

SCL

SDA

CLK

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 1995-2012 Microchip Technology Inc.

DS21127G-page 5

24LCS21

3.0

BIDIRECTIONAL MODE

CLK

input is disregarded, with the exception

that a logic high level is required to enable write capa-
bility. This mode supports a two-wire bidirectional data
transmission protocol (I

™

). In this protocol, a device

In this mode, the 24LCS21 only responds to
commands for device ‘1010 000X’.

3.1

Bidirectional Mode Bus
Characteristics

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.

Accordingly, the following bus conditions have been
defined (Figure 3-2).

3.1.1

BUS NOT BUSY (A)

Both data and clock lines remain high.

3.1.2

START DATA TRANSFER (B)

A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.

3.1.3

STOP DATA TRANSFER (C)

A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.

FIGURE 3-1:

MODE TRANSITION

FIGURE 3-2:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

SCL

SDA

CLK

Bidirectional mode

VHZ

Transmit-Only mode

(A)

(B)

(D)

(A)

(C)

Start

Condition

Address or

Acknowledge

Valid

Data

Allowed

to Change

Stop

Condition

SCL

SDA

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24LCS21

DS21127G-page 6

 1995-2012 Microchip Technology Inc.

3.1.4

DATA VALID (D)

The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.

The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.

3.1.5

ACKNOWLEDGE

FIGURE 3-3:

BUS TIMING START/STOP

FIGURE 3-4:

BUS TIMING DATA

Note:

Once switched into Bidirectional mode,
the 24LCS21 will remain in that mode
until power goes away. Removing power
is the only way to reset the 24LCS21 into
the Transmit-Only mode.

Note:

The 24LCS21 does not generate any
Acknowledge bits if an internal
programming cycle is in progress.

STA

HYS

STO

Start

Stop

SCL

SDA

SCL

SDA
IN

SDA
OUT

STA

LOW

HIGH

STA

DAT

STO

BUF

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 1995-2012 Microchip Technology Inc.

DS21127G-page 7

24LCS21

3.1.6

SLAVE ADDRESS

After generating a Start condition, the bus master
transmits the slave address consisting of a 7-bit device
code ‘1010000’ for the 24LCS21.

The eighth bit of the slave address determines whether
the master device wants to read or write to the
24LCS21 (Figure 3-5).

The 24LCS21 monitors the bus for its corresponding
slave address continuously. It generates an
Acknowledge bit if the slave address was true and it is
not in a programming mode.

FIGURE 3-5:

CONTROL BYTE
ALLOCATION

Operation

Slave Address

R/W

Read

1010000

Write

1010000

Slave Address

R/W

Start

Read/Write

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24LCS21

DS21127G-page 8

 1995-2012 Microchip Technology Inc.

4.0

WRITE OPERATION

4.1

Byte Write

It is required that V

CLK

be held at a logic high level

during command and data transfer in order to program
the device. This applies to both byte write and page
write operation. Note, however, that the V

CLK

is ignored

during the self-timed program operation. Changing
V

CLK

from high-to-low during the self-timed program

operation will not halt programming of the device.

FIGURE 4-1:

BYTE WRITE

FIGURE 4-2:

VCLK WRITE ENABLE TIMING

Bus Activity

SDA Line

Bus Activity

Control

Byte

Word

Address

Data

S
T

A
C
K

CLK

Activity

SPVL

STO

STA

VHST

CLK

SDA

SCL

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 1995-2012 Microchip Technology Inc.

DS21127G-page 9

24LCS21

4.2

Page Write

It is required that V

CLK

be held at a logic high level

during command and data transfer in order to program
the device. This applies to both byte write and page
write operation. Note, however, that the V

CLK

is ignored

during the self-timed program operation. Changing
V

CLK

from high-to-low during the self-timed program

operation will not halt programming of the device.

Note:

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24LCS21

DS21127G-page 10

 1995-2012 Microchip Technology Inc.

5.0

ACKNOWLEDGE POLLING

FIGURE 5-1:

ACKNOWLEDGE
POLLING FLOW

FIGURE 5-2:

PAGE WRITE

Did Device

Acknowledge

(ACK = 0)?

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Operation

Yes

Bus

Master

SDA Line

Bus

Control

Byte

Word

Address

Activity

Data n + 1

Data n + 7

Data (n)

CLK

Maker

Microchip Technology Inc.

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