21101H.book | Datasheet Lookup

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

2004 Microchip Technology Inc.

DS21101H-page 1

FEATURES

• Single supply with operation down to 2.5V
• 16 bytes OTP Secure Memory
• Low power CMOS technology

- 1 mA active current typical
- 10

A standby current typical at 5.5V

- 5

A standby current typical at 3.0V

• Organized as eight blocks of 256 bytes (8 x 256 x 8)
• 2-wire serial interface bus, I



compatible

• Functional address inputs for cascading up to 8

devices

• Schmitt trigger, filtered inputs for noise suppression
• Output slope control to eliminate ground bounce
• 100 kHz (2.5V) and 400 kHz (5V) compatibility
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 16 bytes
• 2 ms typical write cycle time for page-write
• Hardware write protect for entire memory
• Can be operated as a serial ROM
• Factory programming (QTP) available
• ESD protection > 4,000V
• 1,000,000 Erase/Write cycles guaranteed
• Data retention > 200 years
• 8-pin DIP, 8-lead SOIC packages
• Available temperature ranges:

DESCRIPTION

The Microchip Technology Inc. 24LC174 is a cascad-
able 16K bit Electrically Erasable PROM. The device is
organized as eight blocks of 256 x 8-bit memory with a
2-wire serial interface and provides a specially
addressed OTP (one-time programmable) 16 byte
security block. Low voltage design permits operation
down to 2.5 volts with standby and active currents of
only 5

A and 1 mA respectively. The 24LC174 also

has a page-write capability for up to 16 bytes of data.
The 24LC174 is available in the standard 8-pin DIP and
8-lead surface mount SOIC packages.

The three select pins, A0, A1, and A2, function as chip
select inputs and allow up to eight devices to share a
common bus, for up to 128K bits total system
EEPROM.

- Commercial (C):

0°C to +70°C

- Industrial (I):

-40° to

+85°

PACKAGE TYPES

BLOCK DIAGRAM

24
LC
17
4

SCL

SDA

24L

C174

SCL

SDA

PDIP

8-lead
SOIC

HV GENERATOR

EEPROM ARRAY

(8 x 256 x 8)

PAGE LATCHES

YDEC

XDEC

SENSE AMP

R/W CONTROL

MEMORY

CONTROL

LOGIC

I/O

CONTROL

LOGIC

SDA

SCL

24LC174

16K 2.5V Cascadable I

™

Serial EEPROM with OTP Security Page

C is a trademark of Philips Corporation.

Obsolete Device

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24LC174

DS21101H-page 2

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2004 Microchip Technology Inc.

1.0

ELECTRICAL CHARACTERISTICS

1.1

Maximum Ratings*

...................................................................................7.0V

All inputs and outputs w.r.t. V

................ -0.3V to Vcc +1.0V

Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-65°C to +125°C
Soldering temperature of leads (10 seconds) ............. +300°C
ESD protection on all pins

..................................................≥

4 kV

*Notice: Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

TABLE 1-1:

PIN FUNCTION TABLE

Name

Function

Ground

SDA

Serial Address/Data I/O

SCL

Serial Clock

Write Protect Input

+2.5V to 5.5V Power Supply

A0, A1, A2

Chip Address Inputs

TABLE 1-2:

DC CHARACTERISTICS

FIGURE 1-1:

BUS TIMING START/STOP

Vcc = +2.5V to 5.5V
Commercial

(C):

Tamb = 0°C to +70°C

Industrial

(I):

Tamb = -40°C to +85°C

Parameter

Symbol

Min

Max

Units

Conditions

WP, SCL and SDA pins:

High level input voltage
Low level input voltage
Hysteresis of Schmitt trigger inputs
Low level output voltage

HYS

.7 V

—

.05 V

—

.3 V

—

.40

V
V
V
V

(Note)
I

= 3.0 mA, V

= 2.5V

Input leakage current

-10

= .1V to V

Output leakage current

-10

OUT

= .1V to V

Pin capacitance (all inputs/outputs)

, C

OUT

—

= 5.0V (Note1),

Tamb = 25

C, F

CLK

= 1 MHz

Operating current

Write

Read

—
—

3
1

mA
mA

= 5.5V, SCL = 400 kHz

Standby current

CCS

—
—

100

= 3.0V, SDA = SCL = V

= 5.5V, SDA = SCL = V

WP = V

Note:This parameter is periodically sampled and not 100% tested.

STA

HYS

STO

START

STOP

SCL

SDA

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2004 Microchip Technology Inc.

DS21101H-page 3

24LC174

TABLE 1-3:

AC CHARACTERISTICS

FIGURE 1-2:

BUS TIMING DATA

Parameter

Symbol

Standard Mode

Vcc= 4.5 - 5.5V

Fast Mode

Units

Remarks

Min

Max

Min

Max

Clock frequency

CLK

—

100

—

400

kHz

Clock high time

HIGH

4000

—

600

—

Clock low time

LOW

4700

—

1300

—

SDA and SCL rise time

—

1000

—

300

(Note 1)

SDA and SCL fall time

—

300

—

300

(Note 1)

START condition hold time

STA

4000

—

600

—

After this period the first clock
pulse is generated

START condition setup
time

STA

4700

—

600

—

Only relevant for repeated
START condition

Data input hold time

DAT

—

Data input setup time

DAT

250

—

100

—

STOP condition setup time

STO

4000

—

600

—

Output valid from clock

—

3500

—

900

(Note 2)

Bus free time

BUF

4700

—

1300

—

Time the bus must be free
before a new transmission can
start

Output fall time from V

min to V

max

—

250

20 +0.1

250

(Note 1), C

≤

100 pF

Input filter spike suppres-
sion (SDA and SCL pins)

—

(Note 3)

Write cycle time

—

Byte or Page mode

Endurance

—

cycles

25°C, Vcc = 5.0V, Block Mode
(Note 4)

Note 1: Not 100% tested. C

= total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3: The combined T

and V

HYS

specifications are due to new Schmitt trigger inputs which provide improved

noise and spike suppression. This eliminates the need for a T

specification for standard operation.

4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-

cation, please consult the Total Endurance Model which can be obtained on our website.

SCL

SDA
IN

SDA
OUT

STA

LOW

HIGH

STA

DAT

STO

BUF

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24LC174

DS21101H-page 4

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2004 Microchip Technology Inc.

2.0

FUNCTIONAL DESCRIPTION

The 24LC174 supports a Bi-directional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCL), controls the bus access, and generates the
START and STOP conditions, while the 24LC174
works as slave. Both, master and slave can operate as
transmitter or receiver but the master device deter-
mines which mode is activated.

3.0

BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been
defined (Figure 3-1).

3.1

Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2

Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.

3.3

Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.

3.4

Data Valid (D)

The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.

Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last 16
will be stored when doing a write operation. When an
overwrite does occur it will replace data in a first in first
out fashion.

3.5

Acknowledge

Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.

The device that acknowledges, has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the slave by not generating an acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (24LC174) will leave the data line
HIGH to enable the master to generate the STOP con-
dition.

Note:

The 24LC174 does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.

FIGURE 3-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

SCL

SDA

(A)

(B)

(D)

(A)

(C)

START

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

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2004 Microchip Technology Inc.

DS21101H-page 5

24LC174

3.6

Device Addressing and Operation

A control byte is the first byte received following the
start condition from the master device. The first bit is
always a one.  The next three bits of the control byte
are the device select bits (A2, A1, A0).  They are used
to select which of the eight devices are to be accessed.
The A1 bit must be the inverse of the A1 device select
pin.

The next three bits of the control byte are the block
select bits (B2, B1, B0). They are used by the master
device to select which of the eight 256 word blocks of
memory are to be accessed. These bits are in effect
the three most significant bits of the word address.

The last bit of the control byte defines the operation to
be performed. When set to one a read operation is
selected, when set to zero a write operation is selected.
Following the start condition, the 24LC174 looks for the
slave address for the device selected. Depending on
the state of the R/W bit, the 24LC174 will select a read
or write operation.

FIGURE 3-2:

CONTROL BYTE
ALLOCATION

Operation

Control Code

Block Select

R/W

Read

A2 A1 A0 Block Address

Write

A2 A1 A0 Block Address

SLAVE ADDRESS

R/W A

START

READ/WRITE

MSB

LSB

4.0

WRITE OPERATION

4.1

Byte Write

Following the start condition from the master, the
device code (4 bits), the block address (3 bits), and the
R/W bit which is a logic low is placed onto the bus by
the master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will fol-
low after it has generated an acknowledge bit during
the ninth clock cycle. Therefore the next byte transmit-
ted by the master is the word address and will be writ-
ten into the address pointer of the 24LC174. After
receiving another acknowledge signal from the
24LC174 the master device will transmit the data word
to be written into the addressed memory location. The
24LC174 acknowledges again and the master gener-
ates a stop condition. This initiates the internal write
cycle, and during this time the 24LC174 will not gener-
ate acknowledge signals (Figure 4-1).

4.2

Page Write

The write control byte, word address and the first data
byte are transmitted to the 24LC174 in the same way
as in a byte write. But instead of generating a stop con-
dition the master transmits up to 16 data bytes to the
24LC174 which are temporarily stored in the on-chip
page buffer and will be written into the memory after the
master has transmitted a stop condition. After the
receipt of each word, the four lower order address
pointer bits are internally incremented by one. The
higher order seven bits of the word address remains
constant. If the master should transmit more than 16
words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (Figure 7.3).

Note:

Page write operations are limited to writing
bytes within a single physical page,
regardless of the number of bytes actually
being written. Physical page boundaries
start at addresses that are integer multiples
of the page buffer size (or ‘page size’) and
end at addresses that are integer multiples
of [page size - 1]. If a page write command
attempts to write across a physical page
boundary, the result is that the data wraps
around to the beginning of the current page
(overwriting data previously stored there),
instead of being written to the next page as
might be expected. It is therefore neces-
sary for the application software to prevent
page write operations that would attempt to
cross a page boundary.

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24LC174

DS21101H-page 6

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2004 Microchip Technology Inc.

FIGURE 4-1:

BYTE WRITE

FIGURE 4-2:

PAGE WRITE

S
T
O
P

SDA LINE

DATA

S
T
A
R
T

CONTROL

BYTE

WORD

ADDRESS

BUS ACTIVITY:
MASTER

BUS ACTIVITY:

A
C
K

1 A2

A1 A0 B2 B1

S
T
O
P

SDA LINE

DATA n

S
T
A
R
T

CONTROL

BYTE

WORD

ADDRESS (n)

BUS ACTIVITY:
MASTER

BUS ACTIVITY:

A
C
K

DATA n + 1

A
C
K

DATA n + 15

A
C
K

A1 A0 B2 B1

5.0

ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send-
ing a start condition followed by the control byte for a
write command (R/W = 0). If the device is still busy with
the write cycle, then no ACK will be returned. If the
cycle is complete, then the device will return the ACK
and the master can then proceed with the next read or
write command. See Figure 5-1 for flow diagram.

FIGURE 5-1:

ACKNOWLEDGE POLLING
FLOW

6.0

WRITE PROTECTION

The 24LC174 can be used as a serial ROM when the
WP pin is connected to Vcc. Programming will be inhib-
ited and the entire memory will be write-protected.

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

Operation

YES

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2004 Microchip Technology Inc.

DS21101H-page 7

24LC174

7.0

READ OPERATION

Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random
read, and sequential read.

7.1

Current Address Read

The 24LC174 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous access
(either a read or write operation) was to address n, the
next current address read operation would access data
from address n + 1. Upon receipt of the slave address
with R/W bit set to one, the 24LC174 issues an
acknowledge and transmits the 8-bit data word. The
master will not acknowledge the transfer but does gen-
erate a stop condition and the 24LC174 discontinues
transmission (Figure 8-1).

7.2

Random Read

Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24LC174 as part of a write operation. After the word
address is sent, the master generates a start condition
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is
set. Then the master issues the control byte again but
with the R/W bit set to a one. The 24LC174 will then
issue an acknowledge and transmits the 8-bit data
word. The master will not acknowledge the transfer but
does generate a stop condition and the 24LC174 dis-
continues transmission (Figure 8-2).

7.3

Sequential Read

Sequential reads are initiated in the same way as a ran-
dom read except that after the 24LC174 transmits the
first data byte, the master issues an acknowledge as
opposed to a stop condition in a random read. This
directs the 24LC174 to transmit the next sequentially
addressed 8-bit word (Figure 8-3).

To provide sequential reads the 24LC174 contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows an entire device memory contents to be serially
read during one operation.

7.4

Noise Protection

The 24LC174 employs a Vcc threshold detector circuit
which disables the internal erase/write logic if the V

is below 1.5 volts at nominal conditions.

The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.

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24LC174

DS21101H-page 8

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2004 Microchip Technology Inc.

8.0

PIN DESCRIPTIONS

8.1

SDA Serial Address/Data Input/Output

This is a Bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pullup
resistor to V

(typical 10K

Ω

for 100 kHz, 2 K

Ω

for

400 kHz).

For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi-
tions.

8.2

SCL Serial Clock

This input is used to synchronize the data transfer from
and to the device.

8.3

This pin must be connected to either V

or V

If tied to V

, normal memory operation is enabled

(read/write the entire memory 000-7FF).

If tied to V

, WRITE operations are inhibited. The

entire memory will be write-protected. Read operations
are not affected.

This feature allows the user to use the 24LC174 as a
serial ROM when WP is enabled (tied to Vcc).

8.4

A0, A1, A2

These pins are used to configure the proper chip
address in multiple-chip applications (more than one
24LC174 on the same bus). The levels on these pins
are compared to the corresponding bits in the slave
address. The chip is selected if the compare is true.

Up to eight 24LC174s may be connected to the same
bus. These pins must be connected to either V

Note:

The level on A1 is compared to the inverse
of the slave address.

8.5

Security Access Control

The security row is enabled by sending the control
sequence with the I

C slave address of 0110. Bit 0 of

the control byte must be set to a one for a READ
OPERATION or a zero for the OTP WRITE OPERA-
TION. The SECURITY ACCESS DATA is always read
starting at byte 0 for N bytes up to and including byte
15. (See Figure 8-3).

8.6

Security Access Write

The S.A.W. data is written to the device using a normal
page write following the proper control access
sequence. Upon receiving the final stop bit, the internal
write sequence will commence. At the completion of
the internal write sequence a fuse will be set disabling
the write function for the 16 byte security page.

8.7

Security Access Read

The security access read is accomplished by executing
the normal read sequences, following the security
access control sequence with bit 0 set to a one. The
security page read starts at data byte 0.

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2004 Microchip Technology Inc.

DS21101H-page 9

24LC174

FIGURE 8-1:

CURRENT ADDRESS READ

FIGURE 8-2:

RANDOM READ

FIGURE 8-3:

SEQUENTIAL READ

FIGURE 8-4:

SECURITY CONTROL BYTE ALLOCATION

CONTROL

BYTE

DATA n

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

A
C
K

1 A2 A1 A0 B2 B1 B0

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

S
T
O
P

CONTROL

BYTE

C
K

WORD

ADDRESS (n)

CONTROL

BYTE

S
T
A
R
T

DATA (n)

C
K

A
C
K

1 A2 A1A0B2B1B0

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
O
P

CONTROL

BYTE

A
C
K

N
O

DATA n

DATA n + 1

DATA n + 2

DATA n + X

A
C
K

Operation

Control Code

Block

Select

R/W

Read

0110

000

Write

0110

000

START

READ/WRITE

SLAVE ADDRESS

R/W

MSB

LSB

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24LC174

DS21101H-page 10

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2004 Microchip Technology Inc.

FIGURE 8-5:

SECURITY PAGE READ

FIGURE 8-6:

SECURITY PAGE WRITE

CONTROL

BYTE

S 0 1 1 0

R/W

WORD

ADDRESS (n)

CONTROL

BYTE

DATA 0

A
R

R/W

A
C
K

BUS MASTER
ACTIVITY

SDA LINE

BUS ACTIVITY

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
O
P

DATA 1

DATA 2

DATA 3

DATA 15

A
C
K

CONTROL

S
T
A

BYTE

S 0 1 1 0

R/W

WORD

ADDRESS (n)

BUS MASTER
ACTIVITY

SDA LINE

BUS ACTIVITY

DATA (n)

DATA n + 1

DATA n + 15

S
T
O
P

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2004 Microchip Technology Inc.

DS21101H-page 1

FEATURES

• Single supply with operation down to 2.5V
• 16 bytes OTP Secure Memory
• Low power CMOS technology

- 1 mA active current typical
- 10

A standby current typical at 5.5V

- 5

A standby current typical at 3.0V

• Organized as eight blocks of 256 bytes (8 x 256 x 8)
• 2-wire serial interface bus, I



compatible

• Functional address inputs for cascading up to 8

devices

DESCRIPTION

A and 1 mA respectively. The 24LC174 also

has a page-write capability for up to 16 bytes of data.
The 24LC174 is available in the standard 8-pin DIP and
8-lead surface mount SOIC packages.

The three select pins, A0, A1, and A2, function as chip
select inputs and allow up to eight devices to share a
common bus, for up to 128K bits total system
EEPROM.

- Commercial (C):

0°C to +70°C

- Industrial (I):

-40° to

+85°

PACKAGE TYPES

BLOCK DIAGRAM

24
LC
17
4

SCL

SDA

24L

C174

SCL

SDA

PDIP

8-lead
SOIC

HV GENERATOR

EEPROM ARRAY

(8 x 256 x 8)

PAGE LATCHES

YDEC

XDEC

SENSE AMP

R/W CONTROL

MEMORY

CONTROL

LOGIC

I/O

CONTROL

LOGIC

SDA

SCL

24LC174

16K 2.5V Cascadable I

™

Serial EEPROM with OTP Security Page

C is a trademark of Philips Corporation.

Obsolete Device

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24LC174

DS21101H-page 2

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2004 Microchip Technology Inc.

1.0

ELECTRICAL CHARACTERISTICS

1.1

Maximum Ratings*

...................................................................................7.0V

All inputs and outputs w.r.t. V

................ -0.3V to Vcc +1.0V

..................................................≥

4 kV

TABLE 1-1:

PIN FUNCTION TABLE

Name

Function

Ground

SDA

Serial Address/Data I/O

SCL

Serial Clock

Write Protect Input

+2.5V to 5.5V Power Supply

A0, A1, A2

Chip Address Inputs

TABLE 1-2:

DC CHARACTERISTICS

FIGURE 1-1:

BUS TIMING START/STOP

Vcc = +2.5V to 5.5V
Commercial

(C):

Tamb = 0°C to +70°C

Industrial

(I):

Tamb = -40°C to +85°C

Parameter

Symbol

Min

Max

Units

Conditions

WP, SCL and SDA pins:

High level input voltage
Low level input voltage
Hysteresis of Schmitt trigger inputs
Low level output voltage

HYS

.7 V

—

.05 V

—

.3 V

—

.40

V
V
V
V

(Note)
I

= 3.0 mA, V

= 2.5V

Input leakage current

-10

= .1V to V

Output leakage current

-10

OUT

= .1V to V

Pin capacitance (all inputs/outputs)

, C

OUT

—

= 5.0V (Note1),

Tamb = 25

C, F

CLK

= 1 MHz

Operating current

Write

Read

—
—

3
1

mA
mA

= 5.5V, SCL = 400 kHz

Standby current

CCS

—
—

100

= 3.0V, SDA = SCL = V

= 5.5V, SDA = SCL = V

WP = V

Note:This parameter is periodically sampled and not 100% tested.

STA

HYS

STO

START

STOP

SCL

SDA

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2004 Microchip Technology Inc.

DS21101H-page 3

24LC174

TABLE 1-3:

AC CHARACTERISTICS

FIGURE 1-2:

BUS TIMING DATA

Parameter

Symbol

Standard Mode

Vcc= 4.5 - 5.5V

Fast Mode

Units

Remarks

Min

Max

Min

Max

Clock frequency

CLK

—

100

—

400

kHz

Clock high time

HIGH

4000

—

600

—

Clock low time

LOW

4700

—

1300

—

SDA and SCL rise time

—

1000

—

300

(Note 1)

SDA and SCL fall time

—

300

—

300

(Note 1)

START condition hold time

STA

4000

—

600

—

After this period the first clock
pulse is generated

START condition setup
time

STA

4700

—

600

—

Only relevant for repeated
START condition

Data input hold time

DAT

—

Data input setup time

DAT

250

—

100

—

STOP condition setup time

STO

4000

—

600

—

Output valid from clock

—

3500

—

900

(Note 2)

Bus free time

BUF

4700

—

1300

—

Time the bus must be free
before a new transmission can
start

Output fall time from V

min to V

max

—

250

20 +0.1

250

(Note 1), C

≤

100 pF

Input filter spike suppres-
sion (SDA and SCL pins)

—

(Note 3)

Write cycle time

—

Byte or Page mode

Endurance

—

cycles

25°C, Vcc = 5.0V, Block Mode
(Note 4)

Note 1: Not 100% tested. C

= total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3: The combined T

and V

HYS

specifications are due to new Schmitt trigger inputs which provide improved

noise and spike suppression. This eliminates the need for a T

specification for standard operation.

4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-

cation, please consult the Total Endurance Model which can be obtained on our website.

SCL

SDA
IN

SDA
OUT

STA

LOW

HIGH

STA

DAT

STO

BUF

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24LC174

DS21101H-page 4



2004 Microchip Technology Inc.

2.0

FUNCTIONAL DESCRIPTION

3.0

BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been
defined (Figure 3-1).

3.1

Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2

Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.

3.3

Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.

3.4

Data Valid (D)

The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.

3.5

Acknowledge

Note:

The 24LC174 does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.

FIGURE 3-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

SCL

SDA

(A)

(B)

(D)

(A)

(C)

START

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

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2004 Microchip Technology Inc.

DS21101H-page 5

24LC174

3.6

Device Addressing and Operation

FIGURE 3-2:

CONTROL BYTE
ALLOCATION

Operation

Control Code

Block Select

R/W

Read

A2 A1 A0 Block Address

Write

A2 A1 A0 Block Address

SLAVE ADDRESS

R/W A

START

READ/WRITE

MSB

LSB

4.0

WRITE OPERATION

4.1

Byte Write

4.2

Page Write

Note:

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24LC174

DS21101H-page 6



2004 Microchip Technology Inc.

FIGURE 4-1:

BYTE WRITE

FIGURE 4-2:

PAGE WRITE

S
T
O
P

SDA LINE

DATA

S
T
A
R
T

CONTROL

BYTE

WORD

ADDRESS

BUS ACTIVITY:
MASTER

BUS ACTIVITY:

A
C
K

1 A2

A1 A0 B2 B1

S
T
O
P

SDA LINE

DATA n

S
T
A
R
T

CONTROL

BYTE

WORD

ADDRESS (n)

BUS ACTIVITY:
MASTER

BUS ACTIVITY:

A
C
K

DATA n + 1

A
C
K

DATA n + 15

A
C
K

A1 A0 B2 B1

5.0

ACKNOWLEDGE POLLING

FIGURE 5-1:

ACKNOWLEDGE POLLING
FLOW

6.0

WRITE PROTECTION

The 24LC174 can be used as a serial ROM when the
WP pin is connected to Vcc. Programming will be inhib-
ited and the entire memory will be write-protected.

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

Operation

YES

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2004 Microchip Technology Inc.

DS21101H-page 7

24LC174

7.0

READ OPERATION

7.1

Current Address Read

7.2

Random Read

7.3

Sequential Read

7.4

Noise Protection

The 24LC174 employs a Vcc threshold detector circuit
which disables the internal erase/write logic if the V

is below 1.5 volts at nominal conditions.

The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.

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24LC174

DS21101H-page 8



2004 Microchip Technology Inc.

8.0

PIN DESCRIPTIONS

8.1

SDA Serial Address/Data Input/Output

This is a Bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pullup
resistor to V

(typical 10K

Ω

for 100 kHz, 2 K

Ω

for

400 kHz).

For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi-
tions.

8.2

SCL Serial Clock

This input is used to synchronize the data transfer from
and to the device.

8.3

This pin must be connected to either V

or V

If tied to V

, normal memory operation is enabled

(read/write the entire memory 000-7FF).

If tied to V

, WRITE operations are inhibited. The

entire memory will be write-protected. Read operations
are not affected.

This feature allows the user to use the 24LC174 as a
serial ROM when WP is enabled (tied to Vcc).

8.4

A0, A1, A2

Up to eight 24LC174s may be connected to the same
bus. These pins must be connected to either V

Note:

The level on A1 is compared to the inverse
of the slave address.

8.5

Security Access Control

The security row is enabled by sending the control
sequence with the I

C slave address of 0110. Bit 0 of

8.6

Security Access Write

8.7

Security Access Read

The security access read is accomplished by executing
the normal read sequences, following the security
access control sequence with bit 0 set to a one. The
security page read starts at data byte 0.

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2004 Microchip Technology Inc.

DS21101H-page 9

24LC174

FIGURE 8-1:

CURRENT ADDRESS READ

FIGURE 8-2:

RANDOM READ

FIGURE 8-3:

SEQUENTIAL READ

FIGURE 8-4:

SECURITY CONTROL BYTE ALLOCATION

CONTROL

BYTE

DATA n

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

A
C
K

1 A2 A1 A0 B2 B1 B0

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

S
T
O
P

CONTROL

BYTE

C
K

WORD

ADDRESS (n)

CONTROL

BYTE

S
T
A
R
T

DATA (n)

C
K

A
C
K

1 A2 A1A0B2B1B0

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
O
P

CONTROL

BYTE

A
C
K

N
O

DATA n

DATA n + 1

DATA n + 2

DATA n + X

A
C
K

Operation

Control Code

Block

Select

R/W

Read

0110

000

Write

0110

000

START

READ/WRITE

SLAVE ADDRESS

R/W

MSB

LSB

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24LC174

DS21101H-page 10



2004 Microchip Technology Inc.

FIGURE 8-5:

SECURITY PAGE READ

FIGURE 8-6:

SECURITY PAGE WRITE

CONTROL

BYTE

S 0 1 1 0

R/W

WORD

ADDRESS (n)

CONTROL

BYTE

DATA 0

A
R

R/W

A
C
K

BUS MASTER
ACTIVITY

SDA LINE

BUS ACTIVITY

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
O
P

DATA 1

DATA 2

DATA 3

DATA 15

A
C
K

CONTROL

S
T
A

BYTE

S 0 1 1 0

R/W

WORD

ADDRESS (n)

BUS MASTER
ACTIVITY

SDA LINE

BUS ACTIVITY

DATA (n)

DATA n + 1

DATA n + 15

S
T
O
P

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

2004 Microchip Technology Inc.

DS21101H-page 1

FEATURES

• Single supply with operation down to 2.5V
• 16 bytes OTP Secure Memory
• Low power CMOS technology

- 1 mA active current typical
- 10

A standby current typical at 5.5V

- 5

A standby current typical at 3.0V

• Organized as eight blocks of 256 bytes (8 x 256 x 8)
• 2-wire serial interface bus, I



compatible

• Functional address inputs for cascading up to 8

devices

DESCRIPTION

A and 1 mA respectively. The 24LC174 also

has a page-write capability for up to 16 bytes of data.
The 24LC174 is available in the standard 8-pin DIP and
8-lead surface mount SOIC packages.

The three select pins, A0, A1, and A2, function as chip
select inputs and allow up to eight devices to share a
common bus, for up to 128K bits total system
EEPROM.

- Commercial (C):

0°C to +70°C

- Industrial (I):

-40° to

+85°

PACKAGE TYPES

BLOCK DIAGRAM

24
LC
17
4

SCL

SDA

24L

C174

SCL

SDA

PDIP

8-lead
SOIC

HV GENERATOR

EEPROM ARRAY

(8 x 256 x 8)

PAGE LATCHES

YDEC

XDEC

SENSE AMP

R/W CONTROL

MEMORY

CONTROL

LOGIC

I/O

CONTROL

LOGIC

SDA

SCL

24LC174

16K 2.5V Cascadable I

™

Serial EEPROM with OTP Security Page

C is a trademark of Philips Corporation.

Obsolete Device

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24LC174

DS21101H-page 2



2004 Microchip Technology Inc.

1.0

ELECTRICAL CHARACTERISTICS

1.1

Maximum Ratings*

...................................................................................7.0V

All inputs and outputs w.r.t. V

................ -0.3V to Vcc +1.0V

..................................................≥

4 kV

TABLE 1-1:

PIN FUNCTION TABLE

Name

Function

Ground

SDA

Serial Address/Data I/O

SCL

Serial Clock

Write Protect Input

+2.5V to 5.5V Power Supply

A0, A1, A2

Chip Address Inputs

TABLE 1-2:

DC CHARACTERISTICS

FIGURE 1-1:

BUS TIMING START/STOP

Vcc = +2.5V to 5.5V
Commercial

(C):

Tamb = 0°C to +70°C

Industrial

(I):

Tamb = -40°C to +85°C

Parameter

Symbol

Min

Max

Units

Conditions

WP, SCL and SDA pins:

High level input voltage
Low level input voltage
Hysteresis of Schmitt trigger inputs
Low level output voltage

HYS

.7 V

—

.05 V

—

.3 V

—

.40

V
V
V
V

(Note)
I

= 3.0 mA, V

= 2.5V

Input leakage current

-10

= .1V to V

Output leakage current

-10

OUT

= .1V to V

Pin capacitance (all inputs/outputs)

, C

OUT

—

= 5.0V (Note1),

Tamb = 25

C, F

CLK

= 1 MHz

Operating current

Write

Read

—
—

3
1

mA
mA

= 5.5V, SCL = 400 kHz

Standby current

CCS

—
—

100

= 3.0V, SDA = SCL = V

= 5.5V, SDA = SCL = V

WP = V

Note:This parameter is periodically sampled and not 100% tested.

STA

HYS

STO

START

STOP

SCL

SDA

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2004 Microchip Technology Inc.

DS21101H-page 3

24LC174

TABLE 1-3:

AC CHARACTERISTICS

FIGURE 1-2:

BUS TIMING DATA

Parameter

Symbol

Standard Mode

Vcc= 4.5 - 5.5V

Fast Mode

Units

Remarks

Min

Max

Min

Max

Clock frequency

CLK

—

100

—

400

kHz

Clock high time

HIGH

4000

—

600

—

Clock low time

LOW

4700

—

1300

—

SDA and SCL rise time

—

1000

—

300

(Note 1)

SDA and SCL fall time

—

300

—

300

(Note 1)

START condition hold time

STA

4000

—

600

—

After this period the first clock
pulse is generated

START condition setup
time

STA

4700

—

600

—

Only relevant for repeated
START condition

Data input hold time

DAT

—

Data input setup time

DAT

250

—

100

—

STOP condition setup time

STO

4000

—

600

—

Output valid from clock

—

3500

—

900

(Note 2)

Bus free time

BUF

4700

—

1300

—

Time the bus must be free
before a new transmission can
start

Output fall time from V

min to V

max

—

250

20 +0.1

250

(Note 1), C

≤

100 pF

Input filter spike suppres-
sion (SDA and SCL pins)

—

(Note 3)

Write cycle time

—

Byte or Page mode

Endurance

—

cycles

25°C, Vcc = 5.0V, Block Mode
(Note 4)

Note 1: Not 100% tested. C

= total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3: The combined T

and V

HYS

specifications are due to new Schmitt trigger inputs which provide improved

noise and spike suppression. This eliminates the need for a T

specification for standard operation.

4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-

cation, please consult the Total Endurance Model which can be obtained on our website.

SCL

SDA
IN

SDA
OUT

STA

LOW

HIGH

STA

DAT

STO

BUF

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24LC174

DS21101H-page 4



2004 Microchip Technology Inc.

2.0

FUNCTIONAL DESCRIPTION

3.0

BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been
defined (Figure 3-1).

3.1

Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2

Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.

3.3

Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.

3.4

Data Valid (D)

The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.

3.5

Acknowledge

Note:

The 24LC174 does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.

FIGURE 3-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

SCL

SDA

(A)

(B)

(D)

(A)

(C)

START

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

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

2004 Microchip Technology Inc.

DS21101H-page 5

24LC174

3.6

Device Addressing and Operation

FIGURE 3-2:

CONTROL BYTE
ALLOCATION

Operation

Control Code

Block Select

R/W

Read

A2 A1 A0 Block Address

Write

A2 A1 A0 Block Address

SLAVE ADDRESS

R/W A

START

READ/WRITE

MSB

LSB

4.0

WRITE OPERATION

4.1

Byte Write

4.2

Page Write

Note:

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24LC174

DS21101H-page 6



2004 Microchip Technology Inc.

FIGURE 4-1:

BYTE WRITE

FIGURE 4-2:

PAGE WRITE

S
T
O
P

SDA LINE

DATA

S
T
A
R
T

CONTROL

BYTE

WORD

ADDRESS

BUS ACTIVITY:
MASTER

BUS ACTIVITY:

A
C
K

1 A2

A1 A0 B2 B1

S
T
O
P

SDA LINE

DATA n

S
T
A
R
T

CONTROL

BYTE

WORD

ADDRESS (n)

BUS ACTIVITY:
MASTER

BUS ACTIVITY:

A
C
K

DATA n + 1

A
C
K

DATA n + 15

A
C
K

A1 A0 B2 B1

5.0

ACKNOWLEDGE POLLING

FIGURE 5-1:

ACKNOWLEDGE POLLING
FLOW

6.0

WRITE PROTECTION

The 24LC174 can be used as a serial ROM when the
WP pin is connected to Vcc. Programming will be inhib-
ited and the entire memory will be write-protected.

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

Operation

YES

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

2004 Microchip Technology Inc.

DS21101H-page 7

24LC174

7.0

READ OPERATION

7.1

Current Address Read

7.2

Random Read

7.3

Sequential Read

7.4

Noise Protection

The 24LC174 employs a Vcc threshold detector circuit
which disables the internal erase/write logic if the V

is below 1.5 volts at nominal conditions.

The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.

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24LC174

DS21101H-page 8



2004 Microchip Technology Inc.

8.0

PIN DESCRIPTIONS

8.1

SDA Serial Address/Data Input/Output

This is a Bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pullup
resistor to V

(typical 10K

Ω

for 100 kHz, 2 K

Ω

for

400 kHz).

For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi-
tions.

8.2

SCL Serial Clock

This input is used to synchronize the data transfer from
and to the device.

8.3

This pin must be connected to either V

or V

If tied to V

, normal memory operation is enabled

(read/write the entire memory 000-7FF).

If tied to V

, WRITE operations are inhibited. The

entire memory will be write-protected. Read operations
are not affected.

This feature allows the user to use the 24LC174 as a
serial ROM when WP is enabled (tied to Vcc).

8.4

A0, A1, A2

Up to eight 24LC174s may be connected to the same
bus. These pins must be connected to either V

Note:

The level on A1 is compared to the inverse
of the slave address.

8.5

Security Access Control

The security row is enabled by sending the control
sequence with the I

C slave address of 0110. Bit 0 of

8.6

Security Access Write

8.7

Security Access Read

The security access read is accomplished by executing
the normal read sequences, following the security
access control sequence with bit 0 set to a one. The
security page read starts at data byte 0.

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

2004 Microchip Technology Inc.

DS21101H-page 9

24LC174

FIGURE 8-1:

CURRENT ADDRESS READ

FIGURE 8-2:

RANDOM READ

FIGURE 8-3:

SEQUENTIAL READ

FIGURE 8-4:

SECURITY CONTROL BYTE ALLOCATION

CONTROL

BYTE

DATA n

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

A
C
K

1 A2 A1 A0 B2 B1 B0

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

S
T
O
P

CONTROL

BYTE

C
K

WORD

ADDRESS (n)

CONTROL

BYTE

S
T
A
R
T

DATA (n)

C
K

A
C
K

1 A2 A1A0B2B1B0

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
O
P

CONTROL

BYTE

A
C
K

N
O

DATA n

DATA n + 1

DATA n + 2

DATA n + X

A
C
K

Operation

Control Code

Block

Select

R/W

Read

0110

000

Write

0110

000

START

READ/WRITE

SLAVE ADDRESS

R/W

MSB

LSB

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24LC174

DS21101H-page 10



2004 Microchip Technology Inc.

FIGURE 8-5:

SECURITY PAGE READ

FIGURE 8-6:

SECURITY PAGE WRITE

CONTROL

BYTE

S 0 1 1 0

R/W

WORD

ADDRESS (n)

CONTROL

BYTE

DATA 0

A
R

R/W

A
C
K

BUS MASTER
ACTIVITY

SDA LINE

BUS ACTIVITY

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
O
P

DATA 1

DATA 2

DATA 3

DATA 15

A
C
K

CONTROL

S
T
A

BYTE

S 0 1 1 0

R/W

WORD

ADDRESS (n)

BUS MASTER
ACTIVITY

SDA LINE

BUS ACTIVITY

DATA (n)

DATA n + 1

DATA n + 15

S
T
O
P

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

2004 Microchip Technology Inc.

DS21101H-page 1

FEATURES

• Single supply with operation down to 2.5V
• 16 bytes OTP Secure Memory
• Low power CMOS technology

- 1 mA active current typical
- 10

A standby current typical at 5.5V

- 5

A standby current typical at 3.0V

• Organized as eight blocks of 256 bytes (8 x 256 x 8)
• 2-wire serial interface bus, I



compatible

• Functional address inputs for cascading up to 8

devices

DESCRIPTION

A and 1 mA respectively. The 24LC174 also

has a page-write capability for up to 16 bytes of data.
The 24LC174 is available in the standard 8-pin DIP and
8-lead surface mount SOIC packages.

The three select pins, A0, A1, and A2, function as chip
select inputs and allow up to eight devices to share a
common bus, for up to 128K bits total system
EEPROM.

- Commercial (C):

0°C to +70°C

- Industrial (I):

-40° to

+85°

PACKAGE TYPES

BLOCK DIAGRAM

24
LC
17
4

SCL

SDA

24L

C174

SCL

SDA

PDIP

8-lead
SOIC

HV GENERATOR

EEPROM ARRAY

(8 x 256 x 8)

PAGE LATCHES

YDEC

XDEC

SENSE AMP

R/W CONTROL

MEMORY

CONTROL

LOGIC

I/O

CONTROL

LOGIC

SDA

SCL

24LC174

16K 2.5V Cascadable I

™

Serial EEPROM with OTP Security Page

C is a trademark of Philips Corporation.

Obsolete Device

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24LC174

DS21101H-page 2

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2004 Microchip Technology Inc.

1.0

ELECTRICAL CHARACTERISTICS

1.1

Maximum Ratings*

...................................................................................7.0V

All inputs and outputs w.r.t. V

................ -0.3V to Vcc +1.0V

..................................................≥

4 kV

TABLE 1-1:

PIN FUNCTION TABLE

Name

Function

Ground

SDA

Serial Address/Data I/O

SCL

Serial Clock

Write Protect Input

+2.5V to 5.5V Power Supply

A0, A1, A2

Chip Address Inputs

TABLE 1-2:

DC CHARACTERISTICS

FIGURE 1-1:

BUS TIMING START/STOP

Vcc = +2.5V to 5.5V
Commercial

(C):

Tamb = 0°C to +70°C

Industrial

(I):

Tamb = -40°C to +85°C

Parameter

Symbol

Min

Max

Units

Conditions

WP, SCL and SDA pins:

High level input voltage
Low level input voltage
Hysteresis of Schmitt trigger inputs
Low level output voltage

HYS

.7 V

—

.05 V

—

.3 V

—

.40

V
V
V
V

(Note)
I

= 3.0 mA, V

= 2.5V

Input leakage current

-10

= .1V to V

Output leakage current

-10

OUT

= .1V to V

Pin capacitance (all inputs/outputs)

, C

OUT

—

= 5.0V (Note1),

Tamb = 25

C, F

CLK

= 1 MHz

Operating current

Write

Read

—
—

3
1

mA
mA

= 5.5V, SCL = 400 kHz

Standby current

CCS

—
—

100

= 3.0V, SDA = SCL = V

= 5.5V, SDA = SCL = V

WP = V

Note:This parameter is periodically sampled and not 100% tested.

STA

HYS

STO

START

STOP

SCL

SDA

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2004 Microchip Technology Inc.

DS21101H-page 3

24LC174

TABLE 1-3:

AC CHARACTERISTICS

FIGURE 1-2:

BUS TIMING DATA

Parameter

Symbol

Standard Mode

Vcc= 4.5 - 5.5V

Fast Mode

Units

Remarks

Min

Max

Min

Max

Clock frequency

CLK

—

100

—

400

kHz

Clock high time

HIGH

4000

—

600

—

Clock low time

LOW

4700

—

1300

—

SDA and SCL rise time

—

1000

—

300

(Note 1)

SDA and SCL fall time

—

300

—

300

(Note 1)

START condition hold time

STA

4000

—

600

—

After this period the first clock
pulse is generated

START condition setup
time

STA

4700

—

600

—

Only relevant for repeated
START condition

Data input hold time

DAT

—

Data input setup time

DAT

250

—

100

—

STOP condition setup time

STO

4000

—

600

—

Output valid from clock

—

3500

—

900

(Note 2)

Bus free time

BUF

4700

—

1300

—

Time the bus must be free
before a new transmission can
start

Output fall time from V

min to V

max

—

250

20 +0.1

250

(Note 1), C

≤

100 pF

Input filter spike suppres-
sion (SDA and SCL pins)

—

(Note 3)

Write cycle time

—

Byte or Page mode

Endurance

—

cycles

25°C, Vcc = 5.0V, Block Mode
(Note 4)

Note 1: Not 100% tested. C

= total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3: The combined T

and V

HYS

specifications are due to new Schmitt trigger inputs which provide improved

noise and spike suppression. This eliminates the need for a T

specification for standard operation.

4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-

cation, please consult the Total Endurance Model which can be obtained on our website.

SCL

SDA
IN

SDA
OUT

STA

LOW

HIGH

STA

DAT

STO

BUF

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24LC174

DS21101H-page 4

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2004 Microchip Technology Inc.

2.0

FUNCTIONAL DESCRIPTION

3.0

BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been
defined (Figure 3-1).

3.1

Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2

Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.

3.3

Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.

3.4

Data Valid (D)

The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.

3.5

Acknowledge

Note:

The 24LC174 does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.

FIGURE 3-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

SCL

SDA

(A)

(B)

(D)

(A)

(C)

START

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

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2004 Microchip Technology Inc.

DS21101H-page 5

24LC174

3.6

Device Addressing and Operation

FIGURE 3-2:

CONTROL BYTE
ALLOCATION

Operation

Control Code

Block Select

R/W

Read

A2 A1 A0 Block Address

Write

A2 A1 A0 Block Address

SLAVE ADDRESS

R/W A

START

READ/WRITE

MSB

LSB

4.0

WRITE OPERATION

4.1

Byte Write

4.2

Page Write

Note:

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24LC174

DS21101H-page 6



2004 Microchip Technology Inc.

FIGURE 4-1:

BYTE WRITE

FIGURE 4-2:

PAGE WRITE

S
T
O
P

SDA LINE

DATA

S
T
A
R
T

CONTROL

BYTE

WORD

ADDRESS

BUS ACTIVITY:
MASTER

BUS ACTIVITY:

A
C
K

1 A2

A1 A0 B2 B1

S
T
O
P

SDA LINE

DATA n

S
T
A
R
T

CONTROL

BYTE

WORD

ADDRESS (n)

BUS ACTIVITY:
MASTER

BUS ACTIVITY:

A
C
K

DATA n + 1

A
C
K

DATA n + 15

A
C
K

A1 A0 B2 B1

5.0

ACKNOWLEDGE POLLING

FIGURE 5-1:

ACKNOWLEDGE POLLING
FLOW

6.0

WRITE PROTECTION

The 24LC174 can be used as a serial ROM when the
WP pin is connected to Vcc. Programming will be inhib-
ited and the entire memory will be write-protected.

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

Operation

YES

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2004 Microchip Technology Inc.

DS21101H-page 7

24LC174

7.0

READ OPERATION

7.1

Current Address Read

7.2

Random Read

7.3

Sequential Read

7.4

Noise Protection

The 24LC174 employs a Vcc threshold detector circuit
which disables the internal erase/write logic if the V

is below 1.5 volts at nominal conditions.

The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.

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24LC174

DS21101H-page 8



2004 Microchip Technology Inc.

8.0

PIN DESCRIPTIONS

8.1

SDA Serial Address/Data Input/Output

This is a Bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pullup
resistor to V

(typical 10K

Ω

for 100 kHz, 2 K

Ω

for

400 kHz).

For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi-
tions.

8.2

SCL Serial Clock

This input is used to synchronize the data transfer from
and to the device.

8.3

This pin must be connected to either V

or V

If tied to V

, normal memory operation is enabled

(read/write the entire memory 000-7FF).

If tied to V

, WRITE operations are inhibited. The

entire memory will be write-protected. Read operations
are not affected.

This feature allows the user to use the 24LC174 as a
serial ROM when WP is enabled (tied to Vcc).

8.4

A0, A1, A2

Up to eight 24LC174s may be connected to the same
bus. These pins must be connected to either V

Note:

The level on A1 is compared to the inverse
of the slave address.

8.5

Security Access Control

The security row is enabled by sending the control
sequence with the I

C slave address of 0110. Bit 0 of

8.6

Security Access Write

8.7

Security Access Read

The security access read is accomplished by executing
the normal read sequences, following the security
access control sequence with bit 0 set to a one. The
security page read starts at data byte 0.

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2004 Microchip Technology Inc.

DS21101H-page 9

24LC174

FIGURE 8-1:

CURRENT ADDRESS READ

FIGURE 8-2:

RANDOM READ

FIGURE 8-3:

SEQUENTIAL READ

FIGURE 8-4:

SECURITY CONTROL BYTE ALLOCATION

CONTROL

BYTE

DATA n

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

A
C
K

1 A2 A1 A0 B2 B1 B0

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

S
T
O
P

CONTROL

BYTE

C
K

WORD

ADDRESS (n)

CONTROL

BYTE

S
T
A
R
T

DATA (n)

C
K

A
C
K

1 A2 A1A0B2B1B0

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
O
P

CONTROL

BYTE

A
C
K

N
O

DATA n

DATA n + 1

DATA n + 2

DATA n + X

A
C
K

Operation

Control Code

Block

Select

R/W

Read

0110

000

Write

0110

000

START

READ/WRITE

SLAVE ADDRESS

R/W

MSB

LSB

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24LC174

DS21101H-page 10

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2004 Microchip Technology Inc.

FIGURE 8-5:

SECURITY PAGE READ

FIGURE 8-6:

SECURITY PAGE WRITE

CONTROL

BYTE

S 0 1 1 0

R/W

WORD

ADDRESS (n)

CONTROL

BYTE

DATA 0

A
R

R/W

A
C
K

BUS MASTER
ACTIVITY

SDA LINE

BUS ACTIVITY

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
O
P

DATA 1

DATA 2

DATA 3

DATA 15

A
C
K

CONTROL

S
T
A

BYTE

S 0 1 1 0

R/W

WORD

ADDRESS (n)

BUS MASTER
ACTIVITY

SDA LINE

BUS ACTIVITY

DATA (n)

DATA n + 1

DATA n + 15

S
T
O
P

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2004 Microchip Technology Inc.

DS21101H-page 1

FEATURES

• Single supply with operation down to 2.5V
• 16 bytes OTP Secure Memory
• Low power CMOS technology

- 1 mA active current typical
- 10

A standby current typical at 5.5V

- 5

A standby current typical at 3.0V

• Organized as eight blocks of 256 bytes (8 x 256 x 8)
• 2-wire serial interface bus, I



compatible

• Functional address inputs for cascading up to 8

devices

DESCRIPTION

A and 1 mA respectively. The 24LC174 also

has a page-write capability for up to 16 bytes of data.
The 24LC174 is available in the standard 8-pin DIP and
8-lead surface mount SOIC packages.

The three select pins, A0, A1, and A2, function as chip
select inputs and allow up to eight devices to share a
common bus, for up to 128K bits total system
EEPROM.

- Commercial (C):

0°C to +70°C

- Industrial (I):

-40° to

+85°

PACKAGE TYPES

BLOCK DIAGRAM

24
LC
17
4

SCL

SDA

24L

C174

SCL

SDA

PDIP

8-lead
SOIC

HV GENERATOR

EEPROM ARRAY

(8 x 256 x 8)

PAGE LATCHES

YDEC

XDEC

SENSE AMP

R/W CONTROL

MEMORY

CONTROL

LOGIC

I/O

CONTROL

LOGIC

SDA

SCL

24LC174

16K 2.5V Cascadable I

™

Serial EEPROM with OTP Security Page

C is a trademark of Philips Corporation.

Obsolete Device

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24LC174

DS21101H-page 2



2004 Microchip Technology Inc.

1.0

ELECTRICAL CHARACTERISTICS

1.1

Maximum Ratings*

...................................................................................7.0V

All inputs and outputs w.r.t. V

................ -0.3V to Vcc +1.0V

..................................................≥

4 kV

TABLE 1-1:

PIN FUNCTION TABLE

Name

Function

Ground

SDA

Serial Address/Data I/O

SCL

Serial Clock

Write Protect Input

+2.5V to 5.5V Power Supply

A0, A1, A2

Chip Address Inputs

TABLE 1-2:

DC CHARACTERISTICS

FIGURE 1-1:

BUS TIMING START/STOP

Vcc = +2.5V to 5.5V
Commercial

(C):

Tamb = 0°C to +70°C

Industrial

(I):

Tamb = -40°C to +85°C

Parameter

Symbol

Min

Max

Units

Conditions

WP, SCL and SDA pins:

High level input voltage
Low level input voltage
Hysteresis of Schmitt trigger inputs
Low level output voltage

HYS

.7 V

—

.05 V

—

.3 V

—

.40

V
V
V
V

(Note)
I

= 3.0 mA, V

= 2.5V

Input leakage current

-10

= .1V to V

Output leakage current

-10

OUT

= .1V to V

Pin capacitance (all inputs/outputs)

, C

OUT

—

= 5.0V (Note1),

Tamb = 25

C, F

CLK

= 1 MHz

Operating current

Write

Read

—
—

3
1

mA
mA

= 5.5V, SCL = 400 kHz

Standby current

CCS

—
—

100

= 3.0V, SDA = SCL = V

= 5.5V, SDA = SCL = V

WP = V

Note:This parameter is periodically sampled and not 100% tested.

STA

HYS

STO

START

STOP

SCL

SDA

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2004 Microchip Technology Inc.

DS21101H-page 3

24LC174

TABLE 1-3:

AC CHARACTERISTICS

FIGURE 1-2:

BUS TIMING DATA

Parameter

Symbol

Standard Mode

Vcc= 4.5 - 5.5V

Fast Mode

Units

Remarks

Min

Max

Min

Max

Clock frequency

CLK

—

100

—

400

kHz

Clock high time

HIGH

4000

—

600

—

Clock low time

LOW

4700

—

1300

—

SDA and SCL rise time

—

1000

—

300

(Note 1)

SDA and SCL fall time

—

300

—

300

(Note 1)

START condition hold time

STA

4000

—

600

—

After this period the first clock
pulse is generated

START condition setup
time

STA

4700

—

600

—

Only relevant for repeated
START condition

Data input hold time

DAT

—

Data input setup time

DAT

250

—

100

—

STOP condition setup time

STO

4000

—

600

—

Output valid from clock

—

3500

—

900

(Note 2)

Bus free time

BUF

4700

—

1300

—

Time the bus must be free
before a new transmission can
start

Output fall time from V

min to V

max

—

250

20 +0.1

250

(Note 1), C

≤

100 pF

Input filter spike suppres-
sion (SDA and SCL pins)

—

(Note 3)

Write cycle time

—

Byte or Page mode

Endurance

—

cycles

25°C, Vcc = 5.0V, Block Mode
(Note 4)

Note 1: Not 100% tested. C

= total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3: The combined T

and V

HYS

specifications are due to new Schmitt trigger inputs which provide improved

noise and spike suppression. This eliminates the need for a T

specification for standard operation.

4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-

cation, please consult the Total Endurance Model which can be obtained on our website.

SCL

SDA
IN

SDA
OUT

STA

LOW

HIGH

STA

DAT

STO

BUF

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24LC174

DS21101H-page 4



2004 Microchip Technology Inc.

2.0

FUNCTIONAL DESCRIPTION

3.0

BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been
defined (Figure 3-1).

3.1

Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2

Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.

3.3

Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.

3.4

Data Valid (D)

The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.

3.5

Acknowledge

Note:

The 24LC174 does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.

FIGURE 3-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

SCL

SDA

(A)

(B)

(D)

(A)

(C)

START

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

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2004 Microchip Technology Inc.

DS21101H-page 5

24LC174

3.6

Device Addressing and Operation

FIGURE 3-2:

CONTROL BYTE
ALLOCATION

Operation

Control Code

Block Select

R/W

Read

A2 A1 A0 Block Address

Write

A2 A1 A0 Block Address

SLAVE ADDRESS

R/W A

START

READ/WRITE

MSB

LSB

4.0

WRITE OPERATION

4.1

Byte Write

4.2

Page Write

Note:

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24LC174

DS21101H-page 6



2004 Microchip Technology Inc.

FIGURE 4-1:

BYTE WRITE

FIGURE 4-2:

PAGE WRITE

S
T
O
P

SDA LINE

DATA

S
T
A
R
T

CONTROL

BYTE

WORD

ADDRESS

BUS ACTIVITY:
MASTER

BUS ACTIVITY:

A
C
K

1 A2

A1 A0 B2 B1

S
T
O
P

SDA LINE

DATA n

S
T
A
R
T

CONTROL

BYTE

WORD

ADDRESS (n)

BUS ACTIVITY:
MASTER

BUS ACTIVITY:

A
C
K

DATA n + 1

A
C
K

DATA n + 15

A
C
K

A1 A0 B2 B1

5.0

ACKNOWLEDGE POLLING

FIGURE 5-1:

ACKNOWLEDGE POLLING
FLOW

6.0

WRITE PROTECTION

The 24LC174 can be used as a serial ROM when the
WP pin is connected to Vcc. Programming will be inhib-
ited and the entire memory will be write-protected.

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

Operation

YES

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

2004 Microchip Technology Inc.

DS21101H-page 7

24LC174

7.0

READ OPERATION

7.1

Current Address Read

7.2

Random Read

7.3

Sequential Read

7.4

Noise Protection

The 24LC174 employs a Vcc threshold detector circuit
which disables the internal erase/write logic if the V

is below 1.5 volts at nominal conditions.

The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.

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24LC174

DS21101H-page 8



2004 Microchip Technology Inc.

8.0

PIN DESCRIPTIONS

8.1

SDA Serial Address/Data Input/Output

This is a Bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pullup
resistor to V

(typical 10K

Ω

for 100 kHz, 2 K

Ω

for

400 kHz).

For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi-
tions.

8.2

SCL Serial Clock

This input is used to synchronize the data transfer from
and to the device.

8.3

This pin must be connected to either V

or V

If tied to V

, normal memory operation is enabled

(read/write the entire memory 000-7FF).

If tied to V

, WRITE operations are inhibited. The

entire memory will be write-protected. Read operations
are not affected.

This feature allows the user to use the 24LC174 as a
serial ROM when WP is enabled (tied to Vcc).

8.4

A0, A1, A2

Up to eight 24LC174s may be connected to the same
bus. These pins must be connected to either V

Note:

The level on A1 is compared to the inverse
of the slave address.

8.5

Security Access Control

The security row is enabled by sending the control
sequence with the I

C slave address of 0110. Bit 0 of

8.6

Security Access Write

8.7

Security Access Read

The security access read is accomplished by executing
the normal read sequences, following the security
access control sequence with bit 0 set to a one. The
security page read starts at data byte 0.

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2004 Microchip Technology Inc.

DS21101H-page 9

24LC174

FIGURE 8-1:

CURRENT ADDRESS READ

FIGURE 8-2:

RANDOM READ

FIGURE 8-3:

SEQUENTIAL READ

FIGURE 8-4:

SECURITY CONTROL BYTE ALLOCATION

CONTROL

BYTE

DATA n

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

A
C
K

1 A2 A1 A0 B2 B1 B0

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

S
T
O
P

CONTROL

BYTE

C
K

WORD

ADDRESS (n)

CONTROL

BYTE

S
T
A
R
T

DATA (n)

C
K

A
C
K

1 A2 A1A0B2B1B0

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
O
P

CONTROL

BYTE

A
C
K

N
O

DATA n

DATA n + 1

DATA n + 2

DATA n + X

A
C
K

Operation

Control Code

Block

Select

R/W

Read

0110

000

Write

0110

000

START

READ/WRITE

SLAVE ADDRESS

R/W

MSB

LSB

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24LC174

DS21101H-page 10



2004 Microchip Technology Inc.

FIGURE 8-5:

SECURITY PAGE READ

FIGURE 8-6:

SECURITY PAGE WRITE

CONTROL

BYTE

S 0 1 1 0

R/W

WORD

ADDRESS (n)

CONTROL

BYTE

DATA 0

A
R

R/W

A
C
K

BUS MASTER
ACTIVITY

SDA LINE

BUS ACTIVITY

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
O
P

DATA 1

DATA 2

DATA 3

DATA 15

A
C
K

CONTROL

S
T
A

BYTE

S 0 1 1 0

R/W

WORD

ADDRESS (n)

BUS MASTER
ACTIVITY

SDA LINE

BUS ACTIVITY

DATA (n)

DATA n + 1

DATA n + 15

S
T
O
P

Maker

Microchip Technology Inc.

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