21081G.book | Datasheet Lookup

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

2004 Microchip Technology Inc.

DS21081G-page 1

FEATURES

• Single supply with operation from 4.5-5.5V
• Low power CMOS technology

- 1 mA active current typical
- 10

A standby current typical at 5.5V

• Organized as 4 or 8 blocks of 256 bytes

(4 x 256 x 8) or (8 x 256 x 8)

• 2-wire serial interface bus, I



compatible

• Schmitt trigger, filtered inputs for noise suppres-

sion

• Output slope control to eliminate ground bounce
• 100 kHz compatibility
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 16 bytes
• 2 ms typical write cycle time for page-write
• Hardware write protect for entire memory
• Can be operated as a serial ROM
• ESD protection > 4,000V
• 1,000,000 ERASE/WRITE cycles guaranteed
• Data retention > 200 years
• 8-pin DIP, 8-lead or 14-lead SOIC packages
• Available for extended temperature range

DESCRIPTION

The Microchip Technology Inc. 24C08B/16B is an 8K or
16K bit Electrically Erasable PROM intended for use in
extended/automotive temperature ranges. The device
is organized as four or eight blocks of 256 x 8-bit mem-
ory with a 2-wire serial interface. The 24C08B/16B also
has a page-write capability for up to 16 bytes of data.
The 24C08B/16B is available in the standard 8-pin DIP
and both 8-lead and 14-lead surface mount SOIC pack-
ages.

- Commercial (C):

0°C to

+70°C

- Industrial (I):

-40°C to

+85°C

- Automotive (E):

-40°C to +125°C

PACKAGE TYPES

BLOCK DIAGRAM

SCL

SDA

14-lead
SOIC

24
C

08B

24
C

8B
/1

SCL

SDA

24C08B

/16B

SCL

SDA

PDIP

8-lead
SOIC

HV GENERATOR

EEPROM

ARRAY

PAGE LATCHES

YDEC

XDEC

SENSE AMP

R/W CONTROL

MEMORY

CONTROL

LOGIC

I/O

CONTROL

LOGIC

SDA

SCL

24C08B/16B

8K/16K 5.0V I

™

Serial EEPROMs

C is a trademark of Philips Corporation.

Obsolete Device

Please use 24LC08B or 24LC16B.

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24C08B/16B

DS21081G-page 2



2004 Microchip Technology Inc.

1.0

ELECTRICAL CHARACTERISTICS

1.1

Maximum Ratings*

...................................................................................7.0V

All inputs and outputs w.r.t. V

............... -0.6V to V

+1.0V

Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-65°C to +125°C
Soldering temperature of leads (10 seconds) ............. +300°C
ESD protection on all pins

..................................................≥

4 kV

*Notice: Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

TABLE 1-1:

PIN FUNCTION TABLE

Name

Function

Ground

SDA

Serial Address/Data I/O

SCL Serial

Clock

Write Protect Input

+4.5V to 5.5V Power Supply

A0, A1, A2

No Internal Connection

TABLE 1-2:

DC CHARACTERISTICS

FIGURE 1-1:

BUS TIMING START/STOP

= +4.5V to +5.5V

Commercial (C): Tamb = 0°C to +70°C
Industrial (I):

Tamb = -40°C to +85°C

Automotive (E):

Tamb = -40°C to +125°C

Parameter

Symbol

Min

Max

Units

Conditions

WP, SCL and SDA pins:

High level input voltage

.7 Vcc

—

Low Level input voltage

—

.3 V

Hysteresis of Schmitt trigger
inputs

HYS

.05 Vcc

—

(Note)

Low level output voltage

—

.40

= 3.0 mA, V

=4.5V

Input leakage current

-10

=.1V to V

Output leakage current

-10

OUT

= .1V to V

Pin capacitance
(all inputs/outputs)

, C

OUT

—

= 5.0V (Note 1)

Tamb = 25°C, F

CLK

=1 MHz

Operating current

write

read

—
—

3
1

mA
mA

= 5.5V, SCL = 400 kHz

Standby current

CCS

—

100

= 5.5V, SDA = SCL = V

WP = V

Note:

This parameter is periodically sampled and not 100% tested.

STA

HYS

STO

START

STOP

SCL

SDA

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2004 Microchip Technology Inc.

DS21081G-page 3

24C08B/16B

TABLE 1-3:

AC CHARACTERISTICS

FIGURE 1-2:

BUS TIMING DATA

Parameter

Symbol

Min

Max

Units

Remarks

Clock frequency

CLK

—

100

kHz

Clock high time

HIGH

4000

—

Clock low time

LOW

4700

—

SDA and SCL rise time

—

1000

(Note1)

SDA and SCL fall time

—

300

(Note 1)

START condition hold time

STA

4000

—

After this period the first clock
pulse is generated

START condition setup
time

STA

4700

—

Only relevant for repeated
START condition

Data input hold time

DAT

—

Data input setup time

DAT

250

—

STOP condition setup time

STO

4000

—

Output valid from clock

—

3500

(Note 2)

Bus free time

BUF

4700

—

Time the bus must be free before
a new transmission can start

Output fall time from V

min to V

max

—

250

(Note 1), C

≤

100 pF

Input filter spike suppres-
sion (SDA and SCL pins)

—

(Note 3)

Write cycle time

—

Byte or Page mode

Endurance

—

cycles

25°C, V

= 5.0V, Block Mode

(Note 4)

Note 1: Not 100% tested. C

= total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3: The combined T

and V

HYS

specifications are due to new Schmitt trigger inputs which provide improved

noise and spike suppression. This eliminates the need for a T

specification.

4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific

application, please consult the Total Endurance Model which can be obtained on our website.

STA

LOW

HIGH

DAT

STO

STA

BUF

STA

SCL

SDA

OUT

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24C08B/16B

DS21081G-page 4

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2004 Microchip Technology Inc.

2.0

FUNCTIONAL DESCRIPTION

The 24C08B/16B supports a Bi-directional 2-wire bus
and data transmission protocol. A device that sends
data onto the bus is defined as transmitter, and a
device receiving data as receiver. The bus has to be
controlled by a master device which generates the
serial clock (SCL), controls the bus access, and gener-
ates the START and STOP conditions, while the
24C08B/16B works as slave. Both, master and slave
can operate as transmitter or receiver but the master
device determines which mode is activated.

3.0

BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been
defined (Figure 3-1).

3.1

Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2

Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START condi-
tion.

3.3

Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.

3.4

Data Valid (D)

The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.

Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last 16
will be stored when doing a write operation. When an
overwrite does occur it will replace data in a first in first
out fashion.

3.5

Acknowledge

Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.

The device that acknowledges, has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the slave by NOT generating an acknowledge
bit on the last byte that has been clocked out of the
slave. In this case, the slave (24C08B/16B) will leave
the data line HIGH to enable the master to generate the
STOP condition.

Note:

The 24C08B/16B does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.

FIGURE 3-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

SCL

SDA

(A)

(B)

(D)

(A)

(C)

START

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

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2004 Microchip Technology Inc.

DS21081G-page 5

24C08B/16B

3.6

Device Addressing

A control byte is the first byte received following the
start condition from the master device. The control byte
consists of a 4-bit control code, for the 24C08B/16B
this is set as 1010 binary for read and write operations.
The next three bits of the control byte are the block
select bits (B2, B1, B0). They are used by the master
device to select which of the eight 256 word blocks of
memory are to be accessed. These bits are in effect the
three most significant bits of the word address.

The last bit of the control byte defines the operation to
be performed. When set to one a read operation is
selected, when set to zero a write operation is selected.
Following the start condition, the 24C08B/16B monitors
the SDA bus checking the device type identifier being
transmitted, upon a 1010 code the slave device outputs
an acknowledge signal on the SDA line. Depending on
the state of the R/W bit, the 24C08B/16B will select a
read or write operation.

FIGURE 3-2:

CONTROL BYTE
ALLOCATION

Operation

Control

Code

Block Select

R/W

Read

1010

Block Address

Write

1010

Block Address

SLAVE ADDRESS

R/W

START

READ/WRITE

4.0

WRITE OPERATION

4.1

Byte Write

Following the start condition from the master, the
device code (4 bits), the block address (3 bits), and the
R/W bit which is a logic low is placed onto the bus by
the master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will fol-
low after it has generated an acknowledge bit during
the ninth clock cycle. Therefore the next byte transmit-
ted by the master is the word address and will be writ-
ten into the address pointer of the 24C08B/16B. After
receiving another acknowledge signal from the
24C08B/16B the master device will transmit the data
word to be written into the addressed memory location.
The 24C08B/16B acknowledges again and the master
generates a stop condition. This initiates the internal
write cycle, and during this time the 24C08B/16B will
not generate acknowledge signals (Figure 4-1).

4.2

Page Write

The write control byte, word address and the first data
byte are transmitted to the 24C08B/16B in the same
way as in a byte write. But instead of generating a stop
condition the master transmits up to 16 data bytes to
the 24C08B/16B which are temporarily stored in the
on-chip page buffer and will be written into the memory
after the master has transmitted a stop condition. After
the receipt of each word, the four lower order address
pointer bits are internally incremented by one. The
higher order seven bits of the word address remains
constant. If the master should transmit more than 16
words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (Figure 4-2).

Note:

Page write operations are limited to writing
bytes within a single physical page, regardless
of the number of bytes actually being written.
Physical page boundaries start at addresses that
are integer multiples of the page buffer size (or
‘page size’) and end at addresses that are integer
multiples of [page size - 1]. If a page write com-
mand attempts to write across a physical page
boundary, the result is that the data wraps
around to the beginning of the current page
(overwriting data previously stored there),
instead of being written to the next page as
might be expected. It is therefore necessary for
the application software to prevent page write
operations that would attempt to cross a page
boundary.

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24C08B/16B

DS21081G-page 6



2004 Microchip Technology Inc.

FIGURE 4-1:

BYTE WRITE

FIGURE 4-2:

PAGE WRITE

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

S
T
O
P

CONTROL

BYTE

WORD

ADDRESS

DATA

A
C
K

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

CONTROL

BYTE

WORD

ADDRESS (n)

DATA n

DATA n + 15

S
T
O
P

A
C
K

DATA n + 1

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2004 Microchip Technology Inc.

DS21081G-page 7

24C08B/16B

5.0

ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send-
ing a start condition followed by the control byte for a
write command (R/W = 0). If the device is still busy with
the write cycle, then no ACK will be returned. If the
cycle is complete, then the device will return the ACK
and the master can then proceed with the next read or
write command. See Figure 5-1 for flow diagram.

FIGURE 5-1:

ACKNOWLEDGE POLLING
FLOW

6.0

WRITE PROTECTION

The 24C08B/16B can be used as a serial ROM when
the WP pin is connected to V

. Programming will be

inhibited and the entire memory will be write-protected.

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

Operation

YES

7.0

READ OPERATION

Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic
types of read operations: current address read, ran-
dom read, and sequential read.

7.1

Current Address Read

The 24C08B/16B contains an address counter that
maintains the address of the last word accessed, inter-
nally incremented by one. Therefore, if the previous
access (either a read or write operation) was to
address n, the next current address read operation
would access data from address n + 1. Upon receipt of
the slave address with R/W bit set to one,

the

24C08B/16B issues an acknowledge and transmits the
8-bit data word. The master will not acknowledge the
transfer but does generate a stop condition and the
24C08B/16B discontinues transmission (Figure 7-1).

7.2

Random Read

Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24C08B/16B as part of a write operation. After the word
address is sent, the master generates a start condition
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is
set. Then the master issues the control byte again but
with the R/W bit set to a one. The 24C08B/16B will then
issue an acknowledge and transmits the 8-bit data
word. The master will not acknowledge the transfer but
does generate a stop condition and the 24C08B/16B
discontinues transmission (Figure 7-2).

7.3

Sequential Read

Sequential reads are initiated in the same way as a ran-
dom read except that after the 24C08B/16B transmits
the first data byte, the master issues an acknowledge
as opposed to a stop condition in a random read. This
directs the 24C08B/16B to transmit the next sequen-
tially addressed 8 bit word (Figure 7-3).

To provide sequential reads the 24C08B/16B contains
an internal address pointer which is incremented by
one at the completion of each operation. This address
pointer allows the entire memory contents to be serially
read during one operation.

7.4

Noise Protection

The 24C08B/16B employs a V

threshold detector

circuit which disables the internal erase/write logic if the
V

is below 1.5 volts at nominal conditions.

The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.

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24C08B/16B

DS21081G-page 8

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2004 Microchip Technology Inc.

FIGURE 7-1:

CURRENT ADDRESS READ

FIGURE 7-2:

RANDOM READ

FIGURE 7-3:

SEQUENTIAL READ

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

S
T
O
P

CONTROL

BYTE

DATA n

A
C
K

N
O

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

S
T
O
P

CONTROL

BYTE

A
C
K

WORD

ADDRESS (n)

CONTROL

BYTE

S
T
A
R
T

DATA (n)

A
C
K

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
O
P

CONTROL

BYTE

A
C
K

DATA n

DATA n + 1

DATA n + 2

DATA n + X

A
C
K

8.0

PIN DESCRIPTIONS

8.1

SDA Serial Address/Data Input/Output

This is a Bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to V

(typical 10 k

Ω

For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi-
tions.

8.2

SCL Serial Clock

This input is used to synchronize the data transfer from
and to the device.

8.3

This pin must be connected to either V

or V

If tied to V

, normal memory operation is enabled

(read/write the entire memory 000-7FF).

If tied to V

, WRITE operations are inhibited. The

entire memory will be write-protected. Read operations
are not affected.

This feature allows the user to use the 24C08B/16B as
a serial ROM when WP is enabled (tied to V

8.4

A0, A1, A2

These pins are not used by the 24C08B/16B. They
may be left floating or tied to either V

or V

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2004 Microchip Technology Inc.

DS21081G-page 9

24C08B/16B

NOTES:

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24C08B/16B

24C08B/16B Product Identification System

To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.

Sales and Support

Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1.

Your local Microchip sales office

The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277

The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.

Package:

P = Plastic DIP (300 mil Body), 8-lead

SL = Plastic SOIC (150 mil Body), 14-lead

SN = Plastic SOIC (150 mil Body), 8-lead

Temperature

Blank = 0°C to +70°C

Range:

= -40°C to +85°C

E = -40

C to +125

Device:

24C08B

8K I

C Serial EEPROM

24C08BT

8K I

C Serial EEPROM (Tape and Reel)

24C16B

16K I

C Serial EEPROM

24C16BT

16K I

C Serial EEPROM (Tape and Reel)

24C08B/16B

–

DS21081G-page 10



2004 Microchip Technology Inc.

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

2004 Microchip Technology Inc.

DS21081G-page 1

FEATURES

• Single supply with operation from 4.5-5.5V
• Low power CMOS technology

- 1 mA active current typical
- 10

A standby current typical at 5.5V

• Organized as 4 or 8 blocks of 256 bytes

(4 x 256 x 8) or (8 x 256 x 8)

• 2-wire serial interface bus, I



compatible

• Schmitt trigger, filtered inputs for noise suppres-

sion

DESCRIPTION

- Commercial (C):

0°C to

+70°C

- Industrial (I):

-40°C to

+85°C

- Automotive (E):

-40°C to +125°C

PACKAGE TYPES

BLOCK DIAGRAM

SCL

SDA

14-lead
SOIC

24
C

08B

24
C

8B
/1

SCL

SDA

24C08B

/16B

SCL

SDA

PDIP

8-lead
SOIC

HV GENERATOR

EEPROM

ARRAY

PAGE LATCHES

YDEC

XDEC

SENSE AMP

R/W CONTROL

MEMORY

CONTROL

LOGIC

I/O

CONTROL

LOGIC

SDA

SCL

24C08B/16B

8K/16K 5.0V I

™

Serial EEPROMs

C is a trademark of Philips Corporation.

Obsolete Device

Please use 24LC08B or 24LC16B.

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24C08B/16B

DS21081G-page 2



2004 Microchip Technology Inc.

1.0

ELECTRICAL CHARACTERISTICS

1.1

Maximum Ratings*

...................................................................................7.0V

All inputs and outputs w.r.t. V

............... -0.6V to V

+1.0V

..................................................≥

4 kV

TABLE 1-1:

PIN FUNCTION TABLE

Name

Function

Ground

SDA

Serial Address/Data I/O

SCL Serial

Clock

Write Protect Input

+4.5V to 5.5V Power Supply

A0, A1, A2

No Internal Connection

TABLE 1-2:

DC CHARACTERISTICS

FIGURE 1-1:

BUS TIMING START/STOP

= +4.5V to +5.5V

Commercial (C): Tamb = 0°C to +70°C
Industrial (I):

Tamb = -40°C to +85°C

Automotive (E):

Tamb = -40°C to +125°C

Parameter

Symbol

Min

Max

Units

Conditions

WP, SCL and SDA pins:

High level input voltage

.7 Vcc

—

Low Level input voltage

—

.3 V

Hysteresis of Schmitt trigger
inputs

HYS

.05 Vcc

—

(Note)

Low level output voltage

—

.40

= 3.0 mA, V

=4.5V

Input leakage current

-10

=.1V to V

Output leakage current

-10

OUT

= .1V to V

Pin capacitance
(all inputs/outputs)

, C

OUT

—

= 5.0V (Note 1)

Tamb = 25°C, F

CLK

=1 MHz

Operating current

write

read

—
—

3
1

mA
mA

= 5.5V, SCL = 400 kHz

Standby current

CCS

—

100

= 5.5V, SDA = SCL = V

WP = V

Note:

This parameter is periodically sampled and not 100% tested.

STA

HYS

STO

START

STOP

SCL

SDA

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2004 Microchip Technology Inc.

DS21081G-page 3

24C08B/16B

TABLE 1-3:

AC CHARACTERISTICS

FIGURE 1-2:

BUS TIMING DATA

Parameter

Symbol

Min

Max

Units

Remarks

Clock frequency

CLK

—

100

kHz

Clock high time

HIGH

4000

—

Clock low time

LOW

4700

—

SDA and SCL rise time

—

1000

(Note1)

SDA and SCL fall time

—

300

(Note 1)

START condition hold time

STA

4000

—

After this period the first clock
pulse is generated

START condition setup
time

STA

4700

—

Only relevant for repeated
START condition

Data input hold time

DAT

—

Data input setup time

DAT

250

—

STOP condition setup time

STO

4000

—

Output valid from clock

—

3500

(Note 2)

Bus free time

BUF

4700

—

Time the bus must be free before
a new transmission can start

Output fall time from V

min to V

max

—

250

(Note 1), C

≤

100 pF

Input filter spike suppres-
sion (SDA and SCL pins)

—

(Note 3)

Write cycle time

—

Byte or Page mode

Endurance

—

cycles

25°C, V

= 5.0V, Block Mode

(Note 4)

Note 1: Not 100% tested. C

= total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3: The combined T

and V

HYS

specifications are due to new Schmitt trigger inputs which provide improved

noise and spike suppression. This eliminates the need for a T

specification.

4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific

application, please consult the Total Endurance Model which can be obtained on our website.

STA

LOW

HIGH

DAT

STO

STA

BUF

STA

SCL

SDA

OUT

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24C08B/16B

DS21081G-page 4



2004 Microchip Technology Inc.

2.0

FUNCTIONAL DESCRIPTION

3.0

BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been
defined (Figure 3-1).

3.1

Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2

Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START condi-
tion.

3.3

Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.

3.4

Data Valid (D)

The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.

3.5

Acknowledge

Note:

The 24C08B/16B does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.

FIGURE 3-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

SCL

SDA

(A)

(B)

(D)

(A)

(C)

START

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

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

2004 Microchip Technology Inc.

DS21081G-page 5

24C08B/16B

3.6

Device Addressing

FIGURE 3-2:

CONTROL BYTE
ALLOCATION

Operation

Control

Code

Block Select

R/W

Read

1010

Block Address

Write

1010

Block Address

SLAVE ADDRESS

R/W

START

READ/WRITE

4.0

WRITE OPERATION

4.1

Byte Write

4.2

Page Write

Note:

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21081G-html.html

24C08B/16B

DS21081G-page 6



2004 Microchip Technology Inc.

FIGURE 4-1:

BYTE WRITE

FIGURE 4-2:

PAGE WRITE

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

S
T
O
P

CONTROL

BYTE

WORD

ADDRESS

DATA

A
C
K

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

CONTROL

BYTE

WORD

ADDRESS (n)

DATA n

DATA n + 15

S
T
O
P

A
C
K

DATA n + 1

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

2004 Microchip Technology Inc.

DS21081G-page 7

24C08B/16B

5.0

ACKNOWLEDGE POLLING

FIGURE 5-1:

ACKNOWLEDGE POLLING
FLOW

6.0

WRITE PROTECTION

The 24C08B/16B can be used as a serial ROM when
the WP pin is connected to V

. Programming will be

inhibited and the entire memory will be write-protected.

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

Operation

YES

7.0

READ OPERATION

7.1

Current Address Read

the

7.2

Random Read

7.3

Sequential Read

7.4

Noise Protection

The 24C08B/16B employs a V

threshold detector

circuit which disables the internal erase/write logic if the
V

is below 1.5 volts at nominal conditions.

The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.

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24C08B/16B

DS21081G-page 8



2004 Microchip Technology Inc.

FIGURE 7-1:

CURRENT ADDRESS READ

FIGURE 7-2:

RANDOM READ

FIGURE 7-3:

SEQUENTIAL READ

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

S
T
O
P

CONTROL

BYTE

DATA n

A
C
K

N
O

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

S
T
O
P

CONTROL

BYTE

A
C
K

WORD

ADDRESS (n)

CONTROL

BYTE

S
T
A
R
T

DATA (n)

A
C
K

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
O
P

CONTROL

BYTE

A
C
K

DATA n

DATA n + 1

DATA n + 2

DATA n + X

A
C
K

8.0

PIN DESCRIPTIONS

8.1

SDA Serial Address/Data Input/Output

This is a Bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to V

(typical 10 k

Ω

For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi-
tions.

8.2

SCL Serial Clock

This input is used to synchronize the data transfer from
and to the device.

8.3

This pin must be connected to either V

or V

If tied to V

, normal memory operation is enabled

(read/write the entire memory 000-7FF).

If tied to V

, WRITE operations are inhibited. The

entire memory will be write-protected. Read operations
are not affected.

This feature allows the user to use the 24C08B/16B as
a serial ROM when WP is enabled (tied to V

8.4

A0, A1, A2

These pins are not used by the 24C08B/16B. They
may be left floating or tied to either V

or V

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

2004 Microchip Technology Inc.

DS21081G-page 9

24C08B/16B

NOTES:

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21081G-html.html

24C08B/16B

24C08B/16B Product Identification System

To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.

Sales and Support

Your local Microchip sales office

The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277

The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.

Package:

P = Plastic DIP (300 mil Body), 8-lead

SL = Plastic SOIC (150 mil Body), 14-lead

SN = Plastic SOIC (150 mil Body), 8-lead

Temperature

Blank = 0°C to +70°C

Range:

= -40°C to +85°C

E = -40

C to +125

Device:

24C08B

8K I

C Serial EEPROM

24C08BT

8K I

C Serial EEPROM (Tape and Reel)

24C16B

16K I

C Serial EEPROM

24C16BT

16K I

C Serial EEPROM (Tape and Reel)

24C08B/16B

–

DS21081G-page 10



2004 Microchip Technology Inc.

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

2004 Microchip Technology Inc.

DS21081G-page 1

FEATURES

• Single supply with operation from 4.5-5.5V
• Low power CMOS technology

- 1 mA active current typical
- 10

A standby current typical at 5.5V

• Organized as 4 or 8 blocks of 256 bytes

(4 x 256 x 8) or (8 x 256 x 8)

• 2-wire serial interface bus, I



compatible

• Schmitt trigger, filtered inputs for noise suppres-

sion

DESCRIPTION

- Commercial (C):

0°C to

+70°C

- Industrial (I):

-40°C to

+85°C

- Automotive (E):

-40°C to +125°C

PACKAGE TYPES

BLOCK DIAGRAM

SCL

SDA

14-lead
SOIC

24
C

08B

24
C

8B
/1

SCL

SDA

24C08B

/16B

SCL

SDA

PDIP

8-lead
SOIC

HV GENERATOR

EEPROM

ARRAY

PAGE LATCHES

YDEC

XDEC

SENSE AMP

R/W CONTROL

MEMORY

CONTROL

LOGIC

I/O

CONTROL

LOGIC

SDA

SCL

24C08B/16B

8K/16K 5.0V I

™

Serial EEPROMs

C is a trademark of Philips Corporation.

Obsolete Device

Please use 24LC08B or 24LC16B.

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21081G-html.html

24C08B/16B

DS21081G-page 2



2004 Microchip Technology Inc.

1.0

ELECTRICAL CHARACTERISTICS

1.1

Maximum Ratings*

...................................................................................7.0V

All inputs and outputs w.r.t. V

............... -0.6V to V

+1.0V

..................................................≥

4 kV

TABLE 1-1:

PIN FUNCTION TABLE

Name

Function

Ground

SDA

Serial Address/Data I/O

SCL Serial

Clock

Write Protect Input

+4.5V to 5.5V Power Supply

A0, A1, A2

No Internal Connection

TABLE 1-2:

DC CHARACTERISTICS

FIGURE 1-1:

BUS TIMING START/STOP

= +4.5V to +5.5V

Commercial (C): Tamb = 0°C to +70°C
Industrial (I):

Tamb = -40°C to +85°C

Automotive (E):

Tamb = -40°C to +125°C

Parameter

Symbol

Min

Max

Units

Conditions

WP, SCL and SDA pins:

High level input voltage

.7 Vcc

—

Low Level input voltage

—

.3 V

Hysteresis of Schmitt trigger
inputs

HYS

.05 Vcc

—

(Note)

Low level output voltage

—

.40

= 3.0 mA, V

=4.5V

Input leakage current

-10

=.1V to V

Output leakage current

-10

OUT

= .1V to V

Pin capacitance
(all inputs/outputs)

, C

OUT

—

= 5.0V (Note 1)

Tamb = 25°C, F

CLK

=1 MHz

Operating current

write

read

—
—

3
1

mA
mA

= 5.5V, SCL = 400 kHz

Standby current

CCS

—

100

= 5.5V, SDA = SCL = V

WP = V

Note:

This parameter is periodically sampled and not 100% tested.

STA

HYS

STO

START

STOP

SCL

SDA

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

2004 Microchip Technology Inc.

DS21081G-page 3

24C08B/16B

TABLE 1-3:

AC CHARACTERISTICS

FIGURE 1-2:

BUS TIMING DATA

Parameter

Symbol

Min

Max

Units

Remarks

Clock frequency

CLK

—

100

kHz

Clock high time

HIGH

4000

—

Clock low time

LOW

4700

—

SDA and SCL rise time

—

1000

(Note1)

SDA and SCL fall time

—

300

(Note 1)

START condition hold time

STA

4000

—

After this period the first clock
pulse is generated

START condition setup
time

STA

4700

—

Only relevant for repeated
START condition

Data input hold time

DAT

—

Data input setup time

DAT

250

—

STOP condition setup time

STO

4000

—

Output valid from clock

—

3500

(Note 2)

Bus free time

BUF

4700

—

Time the bus must be free before
a new transmission can start

Output fall time from V

min to V

max

—

250

(Note 1), C

≤

100 pF

Input filter spike suppres-
sion (SDA and SCL pins)

—

(Note 3)

Write cycle time

—

Byte or Page mode

Endurance

—

cycles

25°C, V

= 5.0V, Block Mode

(Note 4)

Note 1: Not 100% tested. C

= total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3: The combined T

and V

HYS

specifications are due to new Schmitt trigger inputs which provide improved

noise and spike suppression. This eliminates the need for a T

specification.

4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific

application, please consult the Total Endurance Model which can be obtained on our website.

STA

LOW

HIGH

DAT

STO

STA

BUF

STA

SCL

SDA

OUT

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24C08B/16B

DS21081G-page 4



2004 Microchip Technology Inc.

2.0

FUNCTIONAL DESCRIPTION

3.0

BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been
defined (Figure 3-1).

3.1

Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2

Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START condi-
tion.

3.3

Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.

3.4

Data Valid (D)

The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.

3.5

Acknowledge

Note:

The 24C08B/16B does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.

FIGURE 3-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

SCL

SDA

(A)

(B)

(D)

(A)

(C)

START

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

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

2004 Microchip Technology Inc.

DS21081G-page 5

24C08B/16B

3.6

Device Addressing

FIGURE 3-2:

CONTROL BYTE
ALLOCATION

Operation

Control

Code

Block Select

R/W

Read

1010

Block Address

Write

1010

Block Address

SLAVE ADDRESS

R/W

START

READ/WRITE

4.0

WRITE OPERATION

4.1

Byte Write

4.2

Page Write

Note:

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21081G-html.html

24C08B/16B

DS21081G-page 6



2004 Microchip Technology Inc.

FIGURE 4-1:

BYTE WRITE

FIGURE 4-2:

PAGE WRITE

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

S
T
O
P

CONTROL

BYTE

WORD

ADDRESS

DATA

A
C
K

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

CONTROL

BYTE

WORD

ADDRESS (n)

DATA n

DATA n + 15

S
T
O
P

A
C
K

DATA n + 1

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

2004 Microchip Technology Inc.

DS21081G-page 7

24C08B/16B

5.0

ACKNOWLEDGE POLLING

FIGURE 5-1:

ACKNOWLEDGE POLLING
FLOW

6.0

WRITE PROTECTION

The 24C08B/16B can be used as a serial ROM when
the WP pin is connected to V

. Programming will be

inhibited and the entire memory will be write-protected.

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

Operation

YES

7.0

READ OPERATION

7.1

Current Address Read

the

7.2

Random Read

7.3

Sequential Read

7.4

Noise Protection

The 24C08B/16B employs a V

threshold detector

circuit which disables the internal erase/write logic if the
V

is below 1.5 volts at nominal conditions.

The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21081G-html.html

24C08B/16B

DS21081G-page 8



2004 Microchip Technology Inc.

FIGURE 7-1:

CURRENT ADDRESS READ

FIGURE 7-2:

RANDOM READ

FIGURE 7-3:

SEQUENTIAL READ

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

S
T
O
P

CONTROL

BYTE

DATA n

A
C
K

N
O

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

S
T
O
P

CONTROL

BYTE

A
C
K

WORD

ADDRESS (n)

CONTROL

BYTE

S
T
A
R
T

DATA (n)

A
C
K

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
O
P

CONTROL

BYTE

A
C
K

DATA n

DATA n + 1

DATA n + 2

DATA n + X

A
C
K

8.0

PIN DESCRIPTIONS

8.1

SDA Serial Address/Data Input/Output

This is a Bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to V

(typical 10 k

Ω

For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi-
tions.

8.2

SCL Serial Clock

This input is used to synchronize the data transfer from
and to the device.

8.3

This pin must be connected to either V

or V

If tied to V

, normal memory operation is enabled

(read/write the entire memory 000-7FF).

If tied to V

, WRITE operations are inhibited. The

entire memory will be write-protected. Read operations
are not affected.

This feature allows the user to use the 24C08B/16B as
a serial ROM when WP is enabled (tied to V

8.4

A0, A1, A2

These pins are not used by the 24C08B/16B. They
may be left floating or tied to either V

or V

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21081G-html.html



2004 Microchip Technology Inc.

DS21081G-page 9

24C08B/16B

NOTES:

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21081G-html.html

24C08B/16B

24C08B/16B Product Identification System

To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.

Sales and Support

Your local Microchip sales office

The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277

The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.

Package:

P = Plastic DIP (300 mil Body), 8-lead

SL = Plastic SOIC (150 mil Body), 14-lead

SN = Plastic SOIC (150 mil Body), 8-lead

Temperature

Blank = 0°C to +70°C

Range:

= -40°C to +85°C

E = -40

C to +125

Device:

24C08B

8K I

C Serial EEPROM

24C08BT

8K I

C Serial EEPROM (Tape and Reel)

24C16B

16K I

C Serial EEPROM

24C16BT

16K I

C Serial EEPROM (Tape and Reel)

24C08B/16B

–

DS21081G-page 10



2004 Microchip Technology Inc.

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21081G-html.html



2004 Microchip Technology Inc.

DS21081G-page 1

FEATURES

• Single supply with operation from 4.5-5.5V
• Low power CMOS technology

- 1 mA active current typical
- 10

A standby current typical at 5.5V

• Organized as 4 or 8 blocks of 256 bytes

(4 x 256 x 8) or (8 x 256 x 8)

• 2-wire serial interface bus, I



compatible

• Schmitt trigger, filtered inputs for noise suppres-

sion

DESCRIPTION

- Commercial (C):

0°C to

+70°C

- Industrial (I):

-40°C to

+85°C

- Automotive (E):

-40°C to +125°C

PACKAGE TYPES

BLOCK DIAGRAM

SCL

SDA

14-lead
SOIC

24
C

08B

24
C

8B
/1

SCL

SDA

24C08B

/16B

SCL

SDA

PDIP

8-lead
SOIC

HV GENERATOR

EEPROM

ARRAY

PAGE LATCHES

YDEC

XDEC

SENSE AMP

R/W CONTROL

MEMORY

CONTROL

LOGIC

I/O

CONTROL

LOGIC

SDA

SCL

24C08B/16B

8K/16K 5.0V I

™

Serial EEPROMs

C is a trademark of Philips Corporation.

Obsolete Device

Please use 24LC08B or 24LC16B.

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21081G-html.html

24C08B/16B

DS21081G-page 2



2004 Microchip Technology Inc.

1.0

ELECTRICAL CHARACTERISTICS

1.1

Maximum Ratings*

...................................................................................7.0V

All inputs and outputs w.r.t. V

............... -0.6V to V

+1.0V

..................................................≥

4 kV

TABLE 1-1:

PIN FUNCTION TABLE

Name

Function

Ground

SDA

Serial Address/Data I/O

SCL Serial

Clock

Write Protect Input

+4.5V to 5.5V Power Supply

A0, A1, A2

No Internal Connection

TABLE 1-2:

DC CHARACTERISTICS

FIGURE 1-1:

BUS TIMING START/STOP

= +4.5V to +5.5V

Commercial (C): Tamb = 0°C to +70°C
Industrial (I):

Tamb = -40°C to +85°C

Automotive (E):

Tamb = -40°C to +125°C

Parameter

Symbol

Min

Max

Units

Conditions

WP, SCL and SDA pins:

High level input voltage

.7 Vcc

—

Low Level input voltage

—

.3 V

Hysteresis of Schmitt trigger
inputs

HYS

.05 Vcc

—

(Note)

Low level output voltage

—

.40

= 3.0 mA, V

=4.5V

Input leakage current

-10

=.1V to V

Output leakage current

-10

OUT

= .1V to V

Pin capacitance
(all inputs/outputs)

, C

OUT

—

= 5.0V (Note 1)

Tamb = 25°C, F

CLK

=1 MHz

Operating current

write

read

—
—

3
1

mA
mA

= 5.5V, SCL = 400 kHz

Standby current

CCS

—

100

= 5.5V, SDA = SCL = V

WP = V

Note:

This parameter is periodically sampled and not 100% tested.

STA

HYS

STO

START

STOP

SCL

SDA

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2004 Microchip Technology Inc.

DS21081G-page 3

24C08B/16B

TABLE 1-3:

AC CHARACTERISTICS

FIGURE 1-2:

BUS TIMING DATA

Parameter

Symbol

Min

Max

Units

Remarks

Clock frequency

CLK

—

100

kHz

Clock high time

HIGH

4000

—

Clock low time

LOW

4700

—

SDA and SCL rise time

—

1000

(Note1)

SDA and SCL fall time

—

300

(Note 1)

START condition hold time

STA

4000

—

After this period the first clock
pulse is generated

START condition setup
time

STA

4700

—

Only relevant for repeated
START condition

Data input hold time

DAT

—

Data input setup time

DAT

250

—

STOP condition setup time

STO

4000

—

Output valid from clock

—

3500

(Note 2)

Bus free time

BUF

4700

—

Time the bus must be free before
a new transmission can start

Output fall time from V

min to V

max

—

250

(Note 1), C

≤

100 pF

Input filter spike suppres-
sion (SDA and SCL pins)

—

(Note 3)

Write cycle time

—

Byte or Page mode

Endurance

—

cycles

25°C, V

= 5.0V, Block Mode

(Note 4)

Note 1: Not 100% tested. C

= total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3: The combined T

and V

HYS

specifications are due to new Schmitt trigger inputs which provide improved

noise and spike suppression. This eliminates the need for a T

specification.

4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific

application, please consult the Total Endurance Model which can be obtained on our website.

STA

LOW

HIGH

DAT

STO

STA

BUF

STA

SCL

SDA

OUT

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24C08B/16B

DS21081G-page 4



2004 Microchip Technology Inc.

2.0

FUNCTIONAL DESCRIPTION

3.0

BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been
defined (Figure 3-1).

3.1

Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2

Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START condi-
tion.

3.3

Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.

3.4

Data Valid (D)

The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.

3.5

Acknowledge

Note:

The 24C08B/16B does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.

FIGURE 3-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

SCL

SDA

(A)

(B)

(D)

(A)

(C)

START

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

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

2004 Microchip Technology Inc.

DS21081G-page 5

24C08B/16B

3.6

Device Addressing

FIGURE 3-2:

CONTROL BYTE
ALLOCATION

Operation

Control

Code

Block Select

R/W

Read

1010

Block Address

Write

1010

Block Address

SLAVE ADDRESS

R/W

START

READ/WRITE

4.0

WRITE OPERATION

4.1

Byte Write

4.2

Page Write

Note:

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24C08B/16B

DS21081G-page 6



2004 Microchip Technology Inc.

FIGURE 4-1:

BYTE WRITE

FIGURE 4-2:

PAGE WRITE

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

S
T
O
P

CONTROL

BYTE

WORD

ADDRESS

DATA

A
C
K

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

CONTROL

BYTE

WORD

ADDRESS (n)

DATA n

DATA n + 15

S
T
O
P

A
C
K

DATA n + 1

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

2004 Microchip Technology Inc.

DS21081G-page 7

24C08B/16B

5.0

ACKNOWLEDGE POLLING

FIGURE 5-1:

ACKNOWLEDGE POLLING
FLOW

6.0

WRITE PROTECTION

The 24C08B/16B can be used as a serial ROM when
the WP pin is connected to V

. Programming will be

inhibited and the entire memory will be write-protected.

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

Operation

YES

7.0

READ OPERATION

7.1

Current Address Read

the

7.2

Random Read

7.3

Sequential Read

7.4

Noise Protection

The 24C08B/16B employs a V

threshold detector

circuit which disables the internal erase/write logic if the
V

is below 1.5 volts at nominal conditions.

The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.

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24C08B/16B

DS21081G-page 8



2004 Microchip Technology Inc.

FIGURE 7-1:

CURRENT ADDRESS READ

FIGURE 7-2:

RANDOM READ

FIGURE 7-3:

SEQUENTIAL READ

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

S
T
O
P

CONTROL

BYTE

DATA n

A
C
K

N
O

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

S
T
O
P

CONTROL

BYTE

A
C
K

WORD

ADDRESS (n)

CONTROL

BYTE

S
T
A
R
T

DATA (n)

A
C
K

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
O
P

CONTROL

BYTE

A
C
K

DATA n

DATA n + 1

DATA n + 2

DATA n + X

A
C
K

8.0

PIN DESCRIPTIONS

8.1

SDA Serial Address/Data Input/Output

This is a Bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to V

(typical 10 k

Ω

For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi-
tions.

8.2

SCL Serial Clock

This input is used to synchronize the data transfer from
and to the device.

8.3

This pin must be connected to either V

or V

If tied to V

, normal memory operation is enabled

(read/write the entire memory 000-7FF).

If tied to V

, WRITE operations are inhibited. The

entire memory will be write-protected. Read operations
are not affected.

This feature allows the user to use the 24C08B/16B as
a serial ROM when WP is enabled (tied to V

8.4

A0, A1, A2

These pins are not used by the 24C08B/16B. They
may be left floating or tied to either V

or V

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

2004 Microchip Technology Inc.

DS21081G-page 9

24C08B/16B

NOTES:

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24C08B/16B

24C08B/16B Product Identification System

To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.

Sales and Support

Your local Microchip sales office

The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277

The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.

Package:

P = Plastic DIP (300 mil Body), 8-lead

SL = Plastic SOIC (150 mil Body), 14-lead

SN = Plastic SOIC (150 mil Body), 8-lead

Temperature

Blank = 0°C to +70°C

Range:

= -40°C to +85°C

E = -40

C to +125

Device:

24C08B

8K I

C Serial EEPROM

24C08BT

8K I

C Serial EEPROM (Tape and Reel)

24C16B

16K I

C Serial EEPROM

24C16BT

16K I

C Serial EEPROM (Tape and Reel)

24C08B/16B

–

DS21081G-page 10



2004 Microchip Technology Inc.

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

2004 Microchip Technology Inc.

DS21081G-page 1

FEATURES

• Single supply with operation from 4.5-5.5V
• Low power CMOS technology

- 1 mA active current typical
- 10

A standby current typical at 5.5V

• Organized as 4 or 8 blocks of 256 bytes

(4 x 256 x 8) or (8 x 256 x 8)

• 2-wire serial interface bus, I



compatible

• Schmitt trigger, filtered inputs for noise suppres-

sion

DESCRIPTION

- Commercial (C):

0°C to

+70°C

- Industrial (I):

-40°C to

+85°C

- Automotive (E):

-40°C to +125°C

PACKAGE TYPES

BLOCK DIAGRAM

SCL

SDA

14-lead
SOIC

24
C

08B

24
C

8B
/1

SCL

SDA

24C08B

/16B

SCL

SDA

PDIP

8-lead
SOIC

HV GENERATOR

EEPROM

ARRAY

PAGE LATCHES

YDEC

XDEC

SENSE AMP

R/W CONTROL

MEMORY

CONTROL

LOGIC

I/O

CONTROL

LOGIC

SDA

SCL

24C08B/16B

8K/16K 5.0V I

™

Serial EEPROMs

C is a trademark of Philips Corporation.

Obsolete Device

Please use 24LC08B or 24LC16B.

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24C08B/16B

DS21081G-page 2



2004 Microchip Technology Inc.

1.0

ELECTRICAL CHARACTERISTICS

1.1

Maximum Ratings*

...................................................................................7.0V

All inputs and outputs w.r.t. V

............... -0.6V to V

+1.0V

..................................................≥

4 kV

TABLE 1-1:

PIN FUNCTION TABLE

Name

Function

Ground

SDA

Serial Address/Data I/O

SCL Serial

Clock

Write Protect Input

+4.5V to 5.5V Power Supply

A0, A1, A2

No Internal Connection

TABLE 1-2:

DC CHARACTERISTICS

FIGURE 1-1:

BUS TIMING START/STOP

= +4.5V to +5.5V

Commercial (C): Tamb = 0°C to +70°C
Industrial (I):

Tamb = -40°C to +85°C

Automotive (E):

Tamb = -40°C to +125°C

Parameter

Symbol

Min

Max

Units

Conditions

WP, SCL and SDA pins:

High level input voltage

.7 Vcc

—

Low Level input voltage

—

.3 V

Hysteresis of Schmitt trigger
inputs

HYS

.05 Vcc

—

(Note)

Low level output voltage

—

.40

= 3.0 mA, V

=4.5V

Input leakage current

-10

=.1V to V

Output leakage current

-10

OUT

= .1V to V

Pin capacitance
(all inputs/outputs)

, C

OUT

—

= 5.0V (Note 1)

Tamb = 25°C, F

CLK

=1 MHz

Operating current

write

read

—
—

3
1

mA
mA

= 5.5V, SCL = 400 kHz

Standby current

CCS

—

100

= 5.5V, SDA = SCL = V

WP = V

Note:

This parameter is periodically sampled and not 100% tested.

STA

HYS

STO

START

STOP

SCL

SDA

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

2004 Microchip Technology Inc.

DS21081G-page 3

24C08B/16B

TABLE 1-3:

AC CHARACTERISTICS

FIGURE 1-2:

BUS TIMING DATA

Parameter

Symbol

Min

Max

Units

Remarks

Clock frequency

CLK

—

100

kHz

Clock high time

HIGH

4000

—

Clock low time

LOW

4700

—

SDA and SCL rise time

—

1000

(Note1)

SDA and SCL fall time

—

300

(Note 1)

START condition hold time

STA

4000

—

After this period the first clock
pulse is generated

START condition setup
time

STA

4700

—

Only relevant for repeated
START condition

Data input hold time

DAT

—

Data input setup time

DAT

250

—

STOP condition setup time

STO

4000

—

Output valid from clock

—

3500

(Note 2)

Bus free time

BUF

4700

—

Time the bus must be free before
a new transmission can start

Output fall time from V

min to V

max

—

250

(Note 1), C

≤

100 pF

Input filter spike suppres-
sion (SDA and SCL pins)

—

(Note 3)

Write cycle time

—

Byte or Page mode

Endurance

—

cycles

25°C, V

= 5.0V, Block Mode

(Note 4)

Note 1: Not 100% tested. C

= total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3: The combined T

and V

HYS

specifications are due to new Schmitt trigger inputs which provide improved

noise and spike suppression. This eliminates the need for a T

specification.

4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific

application, please consult the Total Endurance Model which can be obtained on our website.

STA

LOW

HIGH

DAT

STO

STA

BUF

STA

SCL

SDA

OUT

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24C08B/16B

DS21081G-page 4



2004 Microchip Technology Inc.

2.0

FUNCTIONAL DESCRIPTION

3.0

BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been
defined (Figure 3-1).

3.1

Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2

Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START condi-
tion.

3.3

Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.

3.4

Data Valid (D)

The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.

3.5

Acknowledge

Note:

The 24C08B/16B does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.

FIGURE 3-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

SCL

SDA

(A)

(B)

(D)

(A)

(C)

START

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

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

2004 Microchip Technology Inc.

DS21081G-page 5

24C08B/16B

3.6

Device Addressing

FIGURE 3-2:

CONTROL BYTE
ALLOCATION

Operation

Control

Code

Block Select

R/W

Read

1010

Block Address

Write

1010

Block Address

SLAVE ADDRESS

R/W

START

READ/WRITE

4.0

WRITE OPERATION

4.1

Byte Write

4.2

Page Write

Note:

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24C08B/16B

DS21081G-page 6



2004 Microchip Technology Inc.

FIGURE 4-1:

BYTE WRITE

FIGURE 4-2:

PAGE WRITE

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

S
T
O
P

CONTROL

BYTE

WORD

ADDRESS

DATA

A
C
K

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

CONTROL

BYTE

WORD

ADDRESS (n)

DATA n

DATA n + 15

S
T
O
P

A
C
K

DATA n + 1

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

2004 Microchip Technology Inc.

DS21081G-page 7

24C08B/16B

5.0

ACKNOWLEDGE POLLING

FIGURE 5-1:

ACKNOWLEDGE POLLING
FLOW

6.0

WRITE PROTECTION

The 24C08B/16B can be used as a serial ROM when
the WP pin is connected to V

. Programming will be

inhibited and the entire memory will be write-protected.

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

Operation

YES

7.0

READ OPERATION

7.1

Current Address Read

the

7.2

Random Read

7.3

Sequential Read

7.4

Noise Protection

The 24C08B/16B employs a V

threshold detector

circuit which disables the internal erase/write logic if the
V

is below 1.5 volts at nominal conditions.

The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.

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24C08B/16B

DS21081G-page 8



2004 Microchip Technology Inc.

FIGURE 7-1:

CURRENT ADDRESS READ

FIGURE 7-2:

RANDOM READ

FIGURE 7-3:

SEQUENTIAL READ

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

S
T
O
P

CONTROL

BYTE

DATA n

A
C
K

N
O

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

S
T
O
P

CONTROL

BYTE

A
C
K

WORD

ADDRESS (n)

CONTROL

BYTE

S
T
A
R
T

DATA (n)

A
C
K

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
O
P

CONTROL

BYTE

A
C
K

DATA n

DATA n + 1

DATA n + 2

DATA n + X

A
C
K

8.0

PIN DESCRIPTIONS

8.1

SDA Serial Address/Data Input/Output

This is a Bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to V

(typical 10 k

Ω

For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi-
tions.

8.2

SCL Serial Clock

This input is used to synchronize the data transfer from
and to the device.

8.3

This pin must be connected to either V

or V

If tied to V

, normal memory operation is enabled

(read/write the entire memory 000-7FF).

If tied to V

, WRITE operations are inhibited. The

entire memory will be write-protected. Read operations
are not affected.

This feature allows the user to use the 24C08B/16B as
a serial ROM when WP is enabled (tied to V

8.4

A0, A1, A2

These pins are not used by the 24C08B/16B. They
may be left floating or tied to either V

or V

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

2004 Microchip Technology Inc.

DS21081G-page 9

24C08B/16B

NOTES:

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21081G-html.html

24C08B/16B

24C08B/16B Product Identification System

To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.

Sales and Support

Your local Microchip sales office

The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277

The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.

Package:

P = Plastic DIP (300 mil Body), 8-lead

SL = Plastic SOIC (150 mil Body), 14-lead

SN = Plastic SOIC (150 mil Body), 8-lead

Temperature

Blank = 0°C to +70°C

Range:

= -40°C to +85°C

E = -40

C to +125

Device:

24C08B

8K I

C Serial EEPROM

24C08BT

8K I

C Serial EEPROM (Tape and Reel)

24C16B

16K I

C Serial EEPROM

24C16BT

16K I

C Serial EEPROM (Tape and Reel)

24C08B/16B

–

DS21081G-page 10



2004 Microchip Technology Inc.

Maker

Microchip Technology Inc.

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