2015 Microchip Technology Inc.
DS20005045C-page 1
Features
• Single Voltage Read and Write Operations
- 2.7-3.6V
• Serial Interface Architecture
- SPI Compatible: Mode 0 and Mode 3
• High Speed Clock Frequency
- 50/66 MHz conditional (see
Table 5-6
)
• Superior Reliability
- Endurance: 100,000 Cycles (typical)
- Greater than 100 years Data Retention
• Low Power Consumption:
- Active Read Current: 10 mA (typical)
- Standby Current: 5 µA (typical)
• Flexible Erase Capability
- Uniform 4 KByte sectors
- Uniform 32 KByte overlay blocks
- Uniform 64 KByte overlay blocks
• Fast Erase and Byte-Program:
- Chip-Erase Time: 35 ms (typical)
- Sector-/Block-Erase Time: 18 ms (typical)
- Byte-Program Time: 7 µs (typical)
• Auto Address Increment (AAI) Programming
- Decrease total chip programming time over
Byte-Program operations
• End-of-Write Detection
- Software polling the BUSY bit in Status Register
- Busy Status readout on SO pin in AAI Mode
• Hold Pin (HOLD#)
- Suspends a serial sequence to the memory
without deselecting the device
• Write Protection (WP#)
- Enables/Disables the Lock-Down function of the
status register
• Software Write Protection
- Write protection through Block-Protection bits in
status register
• Temperature Range
- Commercial: 0°C to +70°C
- Industrial: -40°C to +85°C
• Packages Available
- 8-lead SOIC (200 mils)
- 8-contact WSON (6mm x 5mm)
- 8-lead PDIP (300 mils)
• All devices are RoHS compliant
Product Description
25 series Serial Flash family features a four-wire, SPI-
compatible interface that allows for a low pin-count
package which occupies less board space and ulti-
mately lowers total system costs. The SST25VF080B
devices are enhanced with improved operating fre-
quency and lower power consumption. SST25VF080B
SPI serial flash memories are manufactured with pro-
prietary, high-performance CMOS SuperFlash technol-
ogy. The split-gate cell design and thick-oxide tunneling
injector attain better reliability and manufacturability
compared with alternate approaches.
The SST25VF080B devices significantly improve per-
formance and reliability, while lowering power con-
sumption. The devices write (Program or Erase) with a
single power supply of 2.7-3.6V for SST25VF080B.
The total energy consumed is a function of the applied
voltage, current, and time of application. Since for any
given voltage range, the SuperFlash technology uses
less current to program and has a shorter erase time,
the total energy consumed during any Erase or Pro-
gram operation is less than alternative flash memory
technologies.
The SST25VF080B device is offered in 8-lead SOIC
(200 mils), 8-contact WSON (6mm x 5mm), and 8-lead
PDIP (300 mils) packages. See
Figure 2-1
for pin
assignments.
SST25VF080B
8 Mbit SPI Serial Flash
SST25VF080B
DS20005045C-page 2
2015 Microchip Technology Inc.
1.0
BLOCK DIAGRAM
FIGURE 1-1:
FUNCTIONAL BLOCK DIAGRAM
1296 B1.0
I/O Buffers
and
Data Latches
SuperFlash
Memory
X - Decoder
Control Logic
Address
Buffers
and
Latches
CE#
Y - Decoder
SCK
SI
SO
WP#
HOLD#
Serial Interface
2015 Microchip Technology Inc.
DS20005045C-page 3
SST25VF080B
2.0
PIN DESCRIPTION
FIGURE 2-1:
PIN ASSIGNMENTS
TABLE 2-1:
PIN DESCRIPTION
Symbol
Pin Name
Functions
SCK
Serial Clock
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock
input, while output data is shifted out on the falling edge of the clock input.
SI
Serial Data Input
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
SO
Serial Data Output
To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
Outputs Flash busy status during AAI Programming when reconfigured as RY/BY#
pin. See
“Hardware End-of-Write Detection” on page 10
for details.
CE#
Chip Enable
The device is enabled by a high to low transition on CE#. CE# must remain low for
the duration of any command sequence.
WP#
Write Protect
The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
HOLD#
Hold
To temporarily stop serial communication with SPI flash memory without resetting
the device.
V
DD
Power Supply
To provide power supply voltage: 2.7-3.6V for SST25VF080B
V
SS
Ground
1
2
3
4
8
7
6
5
CE#
SO
WP#
VSS
VDD
HOLD#
SCK
SI
Top View
1296 08-soic S2A P1.0
1
2
3
4
8
7
6
5
CE#
SO
WP#
VSS
Top View
VDD
HOLD#
SCK
SI
1296 08-wson QA P2.0
8-lead SOIC
8-contact WSON
CE#
SO
WP#
VSS
VDD
HOLD#
SCK
SI
Top View
1296 08-pdip-PA-P3.0
8-lead PDIP
SST25VF080B
DS20005045C-page 4
2015 Microchip Technology Inc.
3.0
MEMORY ORGANIZATION
The SST25VF080B SuperFlash memory array is orga-
nized in uniform 4 KByte erasable sectors with 32
KByte overlay blocks and 64 KByte overlay erasable
blocks.
4.0
DEVICE OPERATION
The SST25VF080B is accessed through the SPI (Serial
Peripheral Interface) bus compatible protocol. The SPI
bus consist of four control lines; Chip Enable (CE#) is
used to select the device, and data is accessed through
the Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK).
The SST25VF080B supports both Mode 0 (0,0) and
Mode 3 (1,1) of SPI bus operations. The difference
between the two modes, as shown in
Figure 4-1
, is the
state of the SCK signal when the bus master is in
Stand-by mode and no data is being transferred. The
SCK signal is low for Mode 0 and SCK signal is high for
Mode 3. For both modes, the Serial Data In (SI) is sam-
pled at the rising edge of the SCK clock signal and the
Serial Data Output (SO) is driven after the falling edge
of the SCK clock signal.
FIGURE 4-1:
SPI PROTOCOL
4.1
Hold Operation
The HOLD# pin is used to pause a serial sequence
underway with the SPI flash memory without resetting
the clocking sequence. To activate the HOLD# mode,
CE# must be in active low state. The HOLD# mode
begins when the SCK active low state coincides with
the falling edge of the HOLD# signal. The HOLD mode
ends when the HOLD# signal’s rising edge coincides
with the SCK active low state.
If the falling edge of the HOLD# signal does not coin-
cide with the SCK active low state, then the device
enters Hold mode when the SCK next reaches the
active low state. Similarly, if the rising edge of the
HOLD# signal does not coincide with the SCK active
low state, then the device exits in Hold mode when the
SCK next reaches the active low state. See
Figure 4-2
for Hold Condition waveform.
Once the device enters Hold mode, SO will be in high-
impedance state while SI and SCK can be V
IL
or V
IH.
If CE# is driven active high during a Hold condition, it
resets the internal logic of the device. As long as
HOLD# signal is low, the memory remains in the Hold
condition. To resume communication with the device,
HOLD# must be driven active high, and CE# must be
driven active low. See
Figure 5-3
for Hold timing.
FIGURE 4-2:
HOLD CONDITION WAVEFORM
1296 SPIprot.0
MODE 3
SCK
SI
SO
CE#
MODE 3
DON'T CARE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MODE 0
MODE 0
HIGH IMPEDANCE
MSB
MSB
Active
Hold
Active
Hold
Active
1296 HoldCond.0
SCK
HOLD#
2015 Microchip Technology Inc.
DS20005045C-page 5
SST25VF080B
4.2
Write Protection
SST25VF080B provides software Write protection. The
Write Protect pin (WP#) enables or disables the lock-
down function of the status register. The Block-Protec-
tion bits (BP3, BP2, BP1, BP0, and BPL) in the status
register provide Write protection to the memory array
and the status register. See
Table 4-3
for the Block-Pro-
tection description.
4.2.1
WRITE PROTECT PIN (WP#)
The Write Protect (WP#) pin enables the lock-down
function of the BPL bit (bit 7) in the status register.
When WP# is driven low, the execution of the Write-
Status-Register (WRSR) instruction is determined by
the value of the BPL bit (see
Table 4-1
). When WP# is
high, the lock-down function of the BPL bit is disabled.
4.3
Status Register
The software status register provides status on
whether the flash memory array is available for any
Read or Write operation, whether the device is Write
enabled, and the state of the Memory Write protection.
During an internal Erase or Program operation, the sta-
tus register may be read only to determine the comple-
tion of an operation in progress.
Table 4-2
describes
the function of each bit in the software status register.
4.3.1
BUSY
The Busy bit determines whether there is an internal
Erase or Program operation in progress. A “1” for the
Busy bit indicates the device is busy with an operation
in progress. A “0” indicates the device is ready for the
next valid operation.
4.3.2
WRITE ENABLE LATCH (WEL)
The Write-Enable-Latch bit indicates the status of the
internal memory Write Enable Latch. If the Write-
Enable-Latch bit is set to “1”, it indicates the device is
Write enabled. If the bit is set to “0” (reset), it indicates
the device is not Write enabled and does not accept
any memory Write (Program/Erase) commands. The
Write-Enable-Latch bit is automatically reset under the
following conditions:
• Power-up
• Write-Disable (WRDI) instruction completion
• Byte-Program instruction completion
• Auto Address Increment (AAI) programming is
completed or reached its highest unprotected
memory address
• Sector-Erase instruction completion
• Block-Erase instruction completion
• Chip-Erase instruction completion
• Write-Status-Register instructions
TABLE 4-1:
CONDITIONS TO EXECUTE WRITE-STATUS-REGISTER (WRSR) INSTRUCTION
WP#
BPL
Execute WRSR Instruction
L
1
Not Allowed
L
0
Allowed
H
X
Allowed
TABLE 4-2:
SOFTWARE STATUS REGISTER
Bit
Name
Function
Default at
Power-up
Read/Write
0
BUSY
1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
0
R
1
WEL
1 = Device is memory Write enabled
0 = Device is not memory Write enabled
0
R
2
BP0
Indicate current level of block write protection (See
Table 4-3
)
1
R/W
3
BP1
Indicate current level of block write protection (See
Table 4-3
)
1
R/W
4
BP2
Indicate current level of block write protection (See
Table 4-3
)
1
R/W
5
BP3
Indicate current level of block write protection (See
Table 4-3
)
0
R/W
6
AAI
Auto Address Increment Programming status
1 = AAI programming mode
0 = Byte-Program mode
0
R
7
BPL
1 = BP3, BP2, BP1, BP0 are read-only bits
0 = BP3, BP2, BP1, BP0 are read/writable
0
R/W
SST25VF080B
DS20005045C-page 6
2015 Microchip Technology Inc.
4.3.3
AUTO ADDRESS INCREMENT (AAI)
The Auto Address Increment Programming-Status bit
provides status on whether the device is in AAI pro-
gramming mode or Byte-Program mode. The default at
power up is Byte-Program mode.
4.3.4
BLOCK PROTECTION (BP3,BP2,
BP1, BP0)
The Block-Protection (BP3, BP2, BP1, BP0) bits define
the size of the memory area, as defined in
Table 4-3
, to
be software protected against any memory Write (Pro-
gram or Erase) operation. The Write-Status-Register
(WRSR) instruction is used to program the BP3, BP2,
BP1 and BP0 bits as long as WP# is high or the Block-
Protect-Lock (BPL) bit is 0. Chip-Erase can only be
executed if Block-Protection bits are all 0. After power-
up, BP3, BP2, BP1 and BP0 are set to 1.
4.3.5
BLOCK PROTECTION LOCK-DOWN
(BPL)
WP# pin driven low (V
IL
), enables the Block-Protection-
Lock-Down (BPL) bit. When BPL is set to 1, it prevents
any further alteration of the BPL, BP3, BP2, BP1, and
BP0 bits. When the WP# pin is driven high (V
IH
), the
BPL bit has no effect and its value is “Don’t Care”. After
power-up, the BPL bit is reset to 0.
TABLE 4-3:
SOFTWARE STATUS REGISTER BLOCK PROTECTION FOR
SST25VF080B
1
1. X = Don’t Care (RESERVED) default is “0
Protection Level
Status Register Bit
2
2. Default at power-up for BP2, BP1, and BP0 is ‘111’. (All Blocks Protected)
Protected Memory Address
BP3
BP2
BP1
BP0
8 Mbit
None
X
0
0
0
None
Upper 1/16
X
0
0
1
F0000H-FFFFFH
Upper 1/8
X
0
1
0
E0000H-FFFFFH
Upper 1/4
X
0
1
1
C0000H-FFFFFH
Upper 1/2
X
1
0
0
80000H-FFFFFH
All Blocks
X
1
0
1
00000H-FFFFFH
All Blocks
X
1
1
0
00000H-FFFFFH
All Blocks
X
1
1
1
00000H-FFFFFH
2015 Microchip Technology Inc.
DS20005045C-page 7
SST25VF080B
4.4
Instructions
Instructions are used to read, write (Erase and Pro-
gram), and configure the SST25VF080B. The instruc-
tion bus cycles are 8 bits each for commands (Op
Code), data, and addresses. Prior to executing any
Byte-Program, Auto Address Increment (AAI) program-
ming, Sector-Erase, Block-Erase, Write-Status-Regis-
ter, or Chip-Erase instructions, the Write-Enable
(WREN) instruction must be executed first. The com-
plete list of instructions is provided in
Table 4-4
. All
instructions are synchronized off a high to low transition
of CE#. Inputs will be accepted on the rising edge of
SCK starting with the most significant bit. CE# must be
driven low before an instruction is entered and must be
driven high after the last bit of the instruction has been
shifted in (except for Read, Read-ID, and Read-Status-
Register instructions). Any low to high transition on
CE#, before receiving the last bit of an instruction bus
cycle, will terminate the instruction in progress and
return the device to standby mode. Instruction com-
mands (Op Code), addresses, and data are all input
from the most significant bit (MSB) first.
TABLE 4-4:
DEVICE OPERATION INSTRUCTIONS
Instruction
Description
Op Code Cycle
1
1. One bus cycle is eight clock periods.
Address
Cycle(s)
2
2. Address bits above the most significant bit of each density can be V
IL
or V
IH
.
Dummy
Cycle(s)
Data
Cycle(s)
Read
Read Memory
0000 0011b (03H)
3
0
1 to
High-Speed Read
Read Memory at higher speed
0000 1011b (0BH)
3
1
1 to
4 KByte Sector-Erase
3
3. 4KByte Sector Erase addresses: use A
MS
-A
12,
remaining addresses are don’t care but must be set either at V
IL
or V
IH.
Erase 4 KByte of
memory array
0010 0000b (20H)
3
0
0
32 KByte Block-Erase
4
4. 32KByte Block Erase addresses: use A
MS
-A
15,
remaining addresses are don’t care but must be set either at V
IL
or V
IH.
Erase 32 KByte block
of memory array
0101 0010b (52H)
3
0
0
64 KByte Block-Erase
5
5. 64KByte Block Erase addresses: use A
MS
-A
16,
remaining addresses are don’t care but must be set either at V
IL
or V
IH.
Erase 64 KByte block
of memory array
1101 1000b (D8H)
3
0
0
Chip-Erase
Erase Full Memory Array
0110 0000b (60H) or
1100 0111b (C7H)
0
0
0
Byte-Program
To Program One Data Byte
0000 0010b (02H)
3
0
1
AAI-Word-Program
6
6. To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by 2 bytes of data
to be programmed. Data Byte 0 will be programmed into the initial address [A
23
-A
1
] with A
0
=0, Data Byte 1 will be pro-
grammed into the
initial address [A
23
-A
1
] with A
0
=1.
Auto Address Increment
Programming
1010 1101b (ADH)
3
0
2 to
RDSR
7
7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
Read-Status-Register
0000 0101b (05H)
0
0
1 to
EWSR
Enable-Write-Status-Register
0101b 0000b (50H)
0
0
0
WRSR
Write-Status-Register
0000 0001b (01H)
0
0
1
WREN
Write-Enable
0000 0110b (06H)
0
0
0
WRDI
Write-Disable
0000 0100b (04H)
0
0
0
RDID
8
8. Manufacturer’s ID is read with A
0
=0, and Device ID is read with A
0
=1. All other address bits are 00H. The Manufacturer’s ID
and device ID output stream is continuous until terminated by a low-to-high transition on CE#.
Read-ID
1001 0000b (90H) or
1010 1011b (ABH)
3
0
1 to
JEDEC-ID
JEDEC ID read
1001 1111b (9FH)
0
0
3 to
EBSY
Enable SO to output RY/BY#
status during AAI programming
0111 0000b (70H)
0
0
0
DBSY
Disable SO as RY/BY#
status during AAI programming
1000 0000b (80H)
0
0
0
SST25VF080B
DS20005045C-page 8
2015 Microchip Technology Inc.
4.4.1
READ (25 MHz)
The Read instruction, 03H, supports up to 25 MHz
Read. The device outputs the data starting from the
specified address location. The data output stream is
continuous through all addresses until terminated by a
low to high transition on CE#. The internal address
pointer will automatically increment until the highest
memory address is reached. Once the highest memory
address is reached, the address pointer will automati-
cally increment to the beginning (wrap-around) of the
address space. Once the data from address location
FFFFFH has been read, the next output will be from
address location 00000H.
The Read instruction is initiated by executing an 8-bit
command, 03H, followed by address bits [A23-A0].
CE# must remain active low for the duration of the
Read cycle. See
Figure 4-3
for the Read sequence.
FIGURE 4-3:
READ SEQUENCE
4.4.2
HIGH-SPEED-READ (66 MHz)
1
The High-Speed-Read instruction, supporting up to
66 MHz Read, is initiated by executing an 8-bit com-
mand, 0BH, followed by address bits [A23-A0] and a
dummy byte. CE# must remain active low for the dura-
tion of the High-Speed-Read cycle. See
Figure 4-4
for
the High-Speed-Read sequence.
Following a dummy cycle, the High-Speed-Read
instruction outputs the data starting from the specified
address location. The data output stream is continuous
through all addresses until terminated by a low to high
transition on CE#. The internal address pointer will
automatically increment until the highest memory
address is reached. Once the highest memory address
is reached, the address pointer will automatically incre-
ment to the beginning (wrap-around) of the address
space. Once the data from address location FFFFFH
has been read, the next output will be from address
location 00000H.
FIGURE 4-4:
HIGH-SPEED-READ SEQUENCE
1296 ReadSeq_0.0
CE#
SO
SI
SCK
ADD.
0 1 2 3 4 5 6 7 8
ADD.
ADD.
03
HIGH IMPEDANCE
15 16
23 24
31 32
39 40
70
47
48
55 56
63 64
N+2
N+3
N+4
N
N+1
D
OUT
MSB
MSB
MSB
MODE 0
MODE 3
D
OUT
D
OUT
D
OUT
D
OUT
1.66 MHz operations occur under the conditions specified in
Table 5-6 on page 19
.
1296 HSRdSeq.0
CE#
SO
SI
SCK
ADD.
0 1 2 3 4 5
6 7 8
ADD.
ADD.
0B
HIGH IMPEDANCE
15 16
23 24
31 32
39 40
47 48
55 56
63 64
N+2
N+3
N+4
N
N+1
X
MSB
MSB
MSB
MODE 0
MODE 3
D
OUT
D
OUT
D
OUT
D
OUT
80
71 72
D
OUT
Note: X = Dummy Byte: 8 Clocks Input Dummy Cycle (V
IL
or V
IH
)
2015 Microchip Technology Inc.
DS20005045C-page 9
SST25VF080B
4.4.3
BYTE-PROGRAM
The Byte-Program instruction programs the bits in the
selected byte to the desired data. The selected byte
must be in the erased state (FFH) when initiating a Pro-
gram operation. A Byte-Program instruction applied to a
protected memory area will be ignored.
Prior to any Write operation, the Write-Enable (WREN)
instruction must be executed. CE# must remain active
low for the duration of the Byte-Program instruction.
The Byte-Program instruction is initiated by executing
an 8-bit command, 02H, followed by address bits [A
23
-
A
0
]. Following the address, the data is input in order
from MSB (bit 7) to LSB (bit 0). CE# must be driven
high before the instruction is executed. The user may
poll the Busy bit in the software status register or wait
T
BP
for the completion of the internal self-timed Byte-
Program operation. See
Figure 4-5
for the Byte-Pro-
gram sequence.
FIGURE 4-5:
BYTE-PROGRAM SEQUENCE
4.4.4
AUTO ADDRESS INCREMENT (AAI)
WORD-PROGRAM
The AAI program instruction allows multiple bytes of
data to be programmed without re-issuing the next
sequential address location. This feature decreases
total programming time when multiple bytes or entire
memory array is to be programmed. An AAI Word pro-
gram instruction pointing to a protected memory area
will be ignored. The selected address range must be in
the erased state (FFH) when initiating an AAI Word
Program operation. While within AAI Word Program-
ming sequence, only the following instructions are
valid: for software end-of-write detection—AAI Word
(ADH), WRDI (04H), and RDSR (05H); for hardware
end-of-write detection—AAI Word (ADH) and WRDI
(04H). There are three options to determine the com-
pletion of each AAI Word program cycle: hardware
detection by reading the Serial Output, software detec-
tion by polling the BUSY bit in the software status reg-
ister, or wait T
BP.
Refer to“End-of-Write Detection” for
details.
Prior to any write operation, the Write-Enable (WREN)
instruction must be executed. Initiate the AAI Word
Program instruction by executing an 8-bit command,
ADH, followed by address bits [A
23
-A
0
]. Following the
addresses, two bytes of data are input sequentially,
each one from MSB (Bit 7) to LSB (Bit 0). The first byte
of data (D0) is programmed into the initial address [A
23
-
A
1
] with A
0
=0, the second byte of Data (D1) is pro-
grammed into the initial address [A
23
-A
1
] with A
0
=1.
CE# must be driven high before executing the AAI
Word Program instruction. Check the BUSY status
before entering the next valid command. Once the
device indicates it is no longer busy, data for the next
two sequential addresses may be programmed, fol-
lowed by the next two, and so on.
When programming the last desired word, or the high-
est unprotected memory address, check the busy sta-
tus using either the hardware or software (RDSR
instruction) method to check for program completion.
Once programming is complete, use the applicable
method to terminate AAI. If the device is in Software
End-of-Write Detection mode, execute the Write-Dis-
able (WRDI) instruction, 04H. If the device is in AAI
Hardware End-of-Write Detection mode, execute the
Write-Disable (WRDI) instruction, 04H, followed by the
8-bit DBSY command, 80H. There is no wrap mode
during AAI programming once the highest unprotected
memory address is reached. See Figures
4-8
and
4-9
for the AAI Word programming sequence.
4.4.5
END-OF-WRITE DETECTION
There are three methods to determine completion of a
program cycle during AAI Word programming: hard-
ware detection by reading the Serial Output, software
detection by polling the BUSY bit in the Software Status
Register, or wait T
BP.
The Hardware End-of-Write
detection method is described in the section below.
1296 ByteProg.0
CE#
SO
SI
SCK
ADD.
0 1 2 3 4 5 6 7 8
ADD.
ADD.
D
IN
02
HIGH IMPEDANCE
15 16
23 24
31 32
39
MODE 0
MODE 3
MSB
MSB
MSB
LSB
SST25VF080B
DS20005045C-page 10
2015 Microchip Technology Inc.
4.4.6
HARDWARE END-OF-WRITE
DETECTION
The Hardware End-of-Write detection method elimi-
nates the overhead of polling the Busy bit in the Soft-
ware Status Register during an AAI Word program
operation. The 8-bit command, 70H, configures the
Serial Output (SO) pin to indicate Flash Busy status
during AAI Word programming. (see
Figure 4-6
) The 8-
bit command, 70H, must be executed prior to initiating
an AAI Word-Program instruction. Once an internal
programming operation begins, asserting CE# will
immediately drive the status of the internal flash status
on the SO pin. A ‘0’ indicates the device is busy and a
‘1’ indicates the device is ready for the next instruction.
De-asserting CE# will return the SO pin to tri-state.
While in AAI and Hardware End-of-Write detection
mode, the only valid instructions are AAI Word (ADH)
and WRDI (04H).
To exit AAI Hardware End-of-Write detection, first exe-
cute WRDI instruction, 04H, to reset the Write-Enable-
Latch bit (WEL=0) and AAI bit. Then execute the 8-bit
DBSY command, 80H, to disable RY/BY# status during
the AAI command. See Figures
4-7
and
4-8
.
FIGURE 4-6:
ENABLE SO AS HARDWARE RY/BY# DURING AAI PROGRAMMING
FIGURE 4-7:
DISABLE SO AS HARDWARE RY/BY# DURING AAI PROGRAMMING
CE#
SO
SI
SCK
0 1 2 3 4 5 6 7
70
HIGH IMPEDANCE
MODE 0
MODE 3
1296 EnableSO.0
MSB
CE#
SO
SI
SCK
0 1 2 3 4 5 6 7
80
HIGH IMPEDANCE
MODE 0
MODE 3
1296 DisableSO.0
MSB