©2014 Silicon Storage Technology, Inc.
DS20005020B
07/14
Data Sheet
www.microchip.com
32 Mbit (x16) Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
Features
• Organized as 2M x16
• Single Voltage Read and Write Operations
– 2.7-3.6V
• Superior Reliability
– Endurance: 100,000 Cycles (Typical)
– Greater than 100 years Data Retention
• Low Power Consumption (typical values at 5 MHz)
– Active Current: 6 mA (typical)
– Standby Current: 4 µA (typical)
– Auto Low Power Mode: 4 µA (typical)
• Hardware Block-Protection/WP# Input Pin
– Top Block-Protection (top two 4-KWord blocks)
for SST39VF3202C
– Bottom Block-Protection (bottom two 4-KWord blocks)
for SST39VF3201C
• Sector-Erase Capability
– Uniform 2 KWord sectors
• Block-Erase Capability
– Flexible block architecture
– Eight 4-KWord blocks, 63 32-KWord blocks
• Chip-Erase Capability
• Erase-Suspend/Erase-Resume Capabilities
• Hardware Reset Pin (RST#)
• Security-ID Feature
– Microchip: 128 bits; User: 128 words
• Fast Read Access Time:
– 70 ns
• Latched Address and Data
• Fast Erase and Word-Program:
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 35 ms (typical)
– Word-Program Time: 7 µs (typical)
• Automatic Write Timing
– Internal V
PP
Generation
• End-of-Write Detection
– Toggle Bits
– Data# Polling
– RY/BY# Pin
• CMOS I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pin Assignments
• Packages Available
– 48-lead TSOP (12mm x 20mm)
– 48-ball TFBGA (6mm x 8mm)
• All devices are RoHS compliant
The SST39VF3201C and SST39VF3202C devices are 2M x16, CMOS Multi-Pur-
pose Flash Plus (MPF+) manufactured with proprietary, high performance CMOS
SuperFlash technology. The split-gate cell design and thick-oxide tunneling injec-
tor attain better reliability and manufacturability compared with alternate
approaches. The SST39VF3201C and SST39VF3202C write (Program or Erase)
with a 2.7-3.6V power supply. This device conforms to JEDEC standard pinouts
for x16 memories.
©2014 Silicon Storage Technology, Inc.
DS20005020B
07/14
2
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
Data Sheet
Product Description
The SST39VF3201C and SST39VF3202C devices are 2M x16 CMOS Multi-Purpose Flash Plus
(MPF+) manufactured with proprietary, high-performance CMOS SuperFlash technology. The split-
gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability com-
pared with alternate approaches. The SST39VF3201C/3202C write (Program or Erase) with a 2.7-
3.6V power supply. These devices conform to JEDEC standard pin assignments for x16 memories.
Featuring high performance Word-Program, the SST39VF3201C/3202C devices provide a typical
Word-Program time of 7 µsec. These devices use Toggle Bit, Data# Polling, or RY/BY# pin to indicate
the completion of Program operation. To protect against inadvertent write, they have on-chip hardware
and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of
applications, these devices are offered with a guaranteed typical endurance of 100,000 cycles. Data
retention is rated at greater than 100 years.
The SST39VF3201C/3202C devices are suited for applications that require convenient and economical
updating of program, configuration, or data memory. For all system applications, they significantly
improve performance and reliability, while lowering power consumption. They inherently use less
energy during Erase and Program than alternative flash technologies. The total energy consumed is a
function of the applied voltage, current, and time of application. Since for any given voltage range, the
SuperFlash technology uses less current to program and has a shorter erase time, the total energy
consumed during any Erase or Program operation is less than alternative flash technologies. These
devices also improve flexibility while lowering the cost for program, data, and configuration storage
applications.
The SuperFlash technology provides fixed Erase and Program times, independent of the number of
Erase/Program cycles that have occurred. Therefore the system software or hardware does not have
to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Pro-
gram times increase with accumulated Erase/Program cycles.
To meet high-density, surface mount requirements, the SST39VF3201C/3202C devices are offered in
48-lead TSOP and 48-ball TFBGA packages. See Figure 2 and Figure 3 for pin assignments.
©2014 Silicon Storage Technology, Inc.
DS20005020B
07/14
3
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
Data Sheet
Block Diagram
Figure 1: Functional Block Diagram
Y-Decoder
I/O Buffers and Data Latches
1410 B1.0
Address Buffer Latches
X-Decoder
DQ15 - DQ0
Memory Address
OE#
CE#
WE#
SuperFlash
Memory
Control Logic
WP#
RESET#
RY/BY#
©2014 Silicon Storage Technology, Inc.
DS20005020B
07/14
4
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
Data Sheet
Pin Assignments
Figure 2: Pin Assignments for 48-lead TSOP
Figure 3: Pin assignments for 48-ball TFBGA
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RST#
NC
WP#
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1410 48-tsop EK P1.0
Standard Pinout
Top View
Die Up
1410 4-tfbga B1K P2.0
A B C D E F G H
6
5
4
3
2
1
TOP VIEW (balls facing down)
A13
A9
WE#
RY/BY#
A7
A3
A12
A8
RST#
WP#
A17
A4
A14
A10
NC
A18
A6
A2
A15
A11
A19
A20
A5
A1
A16
DQ7
DQ5
DQ2
DQ0
A0
NC
DQ14
DQ12
DQ10
DQ8
CE#
DQ15
DQ13
VDD
DQ11
DQ9
OE#
VSS
DQ6
DQ4
DQ3
DQ1
VSS
©2014 Silicon Storage Technology, Inc.
DS20005020B
07/14
5
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
Data Sheet
Table 1: Pin Description
Symbol
Pin Name
Functions
A
MS
1
-A
0
1. A
MS
= Most significant address
A
MS
= A
20
for SST39VF3201C/3202C
Address Inputs
To provide memory addresses.
During Sector-Erase A
MS
-A
11
address lines will select the sector.
During Block-Erase A
MS
-A
15
address lines will select the block.
DQ
15
-DQ
0
Data Input/output To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
WP#
Write Protect
To protect the top/bottom boot block from Erase/Program operation when
grounded.
RST#
Reset
To reset and return the device to Read mode.
CE#
Chip Enable
To activate the device when CE# is low.
OE#
Output Enable
To gate the data output buffers.
WE#
Write Enable
To control the Write operations.
V
DD
Power Supply
To provide power supply voltage: 2.7-3.6V
V
SS
Ground
NC
No Connection
Unconnected pins.
RY/BY#
Ready/Busy#
To output the status of a Program or Erase operation
RY/BY# is a open drain output, so a 10K
- 100K pull-up resistor is required
to allow RY/BY# to transition high indicating the device is ready to read.
T1.0 20005020
©2014 Silicon Storage Technology, Inc.
DS20005020B
07/14
6
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
Data Sheet
Table 2: Top / Bottom Boot Block Address (1 of 2)
Top Boot Block Address SST39VF3202C
Bottom Boot Block Address SST39VF3201C
#
Size
(KWord)
Address Range
#
Size
(KWord)
Address Range
70
4
1FF000H-1FFFFFH
70
32
1F8000H-1FFFFFH
69
4
1FE000H-1FEFFFH
69
32
1F0000H-1F7FFFH
68
4
1FD000H-1FDFFFH
68
32
1E8000H-1EFFFFH
67
4
1FC000H-1FCFFFH
67
32
1E0000H-1E7FFFH
66
4
1FB000H-1FBFFFH
66
32
1D8000H-1DFFFFH
65
4
1FA000H-1FAFFFH
65
32
1D0000H-1D7FFFH
64
4
1F9000H-1F9FFFH
64
32
1C8000H-1CFFFFH
63
4
1F8000H-1F8FFFH
63
32
1C0000H-1C7FFFH
62
32
1F0000H-1F7FFFH
62
32
1B8000H-1BFFFFH
61
32
1E8000H-1EFFFFH
61
32
1B0000H-1B7FFFH
60
32
1E0000H-1E7FFFH
60
32
1A8000H-1AFFFFH
59
32
1D8000H-1DFFFFH
59
32
1A0000H-1A7FFFH
58
32
1D0000H-1D7FFFH
58
32
198000H-19FFFFH
57
32
1C8000H-1CFFFFH
57
32
190000H-197FFFH
56
32
1C0000H-1C7FFFH
56
32
188000H-18FFFFH
55
32
1B8000H-1BFFFFH
55
32
180000H-187FFFH
54
32
1B0000H-1B7FFFH
54
32
178000H-17FFFFH
53
32
1A8000H-1AFFFFH
53
32
170000H-177FFFH
52
32
1A0000H-1A7FFFH
52
32
168000H-16FFFFH
51
32
198000H-19FFFFH
51
32
160000H-167FFFH
50
32
190000H-197FFFH
50
32
158000H-15FFFFH
49
32
188000H-18FFFFH
49
32
150000H-157FFFH
48
32
180000H-187FFFH
48
32
148000H-14FFFFH
47
32
178000H-17FFFFH
47
32
140000H-147FFFH
46
32
170000H-177FFFH
46
32
138000H-13FFFFH
45
32
168000H-16FFFFH
45
32
130000H-137FFFH
44
32
160000H-167FFFH
44
32
128000H-12FFFFH
43
32
158000H-15FFFFH
43
32
120000H-127FFFH
42
32
150000H-157FFFH
42
32
118000H-11FFFFH
41
32
148000H-14FFFFH
41
32
110000H-117FFFH
40
32
140000H-147FFFH
40
32
108000H-10FFFFH
39
32
138000H-13FFFFH
39
32
100000H-107FFFH
38
32
130000H-137FFFH
38
32
0F8000H-0FFFFFH
37
32
128000H-12FFFFH
37
32
0F0000H-0F7FFFH
36
32
120000H-127FFFH
36
32
0E8000H-0EFFFFH
35
32
118000H-11FFFFH
35
32
0E0000H-0E7FFFH
34
32
110000H-117FFFH
34
32
0D8000H-0DFFFFH
33
32
108000H-10FFFFH
33
32
0D0000H-0D7FFFH
32
32
100000H-107FFFH
32
32
0C8000H-0CFFFFH
31
32
0F8000H-0FFFFFH
31
32
0C0000H-0C7FFFH
©2014 Silicon Storage Technology, Inc.
DS20005020B
07/14
7
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
Data Sheet
30
32
0F0000H-0F7FFFH
30
32
0B8000H-0BFFFFH
29
32
0E8000H-0EFFFFH
29
32
0B0000H-0B7FFFH
28
32
0E0000H-0E7FFFH
28
32
0A8000H-0AFFFFH
27
32
0D8000H-0DFFFFH
27
32
0A0000H-0A7FFFH
26
32
0D0000H-0D7FFFH
26
32
098000H-09FFFFH
25
32
0C8000H-0CFFFFH
25
32
090000H-097FFFH
24
32
0C0000H-0C7FFFH
24
32
088000H-08FFFFH
23
32
0B8000H-0BFFFFH
23
32
080000H-087FFFH
22
32
0B0000H-0B7FFFH
22
32
078000H-07FFFFH
21
32
0A8000H-0AFFFFH
21
32
070000H-077FFFH
20
32
0A0000H-0A7FFFH
20
32
068000H-06FFFFH
19
32
098000H-09FFFFH
19
32
060000H-067FFFH
18
32
090000H-097FFFH
18
32
058000H-05FFFFH
17
32
088000H-08FFFFH
17
32
050000H-057FFFH
16
32
080000H-087FFFH
16
32
048000H-04FFFFH
15
32
078000H-07FFFFH
15
32
040000H-047FFFH
14
32
070000H-077FFFH
14
32
038000H-03FFFFH
13
32
068000H-06FFFFH
13
32
030000H-037FFFH
12
32
060000H-067FFFH
12
32
028000H-02FFFFH
11
32
058000H-05FFFFH
11
32
020000H-027FFFH
10
32
050000H-057FFFH
10
32
018000H-01FFFFH
9
32
048000H-04FFFFH
9
32
010000H-017FFFH
8
32
040000H-047FFFH
8
32
008000H-00FFFFH
7
32
038000H-03FFFFH
7
4
007000H-007FFFH
6
32
030000H-037FFFH
6
4
006000H-006FFFH
5
32
028000H-02FFFFH
5
4
005000H-005FFFH
4
32
020000H-027FFFH
4
4
004000H-004FFFH
3
32
018000H-01FFFFH
3
4
003000H-003FFFH
2
32
010000H-017FFFH
2
4
002000H-002FFFH
1
32
008000H-00FFFFH
1
4
001000H-001FFFH
0
32
000000H-007FFFH
0
4
000000H-000FFFH
T2.20005020
Table 2: Top / Bottom Boot Block Address (Continued) (2 of 2)
©2014 Silicon Storage Technology, Inc.
DS20005020B
07/14
8
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
Data Sheet
Device Operation
Commands are used to initiate the memory operation functions of the device. Commands are written
to the device using standard microprocessor write sequences. A command is written by asserting WE#
low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever
occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.
The SST39VF3201C/3202C also have the Auto Low Power mode which puts the device in a near
standby mode after data has been accessed with a valid Read operation. This reduces the I
DD
active
read current from typically 9 mA to typically 4 µA. The Auto Low Power mode reduces the typical I
DD
active read current to the range of 2 mA/MHz of Read cycle time. The device exits the Auto Low Power
mode with any address transition or control signal transition used to initiate another Read cycle, with
no access time penalty. Note that the device does not enter Auto-Low Power mode after power-up with
CE# held steadily low, until the first address transition or CE# is driven high.
Read
The Read operation of the SST39VF3201C/3202C is controlled by CE# and OE#, both have to be low
for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the
chip is deselected and only standby power is consumed. OE# is the output control and is used to gate
data from the output pins. The data bus is in high impedance state when either CE# or OE# is high.
Refer to the Read cycle timing diagram for further details (Figure 5).
Word-Program Operation
The SST39VF3201C/3202C are programmed on a word-by-word basis. Before programming, the sector
where the word exists must be fully erased. The Program operation is accomplished in three steps.
The first step is the three-byte load sequence for Software Data Protection. The second step is to load
word address and word data. During the Word-Program operation, the addresses are latched on the
falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of
either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is ini-
tiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation,
once initiated, will be completed within 10 µs. See Figure 6 and Figure 7 for WE# and CE# controlled
Program operation timing diagrams and Figure 21 for flowcharts. During the Program operation, the
only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is
free to perform additional tasks. Any commands issued during the internal Program operation are
ignored. During the command sequence, WP# should be statically held high or low.
Sector/Block-Erase Operation
The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or
block-by-block) basis. The SST39VF3201C/3202C offer both Sector-Erase and Block-Erase mode. The
sector architecture is based on uniform sector size of 2 KWord. The Block-Erase mode is based on
block sizes of 4 and 32 KWord. The Sector-Erase operation is initiated by executing a six-byte com-
mand sequence with Sector-Erase command (50H) and sector address (SA) in the last bus cycle. The
Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase com-
mand (30H) and block address (BA) in the last bus cycle. The sector or block address is latched on the
falling edge of the sixth WE# pulse, while the command (50H or 30H) is latched on the rising edge of
the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase
operation can be determined using either Data# Polling or Toggle Bit methods. See Figure 11 and Fig-
ure 12 for timing waveforms and Figure 25 for the flowchart. Any commands issued during the Sector-
©2014 Silicon Storage Technology, Inc.
DS20005020B
07/14
9
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
Data Sheet
or Block-Erase operation are ignored. When WP# is low, any attempt to Sector- (Block-) Erase the pro-
tected block will be ignored. During the command sequence, WP# should be statically held high or low.
Erase-Suspend/Erase-Resume Commands
The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing
data to be read from any memory location, or program data into any sector/block that is not suspended
for an Erase operation. The operation is executed by issuing one byte command sequence with Erase-
Suspend command (B0H). The device automatically enters read mode typically within 10 µs after the
Erase-Suspend command had been issued. Valid data can be read from any sector or block that is not
suspended from an Erase operation. Reading at address location within erase-suspended sectors/
blocks will output DQ
2
toggling and DQ
6
at ‘1’. While in Erase-Suspend mode, a Word-Program opera-
tion is allowed except for the sector or block selected for Erase-Suspend.
To resume Sector-Erase or Block-Erase operation which has been suspended the system must issue
Erase Resume command. The operation is executed by issuing one byte command sequence with
Erase Resume command (30H) at any address in the last Byte sequence.
Chip-Erase Operation
The SST39VF3201C/3202C provide a Chip-Erase operation, which allows the user to erase the entire
memory array to the “1” state. This is useful when the entire device must be quickly erased.
The Chip-Erase operation is initiated by executing a six-byte command sequence with Chip-Erase
command (10H) at address 555H in the last byte sequence. The Erase operation begins with the rising
edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is
Toggle Bit or Data# Polling. See Table 7 for the command sequence, Figure 10 for timing diagram, and
Figure 25 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. When
WP# is low, any attempt to Chip-Erase will be ignored. During the command sequence, WP# should
be statically held high or low.
Write Operation Status Detection
The SST39VF3201C/3202C provide two software means to detect the completion of a Write (Program
or Erase) cycle, in order to optimize the system write cycle time. The software detection includes two
status bits: Data# Polling (DQ
7
) and Toggle Bit (DQ
6
). The End-of-Write detection mode is enabled
after the rising edge of WE#, which initiates the internal Program or Erase operation.
The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a
Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this
occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with
either DQ
7
or DQ
6
. In order to prevent spurious rejection, if an erroneous result occurs, the software
routine should include a loop to read the accessed location an additional two (2) times. If both reads
are valid, then the device has completed the Write cycle, otherwise the rejection is valid.
©2014 Silicon Storage Technology, Inc.
DS20005020B
07/14
10
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
Data Sheet
Data# Polling (DQ
7
)
When the SST39VF3201C/3202C are in the internal Program operation, any attempt to read DQ
7
will
produce the complement of the true data. Once the Program operation is completed, DQ
7
will produce
true data. Note that even though DQ
7
may have valid data immediately following the completion of an internal
Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in
subsequent successive Read cycles after an interval of 1 µs. During internal Erase operation, any attempt
to read DQ
7
will produce a ‘0’. Once the internal Erase operation is completed, DQ
7
will produce a ‘1’.
The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For
Sector-, Block- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#)
pulse. See Figure 8 for Data# Polling timing diagram and Figure 22 for a flowchart.
Toggle Bits (DQ6 and DQ2)
During the internal Program or Erase operation, any consecutive attempts to read DQ
6
will produce
alternating “1”s and “0”s, i.e., toggling between 1 and 0. When the internal Program or Erase operation
is completed, the DQ
6
bit will stop toggling. The device is then ready for the next operation. For Sector-
, Block-, or Chip-Erase, the toggle bit (DQ
6
) is valid after the rising edge of sixth WE# (or CE#) pulse.
DQ
6
will be set to ‘1’ if a Read operation is attempted on an Erase-Suspended Sector/Block. If Pro-
gram operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ
6
will toggle.
An additional Toggle Bit is available on DQ
2
, which can be used in conjunction with DQ
6
to check
whether a particular sector is being actively erased or erase-suspended. Table 3 shows detailed status
bits information. The Toggle Bit (DQ
2
) is valid after the rising edge of the last WE# (or CE#) pulse of
Write operation. See Figure 9 for Toggle Bit timing diagram and Figure 22 for a flowchart.
Note: DQ
7
, DQ
6
and DQ
2
require a valid address when reading status information.
Table 3: Write Operation Status
Status
DQ
7
DQ
6
DQ
2
RY/BY#
Normal Operation
Standard Program
DQ
7
#
Toggle
No
Toggle
0
Standard Erase
0
Toggle
Toggle
0
Erase-Suspend
Mode
Read from Erase-Sus-
pended Sector/Block
1
1
Toggle
1
Read from Non- Erase-
Suspended Sector/Block
Data
Data
Data
1
Program
DQ
7
#
Toggle
N/A
0
T3.0 20005020