© 2008 Microchip Technology Inc.
DS21298E-page 1
MCP3204/3208
Features
• 12-bit resolution
• ± 1 LSB max DNL
• ± 1 LSB max INL (MCP3204/3208-B)
• ± 2 LSB max INL (MCP3204/3208-C)
• 4 (MCP3204) or 8 (MCP3208) input channels
• Analog inputs programmable as single-ended or
pseudo-differential pairs
• On-chip sample and hold
• SPI serial interface (modes 0,0 and 1,1)
• Single supply operation: 2.7V - 5.5V
• 100 ksps max. sampling rate at V
DD
= 5V
• 50 ksps max. sampling rate at V
DD
= 2.7V
• Low power CMOS technology:
- 500 nA typical standby current, 2 µA max.
- 400 µA max. active current at 5V
• Industrial temp range: -40°C to +85°C
• Available in PDIP, SOIC and TSSOP packages
Applications
• Sensor Interface
• Process Control
• Data Acquisition
• Battery Operated Systems
Functional Block Diagram
Description
The Microchip Technology Inc. MCP3204/3208
devices are successive approximation 12-bit Analog-
to-Digital (A/D) Converters with on-board sample and
hold circuitry. The MCP3204 is programmable to
provide two pseudo-differential input pairs or four
single-ended inputs. The MCP3208 is programmable
to provide four pseudo-differential input pairs or eight
single-ended inputs. Differential Nonlinearity (DNL) is
specified at ±1 LSB, while Integral Nonlinearity (INL) is
offered in ±1 LSB (MCP3204/3208-B) and ±2 LSB
(MCP3204/3208-C) versions.
Communication with the devices is accomplished using
a simple serial interface compatible with the SPI
protocol. The devices are capable of conversion rates
of up to 100 ksps. The MCP3204/3208 devices operate
over a broad voltage range (2.7V - 5.5V). Low current
design permits operation with typical standby and
active currents of only 500 nA and 320 µA,
respectively. The MCP3204 is offered in 14-pin PDIP,
150 mil SOIC and TSSOP packages. The MCP3208 is
offered in 16-pin PDIP and SOIC packages.
Package Types
Comparator
Sample
and
Hold
12-Bit SAR
DAC
Control Logic
CS/SHDN
V
REF
V
SS
V
DD
CLK
D
OUT
Shift
Register
CH0
Channel
Mux
Input
CH1
CH7*
* Note:
Channels 5-7 available on MCP3208 Only
D
IN
V
DD
CLK
D
OUT
MCP3204
1
2
3
4
14
13
12
11
10
9
8
5
6
7
V
REF
D
IN
CH0
CH1
CH2
CH3
CS/SHDN
DGND
AGND
NC
V
DD
CLK
D
OUT
MC
P3
208
1
2
3
4
16
15
14
13
12
11
10
9
5
6
7
8
V
REF
D
IN
CS/SHDN
DGND
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
NC
AGND
PDIP, SOIC, TSSOP
PDIP, SOIC
2.7V 4-Channel/8-Channel 12-Bit A/D Converters
with SPI Serial Interface
MCP3204/3208
DS21298E-page 2
© 2008 Microchip Technology Inc.
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings†
V
DD
...................................................................................7.0V
All inputs and outputs w.r.t. V
SS
............... -0.6V to V
DD
+0.6V
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-65°C to +125°C
Soldering temperature of leads (10 seconds) .............+300°C
ESD protection on all pins.............................................> 4 kV
†Notice:
Stresses above those listed under "Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect
device reliability.
ELECTRICAL SPECIFICATIONS
Electrical Characteristics:
Unless otherwise noted, all parameters apply at V
DD
= 5V, V
SS
= 0V, V
REF
= 5V,
T
A
= -40°C to +85°C,f
SAMPLE
= 100 ksps and f
CLK
= 20*f
SAMPLE
Parameters
Sym
Min
Typ
Max
Units
Conditions
Conversion Rate
Conversion Time
t
CONV
—
—
12
clock
cycles
Analog Input Sample Time
t
SAMPLE
1.5
clock
cycles
Throughput Rate
f
SAMPLE
—
—
—
—
100
50
ksps
ksps
V
DD
= V
REF
= 5V
V
DD
= V
REF
= 2.7V
DC Accuracy
Resolution
12
bits
Integral Nonlinearity
INL
—
—
±0.75
±1.0
±1
±2
LSB
MCP3204/3208-B
MCP3204/3208-C
Differential Nonlinearity
DNL
—
±0.5
±1
LSB
No missing codes
over-temperature
Offset Error
—
±1.25
±3
LSB
Gain Error
—
±1.25
±5
LSB
Dynamic Performance
Total Harmonic Distortion
—
-82
—
dB
V
IN
= 0.1V to 4.9V@1 kHz
Signal to Noise and Distortion
(SINAD)
—
72
—
dB
V
IN
= 0.1V to 4.9V@1 kHz
Spurious Free Dynamic
Range
—
86
—
dB
V
IN
= 0.1V to 4.9V@1 kHz
Reference Input
Voltage Range
0.25
—
V
DD
V
Note 2
Current Drain
—
—
100
0.001
150
3.0
µA
µA
CS = V
DD
= 5V
Analog Inputs
Input Voltage Range for CH0-
CH7 in Single-Ended Mode
V
SS
—
V
REF
V
Input Voltage Range for IN+ in
pseudo-differential Mode
IN-
—
V
REF
+IN-
Note 1:
This parameter is established by characterization and not 100% tested.
2:
See graphs that relate linearity performance to V
REF
levels.
3:
Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity
performance, particularly at elevated temperatures. See Section 6.2 “Maintaining Minimum Clock
Speed”
, “Maintaining Minimum Clock Speed”, for more information.
© 2008 Microchip Technology Inc.
DS21298E-page 3
MCP3204/3208
Input Voltage Range for IN- in
pseudo-differential Mode
V
SS
-100
—
V
SS
+100
mV
Leakage Current
—
0.001
±1
µA
Switch Resistance
—
1000
—
Ω
See
Figure 4-1
Sample Capacitor
—
20
—
pF
See
Figure 4-1
Digital Input/Output
Data Coding Format
Straight Binary
High Level Input Voltage
V
IH
0.7 V
DD
—
—
V
Low Level Input Voltage
V
IL
—
—
0.3 V
DD
V
High Level Output Voltage
V
OH
4.1
—
—
V
I
OH
= -1 mA, V
DD
= 4.5V
Low Level Output Voltage
V
OL
—
—
0.4
V
I
OL
= 1 mA, V
DD
= 4.5V
Input Leakage Current
I
LI
-10
—
10
µA
V
IN
= V
SS
or V
DD
Output Leakage Current
I
LO
-10
—
10
µA
V
OUT
= V
SS
or V
DD
Pin Capacitance
(All Inputs/Outputs)
C
IN
,C
OUT
—
—
10
pF
V
DD
= 5.0V (Note 1)
T
A
= 25°C, f = 1 MHz
Timing Parameters
Clock Frequency
f
CLK
—
—
—
—
2.0
1.0
MHz
MHz
V
DD
= 5V (Note 3)
V
DD
= 2.7V (Note 3)
Clock High Time
t
HI
250
—
—
ns
Clock Low Time
t
LO
250
—
—
ns
CS Fall To First Rising CLK
Edge
t
SUCS
100
—
—
ns
Data Input Setup Time
t
SU
50
—
—
ns
Data Input Hold Time
t
HD
50
—
—
ns
CLK Fall To Output Data Valid
t
DO
—
—
200
ns
See Figures 1-2 and 1-3
CLK Fall To Output Enable
t
EN
—
—
200
ns
See Figures 1-2 and 1-3
CS Rise To Output Disable
t
DIS
—
—
100
ns
See Figures 1-2 and 1-3
CS Disable Time
t
CSH
500
—
—
ns
D
OUT
Rise Time
t
R
—
—
100
ns
See Figures 1-2 and 1-3 (Note 1)
D
OUT
Fall Time
t
F
—
—
100
ns
See Figures 1-2 and 1-3 (Note 1)
Power Requirements
Operating Voltage
V
DD
2.7
—
5.5
V
Operating Current
I
DD
—
—
320
225
400
—
µA
V
DD
=V
REF
= 5V, D
OUT
unloaded
V
DD
=V
REF
= 2.7V, D
OUT
unloaded
Standby Current
I
DDS
—
0.5
2.0
µA
CS = V
DD
= 5.0V
ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics:
Unless otherwise noted, all parameters apply at V
DD
= 5V, V
SS
= 0V, V
REF
= 5V,
T
A
= -40°C to +85°C,f
SAMPLE
= 100 ksps and f
CLK
= 20*f
SAMPLE
Parameters
Sym
Min
Typ
Max
Units
Conditions
Note 1:
This parameter is established by characterization and not 100% tested.
2:
See graphs that relate linearity performance to V
REF
levels.
3:
Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity
performance, particularly at elevated temperatures. See Section 6.2 “Maintaining Minimum Clock
Speed”
, “Maintaining Minimum Clock Speed”, for more information.
MCP3204/3208
DS21298E-page 4
© 2008 Microchip Technology Inc.
TEMPERATURE CHARACTERISTICS
FIGURE 1-1:
Serial Interface Timing.
Electrical Specifications:
Unless otherwise indicated, V
DD
= 5V, V
SS
= 0V, V
REF
= 5V
Parameters
Sym
Min
Typ
Max
Units
Conditions
Temperature Ranges
Specified Temperature Range
T
A
-40
—
+125
°C
Operating Temperature Range
T
A
-40
—
+125
°C
Storage Temperature Range
T
A
-65
—
+150
°C
Thermal Package Resistances
Thermal Resistance, 14L-PDIP
θ
JA
—
70
—
°C/W
Thermal Resistance, 14L-SOIC
θ
JA
—
95.3
—
°C/W
Thermal Resistance, 14L-TSSOP
θ
JA
—
100
—
°C/W
Thermal Resistance, 16L-PDIP
θ
JA
—
70
—
°C/W
Thermal Resistance, 16L-SOIC
θ
JA
—
86.1
—
°C/W
CS
CLK
D
IN
MSB IN
t
SU
t
HD
t
SUCS
t
CSH
t
HI
t
LO
D
OUT
t
EN
t
DO
t
R
t
F
LSB
MSB OUT
t
DIS
Null Bit
© 2008 Microchip Technology Inc.
DS21298E-page 5
MCP3204/3208
FIGURE 1-2:
Load Circuit for t
R
, t
F
, t
DO
.
FIGURE 1-3:
Load circuit for t
DIS
and t
EN
.
Test Point
1.4V
D
OUT
3 kΩ
C
L
= 100 pF
D
OUT
t
R
Voltage Waveforms for t
R
, t
F
CLK
D
OUT
t
DO
Voltage Waveforms for t
DO
t
F
V
OH
V
OL
90%
10%
*
Waveform 1 is for an output with internal
conditions such that the output is high,
unless disabled by the output control.
†
Waveform 2 is for an output with internal
conditions such that the output is low,
unless disabled by the output control.
Test Point
D
OUT
3 kΩ
100 pF
t
DIS
Waveform 2
t
DIS
Waveform 1
CS
CLK
D
OUT
t
EN
1
2
B11
Voltage Waveforms for t
EN
t
EN
Waveform
V
DD
V
DD
/2
V
SS
3
4
Voltage Waveforms for t
DIS
D
OUT
D
OUT
CS
V
IH
T
DIS
Waveform 1*
Waveform 2†
MCP3204/3208
DS21298E-page 6
© 2008 Microchip Technology Inc.
NOTES:
© 2008 Microchip Technology Inc.
DS21298E-page 7
MCP3204/3208
2.0
TYPICAL PERFORMANCE CHARACTERISTICS
Note:
Unless otherwise indicated, V
DD
= V
REF
= 5V, V
SS
= 0V, f
SAMPLE
= 100 ksps, f
CLK
= 20* f
SAMPLE
, T
A
= +25°C.
FIGURE 2-1:
Integral Nonlinearity (INL)
vs. Sample Rate.
FIGURE 2-2:
Integral Nonlinearity (INL)
vs. V
REF
.
FIGURE 2-3:
Integral Nonlinearity (INL)
vs. Code (Representative Part).
FIGURE 2-4:
Integral Nonlinearity (INL)
vs. Sample Rate (V
DD
= 2.7V).
FIGURE 2-5:
Integral Nonlinearity (INL)
vs. V
REF
(V
DD
= 2.7V).
FIGURE 2-6:
Integral Nonlinearity (INL)
vs. Code (Representative Part, V
DD
= 2.7V).
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
0
25
50
75
100
125
150
Sample Rate (ksps)
INL (LSB)
Positive INL
Negative INL
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
0
1
2
3
4
5
V
REF
(V)
IN
L (
L
S
B
)
Positive INL
Negative INL
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
0
512
1024
1536
2048
2560
3072
3584
4096
Digital Code
INL (LSB)
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
0
10
20
30
40
50
60
70
80
Sample Rate (ksps)
INL (LS
B
)
Positive INL
Negative INL
V
DD
= V
REF
= 2.7 V
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
V
REF
(V)
IN
L (
L
S
B
)
Positive INL
Negative INL
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
0
512
1024
1536
2048
2560
3072
3584
4096
Digital Code
IN
L
(
L
SB)
V
DD
= V
REF
= 2.7 V
F
SAMPLE
= 50 ksps
MCP3204/3208
DS21298E-page 8
© 2008 Microchip Technology Inc.
Note:
Unless otherwise indicated, V
DD
= V
REF
= 5 V, V
SS
= 0 V, f
SAMPLE
= 100 ksps, f
CLK
= 20* f
SAMPLE
, T
A
= +25°C.
FIGURE 2-7:
Integral Nonlinearity (INL)
vs. Temperature.
FIGURE 2-8:
Differential Nonlinearity
(DNL) vs. Sample Rate.
FIGURE 2-9:
Differential Nonlinearity
(DNL) vs. V
REF
.
FIGURE 2-10:
Integral Nonlinearity (INL)
vs. Temperature (V
DD
= 2.7V).
FIGURE 2-11:
Differential Nonlinearity
(DNL) vs. Sample Rate (V
DD
= 2.7V).
FIGURE 2-12:
Differential Nonlinearity
(DNL) vs. V
REF
(V
DD
= 2.7V)
.
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
-50
-25
0
25
50
75
100
Temperature (°C)
INL
(L
S
B
)
Positive INL
Negative INL
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
0
25
50
75
100
125
150
Sample Rate (ksps)
DNL (LSB)
Positive DNL
Negative DNL
-3.0
-2.0
-1.0
0.0
1.0
2.0
3.0
0
1
2
3
4
5
V
REF
(V)
DN
L (
L
S
B
)
Positive DNL
Negative DNL
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
-50
-25
0
25
50
75
100
Temperature (°C)
INL (LS
B
)
Positive INL
V
DD
= V
REF
= 2.7 V
F
SAMPLE
= 50 ksps
Negative INL
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
0
10
20
30
40
50
60
70
80
Sample Rate (ksps)
DN
L (LSB)
Positive DNL
Negative DNL
V
DD
= V
REF
= 2.7 V
-3.0
-2.0
-1.0
0.0
1.0
2.0
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
V
REF
(V)
DN
L (
L
S
B
)
V
DD
= V
REF
= 2.7 V
F
SAMPLE
= 50 ksps
Positive DNL
Negative DNL
© 2008 Microchip Technology Inc.
DS21298E-page 9
MCP3204/3208
Note:
Unless otherwise indicated, V
DD
= V
REF
= 5V, V
SS
= 0V, f
SAMPLE
= 100 ksps, f
CLK
= 20* f
SAMPLE
, T
A
= +25°C.
FIGURE 2-13:
Differential Nonlinearity
(DNL) vs. Code (Representative Part).
FIGURE 2-14:
Differential Nonlinearity
(DNL) vs. Temperature.
FIGURE 2-15:
Gain Error vs. V
REF
.
FIGURE 2-16:
Differential Nonlinearity
(DNL) vs. Code (Representative Part,
V
DD
= 2.7V).
FIGURE 2-17:
Differential Nonlinearity
(DNL) vs. Temperature (V
DD
= 2.7V).
FIGURE 2-18:
Offset Error vs. V
REF
.
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
0
512
1024
1536
2048
2560
3072
3584
4096
Digital Code
DNL (LSB)
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
-50
-25
0
25
50
75
100
Temperature (°C)
DN
L (
L
SB)
Positive DNL
Negative DNL
-4
-3
-2
-1
0
1
2
3
4
0
1
2
3
4
5
V
REF
(V)
Ga
in Error
(LSB)
V
DD
= V
REF
= 2.7 V
F
SAMPLE
= 50 ksps
V
DD
= V
REF
= 5 V
F
SAMPLE
= 100 ksps
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
0
512
1024
1536
2048
2560
3072
3584
4096
Digital Code
DNL (LSB)
V
DD
= V
REF
= 2.7 V
F
SAMPLE
= 50 ksps
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
-50
-25
0
25
50
75
100
Temperature (°C)
DN
L
(
L
S
B
)
Positive DNL
V
DD
= V
REF
= 2.7 V
F
SAMPLE
= 50 ksps
Negative DNL
0
2
4
6
8
10
12
14
16
18
20
0
1
2
3
4
5
V
REF
(V)
Offse
t Error (LSB)
V
DD
= V
REF
= 2.7V
F
SAMPLE
= 50 ksps
V
DD
= V
REF
= 5V
F
SAMPLE
= 100 ksps
MCP3204/3208
DS21298E-page 10
© 2008 Microchip Technology Inc.
Note:
Unless otherwise indicated, V
DD
= V
REF
= 5V, V
SS
= 0V, f
SAMPLE
= 100 ksps, f
CLK
= 20* f
SAMPLE
, T
A
= +25°C.
FIGURE 2-19:
Gain Error vs. Temperature.
FIGURE 2-20:
Signal-to-Noise (SNR) vs.
Input Frequency.
FIGURE 2-21:
Total Harmonic Distortion
(THD) vs. Input Frequency.
FIGURE 2-22:
Offset Error vs.
Temperature.
FIGURE 2-23:
Signal-to-Noise and
Distortion (SINAD) vs. Input Frequency.
FIGURE 2-24:
Signal-to-Noise and
Distortion (SINAD) vs. Input Signal Level.
-1.8
-1.6
-1.4
-1.2
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
-50
-25
0
25
50
75
100
Temperature (°C)
Ga
in E
rror (LSB)
V
DD
= V
REF
= 5 V
F
SAMPLE
= 100 ksps
V
DD
= V
REF
= 2.7 V
F
SAMPLE
= 50 ksps
0
10
20
30
40
50
60
70
80
90
100
1
10
100
Input Frequency (kHz)
SNR (dB)
V
DD
= V
REF
= 2.7V
F
SAMPLE
= 50 ksps
V
DD
= V
REF
= 5 V
F
SAMPLE
= 100 ksps
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
1
10
100
Input Frequency (kHz)
T
H
D (
d
B)
V
DD
= V
REF
= 5V
F
SAMPLE
= 100 ksps
V
DD
= V
REF
= 2.7V
F
SAMPLE
= 50 ksps
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
-50
-25
0
25
50
75
100
Temperature (°C)
Offse
t Error
(LS
B
)
V
DD
= V
REF
= 5 V
F
SAMPLE
= 100 ksps
V
DD
= V
REF
= 2.7 V
F
SAMPLE
= 50 ksps
0
10
20
30
40
50
60
70
80
90
100
1
10
100
Input Frequency (kHz)
SFDR (dB
)
V
DD
= V
REF
= 5 V
F
SAMPLE
= 100 ksps
V
DD
= V
REF
= 2.7 V
F
SAMPLE
= 50 ksps
0
10
20
30
40
50
60
70
80
-40
-35
-30
-25
-20
-15
-10
-5
0
Input Signal Level (dB)
SINAD
(dB
)
V
DD
= V
REF
= 2.7 V
F
SAMPLE
= 50 ksps
V
DD
= V
REF
= 5 V
F
SAMPLE
= 100 ksps