© 2008 Microchip Technology Inc.
DS21810F-page 1
MCP6271/1R/2/3/4/5
Features
• Gain Bandwidth Product: 2 MHz (typical)
• Supply Current: I
Q
= 170 µA (typical)
• Supply Voltage: 2.0V to 6.0V
• Rail-to-Rail Input/Output
• Extended Temperature Range: –40°C to +125°C
• Available in Single, Dual and Quad Packages
• Parts with Chip Select (CS)
- Single (MCP6273)
- Dual (MCP6275)
Applications
• Automotive
• Portable Equipment
• Photodiode Amplifier
• Analog Filters
• Notebooks and PDAs
• Battery Powered Systems
Available Tools
• SPICE Macro Models
• FilterLab
®
Software
• Mindi™ Circuit Designer & Simulator
• MAPS (Microchip Advanced Part Selector)
• Analog Demonstration and Evaluation Boards
• Application Notes
Description
The Microchip Technology Inc. MCP6271/1R/2/3/4/5
family of operational amplifiers (op amps) provide wide
bandwidth for the current. This family has a 2 MHz
Gain Bandwidth Product (GBWP) and a 65° Phase
Margin. This family also operates from a single supply
voltage as low as 2.0V, while drawing 170 µA (typical)
quiescent current. The MCP6271/1R/2/3/4/5 supports
rail-to-rail input and output swing, with a common mode
input voltage range of V
DD
+ 300 mV to V
SS
– 300 mV.
This family of op amps is designed with Microchip’s
advanced CMOS process.
The MCP6275 has a Chip Select input (CS) for dual op
amps in an 8-pin package and is manufactured by
cascading two op amps (the output of op amp A
connected to the non-inverting input of op amp B). The
CS input puts the device in low power mode.
The MCP6271/1R/2/3/4/5 family operates over the
Extended Temperature Range of –40°C to +125°C,
with a power supply range of 2.0V to 6.0V.
Package Types
V
IN
–
MCP6271
PDIP, SOIC, MSOP
V
DD
1
2
3
4
8
7
6
5
-
+
NC
NC
NC
V
IN
+
V
SS
V
OUT
+ -
- +
-
+
V
IN
–
MCP6273
PDIP, SOIC, MSOP
V
DD
1
2
3
4
8
7
6
5
-
+
NC
CS
NC
V
IN
+
V
SS
V
OUT
V
INA
–
MCP6272
PDIP, SOIC, MSOP
V
OUTB
1
2
3
4
8
7
6
5 V
INB
+
V
DD
V
OUTA
V
INA
+
V
SS
V
INB
–
-
+ -
+
V
INA
–
MCP6274
PDIP, SOIC, TSSOP
V
IND
–
1
2
3
4
14
13
12
11 V
SS
V
OUTD
V
OUTA
V
INA
+
V
DD
V
IND
+
5
6
7
10
9
8
-
+ -
+
+
-
-
+
V
INB
+
V
INC
+
V
OUTC
V
INB
–
V
OUTB
V
INC
–
V
INA
–
MCP6275
PDIP, SOIC, MSOP
V
OUTB
1
2
3
4
8
7
6
5 CS
V
DD
V
OUTA
/V
INB
+
V
INA
+
V
SS
V
INB
–
V
SS
MCP6273
SOT-23-6
CS
1
2
3
6
5
4
V
DD
V
OUT
V
IN
+
V
IN
–
-
+
V
SS
MCP6271
SOT-23-5
1
2
3
5
4
V
DD
V
OUT
V
IN
+
V
IN
–
-
+
V
DD
MCP6271R
SOT-23-5
1
2
3
5
4
V
SS
V
OUT
V
IN
+
V
IN
–
170 µA, 2 MHz Rail-to-Rail Op Amp
MCP6271/1R/2/3/4/5
DS21810F-page 2
© 2008 Microchip Technology Inc.
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
V
DD
– V
SS
........................................................................7.0V
Current at Input Pins ....................................................±2 mA
Analog Inputs (V
IN
+ and V
IN
–) †† .. V
SS
– 1.0V to V
DD
+ 1.0V
All other Inputs and Outputs .......... V
SS
– 0.3V to V
DD
+ 0.3V
Difference Input Voltage ...................................... |V
DD
– V
SS
|
Output Short Circuit Current .................................Continuous
Current at Output and Supply Pins ............................±30 mA
Storage Temperature.................................... –65°C to +150°C
Junction Temperature (T
J
) . .........................................+150°C
ESD Protection On All Pins (HBM/MM)
................ ≥ 4 kV/400V
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
†† See Section 4.1.2 “Input Voltage and Current Limits”.
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, T
A
= +25°C, V
DD
= +2.0V to +5.5V, V
SS
= GND, V
CM
= V
DD
/2,
V
OUT
≈ V
DD
/2, V
L
= V
DD
/2, R
L
= 10 k
Ω to V
L
and CS is tied low. (Refer to
Figure 1-2
and
Figure 1-3
).
Parameters
Sym
Min
Typ
Max
Units
Conditions
Input Offset (Note 1)
Input Offset Voltage
V
OS
–3.0
—
+3.0
mV
V
CM
= V
SS
Input Offset Voltage
(Extended Temperature)
V
OS
–5.0
—
+5.0
mV
T
A
= –40°C to +125°C, V
CM
= V
SS
Input Offset Temperature Drift
ΔV
OS
/
ΔT
A
—
±1.7
—
µV/°C T
A
= –40°C to +125°C, V
CM
= V
SS
Power Supply Rejection Ratio
PSRR
70
90
—
dB
V
CM
= V
SS
Input Bias Current and Impedance
Input Bias Current
I
B
—
±1.0
—
pA
Note 2
At Temperature
I
B
—
50
200
pA
T
A
= +85°C (Note 2)
At Temperature
I
B
—
2
5
nA
T
A
= +125°C (Note 2)
Input Offset Current
I
OS
—
±1.0
—
pA
Note 3
Common Mode Input Impedance
Z
CM
—
10
13
||6
—
Ω||pF Note 3
Differential Input Impedance
Z
DIFF
—
10
13
||3
—
Ω||pF Note 3
Common Mode (Note 4)
Common Mode Input Voltage Range
V
CMR
V
SS
− 0.15
—
V
DD
+ 0.15
V
V
DD
= 2.0V (Note 5)
V
CMR
V
SS
− 0.30
—
V
DD
+ 0.30
V
V
DD
= 5.5V (Note 5)
Common Mode Rejection Ratio
CMRR
70
85
—
dB
V
CM
= –0.3V to 2.5V, V
DD
= 5V
(Note 6)
Common Mode Rejection Ratio
CMRR
65
80
—
dB
V
CM
= –0.3V to 5.3V, V
DD
= 5V
(Note 6)
Open-Loop Gain
DC Open-Loop Gain (Large Signal)
A
OL
90
110
—
dB
V
OUT
= 0.2V to V
DD
– 0.2V,
V
CM
= V
SS
(Note 1)
Note
1:
The MCP6275’s V
CM
for op amp B (pins V
OUTA
/V
INB
+ and V
INB
–) is V
SS
+ 100 mV.
2:
The current at the MCP6275’s V
INB
– pin is specified by I
B
only.
3:
This specification does not apply to the MCP6275’s V
OUTA
/V
INB
+ pin.
4:
The MCP6275’s V
INB
– pin (op amp B) has a common mode input voltage range (V
CMR
) of V
SS
+ 100 mV to
V
DD
– 100 mV. CMRR is not measured for op amp B of the MCP6275. The MCP6275’s V
OUTA
/V
INB
+ pin (op amp B)
has a voltage range specified by V
OH
and V
OL
.
5:
Set by design and characterization.
6:
Does not apply to op amp B of the MCP6275.
7:
All parts with date codes November 2007 and later have been screened to ensure operation at V
DD
= 6.0V. However,
the other minimum and maximum specifications are measured at 2.0V and 5.5V.
© 2008 Microchip Technology Inc.
DS21810F-page 3
MCP6271/1R/2/3/4/5
AC ELECTRICAL SPECIFICATIONS
FIGURE 1-1:
Timing Diagram for the Chip
Select (CS) pin on the MCP6273 and MCP6275.
Output
Maximum Output Voltage Swing
V
OL
, V
OH
V
SS
+ 15
—
V
DD
− 15
mV
0.5V input overdrive (Note 4)
Output Short Circuit Current
I
SC
—
±25
—
mA
Power Supply
Supply Voltage
V
DD
2.0
—
6.0
V
Quiescent Current per Amplifier
I
Q
100
170
240
µA
I
O
= 0
Electrical Characteristics: Unless otherwise indicated, T
A
= +25°C, V
DD
= +2.0V to +5.5V, V
SS
= GND, V
CM
= V
DD
/2,
V
OUT
≈ V
DD
/2, V
L
= V
DD
/2, R
L
= 10 k
Ω to V
L
, C
L
= 60 pF and CS is tied low. (Refer to
Figure 1-2
and
Figure 1-3
).
Parameters
Sym
Min
Typ
Max
Units
Conditions
AC Response
Gain Bandwidth Product
GBWP
—
2.0
—
MHz
Phase Margin
PM
—
65
—
°
G = +1 V/V
Slew Rate
SR
—
0.9
—
V/µs
Noise
Input Noise Voltage
E
ni
—
4.6
—
µV
P-P
f = 0.1 Hz to 10 Hz
Input Noise Voltage Density
e
ni
—
20
—
nV/
√Hz f = 1 kHz
Input Noise Current Density
i
ni
—
3
—
fA/
√Hz f = 1 kHz
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, T
A
= +25°C, V
DD
= +2.0V to +5.5V, V
SS
= GND, V
CM
= V
DD
/2,
V
OUT
≈ V
DD
/2, V
L
= V
DD
/2, R
L
= 10 k
Ω to V
L
and CS is tied low. (Refer to
Figure 1-2
and
Figure 1-3
).
Parameters
Sym
Min
Typ
Max
Units
Conditions
Note
1:
The MCP6275’s V
CM
for op amp B (pins V
OUTA
/V
INB
+ and V
INB
–) is V
SS
+ 100 mV.
2:
The current at the MCP6275’s V
INB
– pin is specified by I
B
only.
3:
This specification does not apply to the MCP6275’s V
OUTA
/V
INB
+ pin.
4:
The MCP6275’s V
INB
– pin (op amp B) has a common mode input voltage range (V
CMR
) of V
SS
+ 100 mV to
V
DD
– 100 mV. CMRR is not measured for op amp B of the MCP6275. The MCP6275’s V
OUTA
/V
INB
+ pin (op amp B)
has a voltage range specified by V
OH
and V
OL
.
5:
Set by design and characterization.
6:
Does not apply to op amp B of the MCP6275.
7:
All parts with date codes November 2007 and later have been screened to ensure operation at V
DD
= 6.0V. However,
the other minimum and maximum specifications are measured at 2.0V and 5.5V.
V
IL
High-Z
t
ON
V
IH
CS
t
OFF
V
OUT
-0.7 µA
High-Z
I
SS
I
CS
0.7 µA
0.7 µA
-0.7 µA
-170 µA
10 nA
(typical)
(typical)
(typical)
(typical)
(typical)
(typical)
MCP6271/1R/2/3/4/5
DS21810F-page 4
© 2008 Microchip Technology Inc.
TEMPERATURE SPECIFICATIONS
MCP6273/MCP6275 CHIP SELECT SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, V
DD
= +2.0V to +5.5V and V
SS
= GND.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Temperature Ranges
Specified Temperature Range
T
A
–40
—
+125
°C
Operating Temperature Range
T
A
–40
—
+125
°C
Note
Storage Temperature Range
T
A
–65
—
+150
°C
Thermal Package Resistances
Thermal Resistance, 5L-SOT-23
θ
JA
—
256
—
°C/W
Thermal Resistance, 6L-SOT-23
θ
JA
—
230
—
°C/W
Thermal Resistance, 8L-PDIP
θ
JA
—
85
—
°C/W
Thermal Resistance, 8L-SOIC
θ
JA
—
163
—
°C/W
Thermal Resistance, 8L-MSOP
θ
JA
—
206
—
°C/W
Thermal Resistance, 14L-PDIP
θ
JA
—
70
—
°C/W
Thermal Resistance, 14L-SOIC
θ
JA
—
120
—
°C/W
Thermal Resistance, 14L-TSSOP
θ
JA
—
100
—
°C/W
Note:
The Junction Temperature (T
J
) must not exceed the Absolute Maximum specification of +150°C.
Electrical Characteristics: Unless otherwise indicated, T
A
= +25°C, V
DD
= +2.0V to +5.5V, V
SS
= GND,
V
CM
= V
DD
/2, V
OUT
≈ V
DD
/2, V
L
= V
DD
/2, R
L
= 10 k
Ω to V
DD
/2, C
L
= 60 pF and CS is tied low.
Parameters
Sym
Min
Typ
Max
Units
Conditions
CS Low Specifications
CS Logic Threshold, Low
V
IL
V
SS
—
0.2V
DD
V
CS Input Current, Low
I
CSL
—
0.01
—
µA
CS = V
SS
CS High Specifications
CS Logic Threshold, High
V
IH
0.8V
DD
—
V
DD
V
CS Input Current, High
I
CSH
—
0.7
2
µA
CS = V
DD
GND Current per Amplifier
I
SS
—
–0.7
—
µA
CS = V
DD
Amplifier Output Leakage
—
—
0.01
—
µA
CS = V
DD
Dynamic Specifications (Note 1)
CS Low to Valid Amplifier
Output, Turn on Time
t
ON
—
4
10
µs
CS Low
≤ 0.2 V
DD
, G = +1 V/V,
V
IN
= V
DD
/2, V
OUT
= 0.9 V
DD
/2,
V
DD
= 5.0V
CS High to Amplifier Output
High-Z
t
OFF
—
0.01
—
µs
CS High
≥ 0.8 V
DD
, G = +1 V/V,
V
IN
= V
DD
/2, V
OUT
= 0.1 V
DD
/2
Hysteresis
V
HYST
—
0.6
—
V
V
DD
= 5V
Note 1:
The input condition (V
IN
) specified applies to both op amp A and B of the MCP6275. The dynamic
specification is tested at the output of op amp B (V
OUTB
).
© 2008 Microchip Technology Inc.
DS21810F-page 5
MCP6271/1R/2/3/4/5
1.1
Test Circuits
The test circuits used for the DC and AC tests are
shown in
Figure 1-2
and
Figure 1-3
. The bypass
capacitors are laid out according to the rules discussed
in Section 4.7 “Supply Bypass”.
FIGURE 1-2:
AC and DC Test Circuit for
Most Non-Inverting Gain Conditions.
FIGURE 1-3:
AC and DC Test Circuit for
Most Inverting Gain Conditions.
V
DD
MCP627X
R
G
R
F
R
N
V
OUT
V
IN
V
DD
/2
1 µF
C
L
R
L
V
L
0.1 µF
V
DD
MCP627X
R
G
R
F
R
N
V
OUT
V
DD
/2
V
IN
1 µF
C
L
R
L
V
L
0.1 µF
MCP6271/1R/2/3/4/5
DS21810F-page 6
© 2008 Microchip Technology Inc.
2.0
TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, T
A
= +25°C, V
DD
= +2.0V to +5.5V, V
SS
= GND, V
CM
= V
DD
/2, V
OUT
≈ V
DD
/2,
V
L
= V
DD
/2, R
L
= 10 k
Ω to V
L
, C
L
= 60 pF and CS is tied low.
FIGURE 2-1:
Input Offset Voltage.
FIGURE 2-2:
Input Bias Current at
T
A
= +85°C.
FIGURE 2-3:
Input Offset Voltage vs.
Common Mode Input Voltage, with V
DD
= 2.0V.
FIGURE 2-4:
Input Offset Voltage Drift.
FIGURE 2-5:
Input Bias Current at
T
A
= +125°C.
FIGURE 2-6:
Input Offset Voltage vs.
Common Mode Input Voltage, with V
DD
= 5.5V.
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
-3.
0
-2.
4
-1.
8
-1.
2
-0.
6
0.
0
0.
6
1.
2
1.
8
2.
4
3.
0
Input Offset Voltage (mV)
Pe
rcen
ta
g
e
of
Occ
u
rr
en
ce
s
832 Samples
V
CM
= V
SS
0%
4%
8%
12%
16%
20%
24%
28%
32%
0
10
20
30
40
50
60
70
80
90 100
Input Bias Current (pA)
Per
cen
ta
g
e
of
Occ
u
rr
en
ces
422 Samples
T
A
= 85°C
-100
-50
0
50
100
150
200
250
300
-0.
4
-0.
2
0.
0
0.
2
0.
4
0.
6
0.
8
1.
0
1.
2
1.
4
1.
6
1.
8
2.
0
2.
2
2.
4
Common Mode Input Voltage (V)
In
p
u
t Of
fse
t V
o
lt
ag
e (µ
V
)
V
DD
= 2.0V
T
A
= +125°C
T
A
= +85°C
T
A
= +25°C
T
A
= -40°C
0%
2%
4%
6%
8%
10%
12%
14%
-1
0
-8
-6
-4
-2
0
2
4
6
8
10
Input Offset Voltage Drift (µV/°C)
Perc
en
ta
g
e
o
f O
ccu
rr
en
ces
832 Samples
V
CM
= V
SS
T
A
= -40°C to +125°C
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
20%
22%
0.
6
0.
8
1.
0
1.
2
1.
4
1.
6
1.
8
2.
0
2.
2
2.
4
2.
6
2.
8
3.
0
Input Bias Current (nA)
Perce
n
ta
g
e
of Oc
curre
n
c
es
422 Samples
T
A
= +125°C
-100
-50
0
50
100
150
200
250
300
-0
.5
0.
0
0.
5
1.
0
1.
5
2.
0
2.
5
3.
0
3.
5
4.
0
4.
5
5.
0
5.
5
6.
0
Common Mode Input Voltage (V)
In
pu
t O
ffs
et
V
o
lt
ag
e (
µ
V)
V
DD
= 5.5V
T
A
= +85°C
T
A
= +25°C
T
A
= -40°C
T
A
= +125°C
© 2008 Microchip Technology Inc.
DS21810F-page 7
MCP6271/1R/2/3/4/5
Note: Unless otherwise indicated, T
A
= +25°C, V
DD
= +2.0V to +5.5V, V
SS
= GND, V
CM
= V
DD
/2, V
OUT
≈ V
DD
/2,
V
L
= V
DD
/2, R
L
= 10 k
Ω to V
L
, C
L
= 60 pF and CS is tied low.
FIGURE 2-7:
Common Mode Input
Voltage Range Lower Limit vs. Temperature.
FIGURE 2-8:
Input Offset Voltage vs.
Output Voltage.
FIGURE 2-9:
CMRR, PSRR vs.
Frequency.
FIGURE 2-10:
Common Mode Input
Voltage Range Upper Limit vs. Temperature.
FIGURE 2-11:
Input Bias, Input Offset
Currents vs. Temperature.
FIGURE 2-12:
CMRR, PSRR vs.
Temperature.
-0.50
-0.45
-0.40
-0.35
-0.30
-0.25
-0.20
-0.15
-0.10
-0.05
0.00
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
C
o
mmon Mo
de Inpu
t
Volta
g
e
Ra
nge
Lim
it
(V)
Typical lower (V
CM
– V
SS
) limit
V
DD
= 5.5V
V
DD
= 2.0V
-100
-50
0
50
100
150
200
250
300
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
In
p
u
t O
ff
s
e
t Vo
lt
ag
e
(µ
V)
V
DD
= 2.0V
V
CM
= V
SS
Representative Part
V
DD
= 5.5V
20
30
40
50
60
70
80
90
100
110
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06
Frequency (Hz)
CM
RR
, P
S
R
R
(
d
B)
1
10k
100k
1M
100
10
1k
PSRR–
PSRR+
CMRR
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
C
o
mmon Mo
de Inpu
t
Volta
g
e
Ra
nge
Lim
it (V)
Typical upper (V
CM
– V
DD
) limit
V
DD
= 5.5V
V
DD
= 2.0V
1
10
100
1,000
10,000
45
55
65
75
85
95
105 115 125
Ambient Temperature (°C)
In
p
u
t
B
ias
, Of
fset
Cu
rren
ts
(p
A
)
Input Bias Current
V
CM
= V
DD
V
DD
= 5.5V
Input Offset Current
60
70
80
90
100
110
120
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
P
S
R
R, C
M
RR
(dB
)
PSRR
(V
CM
= V
SS
)
CMRR
MCP6271/1R/2/3/4/5
DS21810F-page 8
© 2008 Microchip Technology Inc.
Note: Unless otherwise indicated, T
A
= +25°C, V
DD
= +2.0V to +5.5V, V
SS
= GND, V
CM
= V
DD
/2, V
OUT
≈ V
DD
/2,
V
L
= V
DD
/2, R
L
= 10 k
Ω to V
L
, C
L
= 60 pF and CS is tied low.
FIGURE 2-13:
Input Bias, Offset Currents
vs. Common Mode Input Voltage, with
T
A
= +85°C.
FIGURE 2-14:
Quiescent Current vs.
Supply Voltage.
FIGURE 2-15:
Open-Loop Gain, Phase vs.
Frequency.
FIGURE 2-16:
Input Bias, Offset Currents
vs. Common Mode Input Voltage, with
T
A
= +125°C.
FIGURE 2-17:
Output Voltage Headroom
vs. Output Current Magnitude.
FIGURE 2-18:
Gain Bandwidth Product,
Phase Margin vs. Temperature.
-25
-15
-5
5
15
25
35
45
55
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
Inpu
t
B
ias
, Offs
et C
u
rre
n
ts
(pA
)
T
A
= 85°C
V
DD
= 5.5V
Input Bias Current
Input Offset Current
0
50
100
150
200
250
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
Qu
ies
cen
t C
u
rren
t
(µA
/a
m
pl
ifi
e
r)
T
A
= +125°C
T
A
= +85°C
T
A
= +25°C
T
A
= -40°C
-20
0
20
40
60
80
100
120
1.
E-
01
1.
E+
00
1.
E+
01
1.
E+
02
1.
E+
03
1.
E+
04
1.
E+
05
1.
E+
06
1.
E+
07
1.
E+
08
Frequency (Hz)
Op
en
-L
o
o
p
Ga
in
(
d
B)
-210
-180
-150
-120
-90
-60
-30
0
Op
en
-L
oo
p
Ph
as
e (
°)
Gain
Phase
0.1
1
10 100 1k 10k 100k 1M 10M 100M
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
In
p
u
t
B
ias
, Of
fset
Cu
rren
ts
(n
A
)
T
A
= 125°C
V
DD
= 5.5V
Input Bias Current
Input Offset Current
1
10
100
1000
0.01
0.1
1
10
Output Current Magnitude (mA)
O
u
p
u
t V
o
lt
ag
e He
a
d
room
(m
V)
V
OL
– V
SS
V
DD
– V
OH
0.0
0.5
1.0
1.5
2.0
2.5
3.0
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
G
a
in B
a
ndwi
d
th
Pr
o
duc
t
(MHz
)
50
55
60
65
70
75
80
P
h
a
se Ma
rg
in
(
°)
PM, V
DD
= 5.5V
V
DD
= 2.0V
GBWP, V
DD
= 5.5V
V
DD
= 2.0V
© 2008 Microchip Technology Inc.
DS21810F-page 9
MCP6271/1R/2/3/4/5
Note: Unless otherwise indicated, T
A
= +25°C, V
DD
= +2.0V to +5.5V, V
SS
= GND, V
CM
= V
DD
/2, V
OUT
≈ V
DD
/2,
V
L
= V
DD
/2, R
L
= 10 k
Ω to V
L
, C
L
= 60 pF and CS is tied low.
FIGURE 2-19:
Maximum Output Voltage
Swing vs. Frequency.
FIGURE 2-20:
Input Noise Voltage Density
vs. Frequency.
FIGURE 2-21:
Output Short Circuit Current
vs. Supply Voltage.
FIGURE 2-22:
Slew Rate vs. Temperature.
FIGURE 2-23:
Input Noise Voltage Density
vs. Common Mode Input Voltage, with f = 1 kHz.
FIGURE 2-24:
Channel-to-Channel
Separation vs. Frequency (MCP6272 and
MCP6274).
0.1
1
10
1.
E+
03
1.
E+
04
1.
E+
05
1.
E+
06
1.
E+
07
Frequency (Hz)
Ma
xi
m
u
m
O
u
tput
V
o
lt
ag
e
Swi
n
g (
V
P-
P
)
V
DD
= 2.0V
1k
10k
100k
1M
V
DD
= 5.5V
10M
10
100
1,000
1.E-
01
1.E+
00
1.E+
01
1.E+
02
1.E+
03
1.E+
04
1.E+
05
1.E+
06
Frequency (Hz)
Input Noise Voltage Density
(nV/
Hz)
0.1
100
10
1k
100k
10k
1M
1
0
5
10
15
20
25
30
35
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
Ouptu
t Sh
ort-C
ir
c
u
it C
u
rren
t
(mA
)
T
A
= +125°C
T
A
= +85°C
T
A
= +25°C
T
A
= -40°C
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
S
le
w
R
a
te
(V
/µ
s)
Falling Edge
V
DD
= 5.5V
V
DD
= 2.0V
Rising Edge
0
5
10
15
20
25
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Common Mode Input Voltage (V)
Input Noise Voltage Density
(nV/
¥
Hz)
f = 1 kHz
V
DD
= 5.0V
100
110
120
130
140
1
10
100
Frequency (kHz)
C
h
a
nne
l-
to-C
ha
nne
l
S
e
p
a
ra
ti
on (dB
)
MCP6271/1R/2/3/4/5
DS21810F-page 10
© 2008 Microchip Technology Inc.
Note: Unless otherwise indicated, T
A
= +25°C, V
DD
= +2.0V to +5.5V, V
SS
= GND, V
CM
= V
DD
/2, V
OUT
≈ V
DD
/2,
V
L
= V
DD
/2, R
L
= 10 k
Ω to V
L
, C
L
= 60 pF and CS is tied low.
FIGURE 2-25:
Quiescent Current vs. Chip
Select (CS) Voltage, with V
DD
= 2.0V (MCP6273
and MCP6275 only).
FIGURE 2-26:
Large Signal Non-inverting
Pulse Response.
FIGURE 2-27:
Small Signal Non-inverting
Pulse Response.
FIGURE 2-28:
Quiescent Current vs. Chip
Select (CS) Voltage, with V
DD
= 5.5V (MCP6273
and MCP6275 only).
FIGURE 2-29:
Large Signal Inverting Pulse
Response.
FIGURE 2-30:
Small Signal Inverting Pulse
Response.
0
50
100
150
200
250
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Chip Select Voltage (V)
Qu
iesc
en
t Cu
rre
nt
(µ
A/
ampl
if
ie
r)
Hysteresis
Op Amp turns Off
Op Amp turns On
V
DD
= 2.0V
CS swept
High-to-Low
CS swept
Low-to-High
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Time (5 µs/div)
Out
put Volta
g
e (V)
G = +1 V/V
V
DD
= 5.0V
Time (2 µs/div)
O
u
tp
ut V
o
lt
ag
e (1
0 m
V
/d
iv
)
G = +1 V/V
0
100
200
300
400
500
600
700
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Chip Select Voltage (V)
Q
u
ies
cen
t C
u
rr
en
t
(µA
/a
m
pl
ifi
e
r)
Hysteresis
Op Amp
turns
On/Off
CS swept
Low-to-High
CS swe
p
t
H
ig
h
-to
-Low
V
DD
= 5.5V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Time (5 µs/div)
Ou
tp
ut
Vol
tag
e
(V
)
G = -1 V/V
V
DD
= 5.0V
Time (2 µs/div)
Ou
tp
ut
Vol
tag
e (
1
0 m
V
/d
iv
)
G = -1 V/V